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/*
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* MIPS emulation micro-operations for qemu.
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*
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* Copyright (c) 2004-2005 Jocelyn Mayer
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* Copyright (c) 2006 Marius Groeger (FPU operations)
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "config.h" |
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#include "exec.h" |
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#ifndef CALL_FROM_TB0
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#define CALL_FROM_TB0(func) func();
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#endif
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#ifndef CALL_FROM_TB1
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#define CALL_FROM_TB1(func, arg0) func(arg0);
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#endif
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#ifndef CALL_FROM_TB1_CONST16
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#define CALL_FROM_TB1_CONST16(func, arg0) CALL_FROM_TB1(func, arg0);
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#endif
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#ifndef CALL_FROM_TB2
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#define CALL_FROM_TB2(func, arg0, arg1) func(arg0, arg1);
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#endif
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#ifndef CALL_FROM_TB2_CONST16
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#define CALL_FROM_TB2_CONST16(func, arg0, arg1) \
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CALL_FROM_TB2(func, arg0, arg1); |
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#endif
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#ifndef CALL_FROM_TB3
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#define CALL_FROM_TB3(func, arg0, arg1, arg2) func(arg0, arg1, arg2);
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#endif
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#ifndef CALL_FROM_TB4
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#define CALL_FROM_TB4(func, arg0, arg1, arg2, arg3) \
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func(arg0, arg1, arg2, arg3); |
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#endif
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#define REG 1 |
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#include "op_template.c" |
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#undef REG
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#define REG 2 |
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#include "op_template.c" |
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#undef REG
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#define REG 3 |
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#include "op_template.c" |
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#undef REG
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#define REG 4 |
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#include "op_template.c" |
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#undef REG
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#define REG 5 |
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#include "op_template.c" |
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#undef REG
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#define REG 6 |
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#include "op_template.c" |
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#undef REG
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#define REG 7 |
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#include "op_template.c" |
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#undef REG
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#define REG 8 |
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#include "op_template.c" |
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#undef REG
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#define REG 9 |
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#include "op_template.c" |
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#undef REG
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#define REG 10 |
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#include "op_template.c" |
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#undef REG
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#define REG 11 |
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#include "op_template.c" |
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#undef REG
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#define REG 12 |
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#include "op_template.c" |
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#undef REG
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#define REG 13 |
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#include "op_template.c" |
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#undef REG
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#define REG 14 |
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#include "op_template.c" |
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#undef REG
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#define REG 15 |
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#include "op_template.c" |
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#undef REG
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#define REG 16 |
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#include "op_template.c" |
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#undef REG
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#define REG 17 |
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#include "op_template.c" |
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#undef REG
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#define REG 18 |
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#include "op_template.c" |
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#undef REG
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#define REG 19 |
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#include "op_template.c" |
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#undef REG
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#define REG 20 |
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#include "op_template.c" |
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#undef REG
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#define REG 21 |
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#include "op_template.c" |
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#undef REG
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#define REG 22 |
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#include "op_template.c" |
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#undef REG
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#define REG 23 |
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#include "op_template.c" |
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#undef REG
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#define REG 24 |
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#include "op_template.c" |
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#undef REG
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#define REG 25 |
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#include "op_template.c" |
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#undef REG
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#define REG 26 |
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#include "op_template.c" |
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#undef REG
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#define REG 27 |
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#include "op_template.c" |
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#undef REG
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#define REG 28 |
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#include "op_template.c" |
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#undef REG
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#define REG 29 |
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#include "op_template.c" |
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#undef REG
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#define REG 30 |
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#include "op_template.c" |
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#undef REG
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#define REG 31 |
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#include "op_template.c" |
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#undef REG
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#define TN T0
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#include "op_template.c" |
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#undef TN
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#define TN T1
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#include "op_template.c" |
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#undef TN
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#define TN T2
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#include "op_template.c" |
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#undef TN
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#ifdef MIPS_USES_FPU
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#define SFREG 0 |
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#define DFREG 0 |
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#include "fop_template.c" |
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#undef SFREG
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#undef DFREG
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#define SFREG 1 |
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#include "fop_template.c" |
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#undef SFREG
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#define SFREG 2 |
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#define DFREG 2 |
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#include "fop_template.c" |
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#undef SFREG
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#undef DFREG
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#define SFREG 3 |
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#include "fop_template.c" |
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#undef SFREG
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#define SFREG 4 |
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#define DFREG 4 |
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#include "fop_template.c" |
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#undef SFREG
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#undef DFREG
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#define SFREG 5 |
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#include "fop_template.c" |
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#undef SFREG
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#define SFREG 6 |
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#define DFREG 6 |
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#include "fop_template.c" |
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#undef SFREG
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#undef DFREG
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#define SFREG 7 |
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#include "fop_template.c" |
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#undef SFREG
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#define SFREG 8 |
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#define DFREG 8 |
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#include "fop_template.c" |
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#undef SFREG
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#undef DFREG
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#define SFREG 9 |
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#include "fop_template.c" |
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#undef SFREG
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#define SFREG 10 |
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#define DFREG 10 |
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#include "fop_template.c" |
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#undef SFREG
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#undef DFREG
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#define SFREG 11 |
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#include "fop_template.c" |
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#undef SFREG
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#define SFREG 12 |
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#define DFREG 12 |
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#include "fop_template.c" |
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#undef SFREG
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#undef DFREG
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#define SFREG 13 |
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#include "fop_template.c" |
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#undef SFREG
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#define SFREG 14 |
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#define DFREG 14 |
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#include "fop_template.c" |
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#undef SFREG
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#undef DFREG
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#define SFREG 15 |
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#include "fop_template.c" |
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#undef SFREG
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#define SFREG 16 |
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#define DFREG 16 |
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#include "fop_template.c" |
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#undef SFREG
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#undef DFREG
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#define SFREG 17 |
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#include "fop_template.c" |
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#undef SFREG
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#define SFREG 18 |
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#define DFREG 18 |
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#include "fop_template.c" |
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#undef SFREG
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#undef DFREG
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#define SFREG 19 |
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#include "fop_template.c" |
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#undef SFREG
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#define SFREG 20 |
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#define DFREG 20 |
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#include "fop_template.c" |
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#undef SFREG
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#undef DFREG
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#define SFREG 21 |
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#include "fop_template.c" |
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#undef SFREG
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#define SFREG 22 |
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#define DFREG 22 |
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#include "fop_template.c" |
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#undef SFREG
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#undef DFREG
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#define SFREG 23 |
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#include "fop_template.c" |
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#undef SFREG
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#define SFREG 24 |
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#define DFREG 24 |
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#include "fop_template.c" |
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#undef SFREG
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#undef DFREG
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#define SFREG 25 |
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#include "fop_template.c" |
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#undef SFREG
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#define SFREG 26 |
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#define DFREG 26 |
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#include "fop_template.c" |
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#undef SFREG
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#undef DFREG
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#define SFREG 27 |
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#include "fop_template.c" |
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#undef SFREG
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#define SFREG 28 |
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#define DFREG 28 |
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#include "fop_template.c" |
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#undef SFREG
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#undef DFREG
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#define SFREG 29 |
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#include "fop_template.c" |
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#undef SFREG
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#define SFREG 30 |
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#define DFREG 30 |
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#include "fop_template.c" |
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#undef SFREG
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#undef DFREG
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#define SFREG 31 |
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#include "fop_template.c" |
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#undef SFREG
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#define FTN
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#include "fop_template.c" |
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#undef FTN
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#endif
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void op_dup_T0 (void) |
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{
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T2 = T0; |
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RETURN(); |
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} |
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|
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void op_load_HI (void) |
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{
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T0 = env->HI; |
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RETURN(); |
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} |
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|
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void op_store_HI (void) |
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{
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env->HI = T0; |
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RETURN(); |
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} |
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|
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void op_load_LO (void) |
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{
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T0 = env->LO; |
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RETURN(); |
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} |
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|
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void op_store_LO (void) |
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{
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env->LO = T0; |
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RETURN(); |
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} |
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/* Load and store */
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#define MEMSUFFIX _raw
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#include "op_mem.c" |
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#undef MEMSUFFIX
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#if !defined(CONFIG_USER_ONLY)
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#define MEMSUFFIX _user
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#include "op_mem.c" |
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#undef MEMSUFFIX
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#define MEMSUFFIX _kernel
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#include "op_mem.c" |
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#undef MEMSUFFIX
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#endif
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/* Arithmetic */
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void op_add (void) |
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{
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T0 += T1; |
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RETURN(); |
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} |
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|
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void op_addo (void) |
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{
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target_ulong tmp; |
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tmp = T0; |
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T0 += T1; |
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if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 31) { |
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/* operands of same sign, result different sign */
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CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW); |
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} |
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RETURN(); |
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} |
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|
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void op_sub (void) |
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{
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T0 -= T1; |
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RETURN(); |
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} |
| 359 |
|
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void op_subo (void) |
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{
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target_ulong tmp; |
| 363 |
|
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tmp = T0; |
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T0 = (int32_t)T0 - (int32_t)T1; |
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if (((tmp ^ T1) & (tmp ^ T0)) >> 31) { |
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/* operands of different sign, first operand and result different sign */
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CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW); |
| 369 |
} |
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RETURN(); |
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} |
| 372 |
|
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void op_mul (void) |
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{
|
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T0 = (int32_t)T0 * (int32_t)T1; |
| 376 |
RETURN(); |
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} |
| 378 |
|
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void op_div (void) |
| 380 |
{
|
| 381 |
if (T1 != 0) { |
| 382 |
env->LO = (int32_t)T0 / (int32_t)T1; |
| 383 |
env->HI = (int32_t)T0 % (int32_t)T1; |
| 384 |
} |
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RETURN(); |
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} |
| 387 |
|
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void op_divu (void) |
| 389 |
{
|
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if (T1 != 0) { |
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env->LO = T0 / T1; |
| 392 |
env->HI = T0 % T1; |
| 393 |
} |
| 394 |
RETURN(); |
| 395 |
} |
| 396 |
|
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/* Logical */
|
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void op_and (void) |
| 399 |
{
|
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T0 &= T1; |
| 401 |
RETURN(); |
| 402 |
} |
| 403 |
|
| 404 |
void op_nor (void) |
| 405 |
{
|
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T0 = ~(T0 | T1); |
| 407 |
RETURN(); |
| 408 |
} |
| 409 |
|
| 410 |
void op_or (void) |
| 411 |
{
|
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T0 |= T1; |
| 413 |
RETURN(); |
| 414 |
} |
| 415 |
|
| 416 |
void op_xor (void) |
| 417 |
{
|
| 418 |
T0 ^= T1; |
| 419 |
RETURN(); |
| 420 |
} |
| 421 |
|
| 422 |
void op_sll (void) |
| 423 |
{
|
| 424 |
T0 = T0 << T1; |
| 425 |
RETURN(); |
| 426 |
} |
| 427 |
|
| 428 |
void op_sra (void) |
| 429 |
{
|
| 430 |
T0 = (int32_t)T0 >> T1; |
| 431 |
RETURN(); |
| 432 |
} |
| 433 |
|
| 434 |
void op_srl (void) |
| 435 |
{
|
| 436 |
T0 = T0 >> T1; |
| 437 |
RETURN(); |
| 438 |
} |
| 439 |
|
| 440 |
void op_sllv (void) |
| 441 |
{
|
| 442 |
T0 = T1 << (T0 & 0x1F);
|
| 443 |
RETURN(); |
| 444 |
} |
| 445 |
|
| 446 |
void op_srav (void) |
| 447 |
{
|
| 448 |
T0 = (int32_t)T1 >> (T0 & 0x1F);
|
| 449 |
RETURN(); |
| 450 |
} |
| 451 |
|
| 452 |
void op_srlv (void) |
| 453 |
{
|
| 454 |
T0 = T1 >> (T0 & 0x1F);
|
| 455 |
RETURN(); |
| 456 |
} |
| 457 |
|
| 458 |
void op_clo (void) |
| 459 |
{
|
| 460 |
int n;
|
| 461 |
|
| 462 |
if (T0 == (target_ulong)-1) { |
| 463 |
T0 = 32;
|
| 464 |
} else {
|
| 465 |
for (n = 0; n < 32; n++) { |
| 466 |
if (!(T0 & (1 << 31))) |
| 467 |
break;
|
| 468 |
T0 = T0 << 1;
|
| 469 |
} |
| 470 |
T0 = n; |
| 471 |
} |
| 472 |
RETURN(); |
| 473 |
} |
| 474 |
|
| 475 |
void op_clz (void) |
| 476 |
{
|
| 477 |
int n;
|
| 478 |
|
| 479 |
if (T0 == 0) { |
| 480 |
T0 = 32;
|
| 481 |
} else {
|
| 482 |
for (n = 0; n < 32; n++) { |
| 483 |
if (T0 & (1 << 31)) |
| 484 |
break;
|
| 485 |
T0 = T0 << 1;
|
| 486 |
} |
| 487 |
T0 = n; |
| 488 |
} |
| 489 |
RETURN(); |
| 490 |
} |
| 491 |
|
| 492 |
/* 64 bits arithmetic */
|
| 493 |
#if (HOST_LONG_BITS == 64) |
| 494 |
static inline uint64_t get_HILO (void) |
| 495 |
{
|
| 496 |
return ((uint64_t)env->HI << 32) | (uint64_t)env->LO; |
| 497 |
} |
| 498 |
|
| 499 |
static inline void set_HILO (uint64_t HILO) |
| 500 |
{
|
| 501 |
env->LO = HILO & 0xFFFFFFFF;
|
| 502 |
env->HI = HILO >> 32;
|
| 503 |
} |
| 504 |
|
| 505 |
void op_mult (void) |
| 506 |
{
|
| 507 |
set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
| 508 |
RETURN(); |
| 509 |
} |
| 510 |
|
| 511 |
void op_multu (void) |
| 512 |
{
|
| 513 |
set_HILO((uint64_t)T0 * (uint64_t)T1); |
| 514 |
RETURN(); |
| 515 |
} |
| 516 |
|
| 517 |
void op_madd (void) |
| 518 |
{
|
| 519 |
int64_t tmp; |
| 520 |
|
| 521 |
tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
| 522 |
set_HILO((int64_t)get_HILO() + tmp); |
| 523 |
RETURN(); |
| 524 |
} |
| 525 |
|
| 526 |
void op_maddu (void) |
| 527 |
{
|
| 528 |
uint64_t tmp; |
| 529 |
|
| 530 |
tmp = ((uint64_t)T0 * (uint64_t)T1); |
| 531 |
set_HILO(get_HILO() + tmp); |
| 532 |
RETURN(); |
| 533 |
} |
| 534 |
|
| 535 |
void op_msub (void) |
| 536 |
{
|
| 537 |
int64_t tmp; |
| 538 |
|
| 539 |
tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
| 540 |
set_HILO((int64_t)get_HILO() - tmp); |
| 541 |
RETURN(); |
| 542 |
} |
| 543 |
|
| 544 |
void op_msubu (void) |
| 545 |
{
|
| 546 |
uint64_t tmp; |
| 547 |
|
| 548 |
tmp = ((uint64_t)T0 * (uint64_t)T1); |
| 549 |
set_HILO(get_HILO() - tmp); |
| 550 |
RETURN(); |
| 551 |
} |
| 552 |
#else
|
| 553 |
void op_mult (void) |
| 554 |
{
|
| 555 |
CALL_FROM_TB0(do_mult); |
| 556 |
RETURN(); |
| 557 |
} |
| 558 |
|
| 559 |
void op_multu (void) |
| 560 |
{
|
| 561 |
CALL_FROM_TB0(do_multu); |
| 562 |
RETURN(); |
| 563 |
} |
| 564 |
|
| 565 |
void op_madd (void) |
| 566 |
{
|
| 567 |
CALL_FROM_TB0(do_madd); |
| 568 |
RETURN(); |
| 569 |
} |
| 570 |
|
| 571 |
void op_maddu (void) |
| 572 |
{
|
| 573 |
CALL_FROM_TB0(do_maddu); |
| 574 |
RETURN(); |
| 575 |
} |
| 576 |
|
| 577 |
void op_msub (void) |
| 578 |
{
|
| 579 |
CALL_FROM_TB0(do_msub); |
| 580 |
RETURN(); |
| 581 |
} |
| 582 |
|
| 583 |
void op_msubu (void) |
| 584 |
{
|
| 585 |
CALL_FROM_TB0(do_msubu); |
| 586 |
RETURN(); |
| 587 |
} |
| 588 |
#endif
|
| 589 |
|
| 590 |
/* Conditional moves */
|
| 591 |
void op_movn (void) |
| 592 |
{
|
| 593 |
if (T1 != 0) |
| 594 |
env->gpr[PARAM1] = T0; |
| 595 |
RETURN(); |
| 596 |
} |
| 597 |
|
| 598 |
void op_movz (void) |
| 599 |
{
|
| 600 |
if (T1 == 0) |
| 601 |
env->gpr[PARAM1] = T0; |
| 602 |
RETURN(); |
| 603 |
} |
| 604 |
|
| 605 |
/* Tests */
|
| 606 |
#define OP_COND(name, cond) \
|
| 607 |
void glue(op_, name) (void) \ |
| 608 |
{ \
|
| 609 |
if (cond) { \
|
| 610 |
T0 = 1; \
|
| 611 |
} else { \
|
| 612 |
T0 = 0; \
|
| 613 |
} \ |
| 614 |
RETURN(); \ |
| 615 |
} |
| 616 |
|
| 617 |
OP_COND(eq, T0 == T1); |
| 618 |
OP_COND(ne, T0 != T1); |
| 619 |
OP_COND(ge, (int32_t)T0 >= (int32_t)T1); |
| 620 |
OP_COND(geu, T0 >= T1); |
| 621 |
OP_COND(lt, (int32_t)T0 < (int32_t)T1); |
| 622 |
OP_COND(ltu, T0 < T1); |
| 623 |
OP_COND(gez, (int32_t)T0 >= 0);
|
| 624 |
OP_COND(gtz, (int32_t)T0 > 0);
|
| 625 |
OP_COND(lez, (int32_t)T0 <= 0);
|
| 626 |
OP_COND(ltz, (int32_t)T0 < 0);
|
| 627 |
|
| 628 |
/* Branchs */
|
| 629 |
//#undef USE_DIRECT_JUMP
|
| 630 |
|
| 631 |
void OPPROTO op_goto_tb0(void) |
| 632 |
{
|
| 633 |
GOTO_TB(op_goto_tb0, PARAM1, 0);
|
| 634 |
} |
| 635 |
|
| 636 |
void OPPROTO op_goto_tb1(void) |
| 637 |
{
|
| 638 |
GOTO_TB(op_goto_tb1, PARAM1, 1);
|
| 639 |
} |
| 640 |
|
| 641 |
/* Branch to register */
|
| 642 |
void op_save_breg_target (void) |
| 643 |
{
|
| 644 |
env->btarget = T2; |
| 645 |
} |
| 646 |
|
| 647 |
void op_restore_breg_target (void) |
| 648 |
{
|
| 649 |
T2 = env->btarget; |
| 650 |
} |
| 651 |
|
| 652 |
void op_breg (void) |
| 653 |
{
|
| 654 |
env->PC = T2; |
| 655 |
RETURN(); |
| 656 |
} |
| 657 |
|
| 658 |
void op_save_btarget (void) |
| 659 |
{
|
| 660 |
env->btarget = PARAM1; |
| 661 |
RETURN(); |
| 662 |
} |
| 663 |
|
| 664 |
/* Conditional branch */
|
| 665 |
void op_set_bcond (void) |
| 666 |
{
|
| 667 |
T2 = T0; |
| 668 |
RETURN(); |
| 669 |
} |
| 670 |
|
| 671 |
void op_save_bcond (void) |
| 672 |
{
|
| 673 |
env->bcond = T2; |
| 674 |
RETURN(); |
| 675 |
} |
| 676 |
|
| 677 |
void op_restore_bcond (void) |
| 678 |
{
|
| 679 |
T2 = env->bcond; |
| 680 |
RETURN(); |
| 681 |
} |
| 682 |
|
| 683 |
void op_jnz_T2 (void) |
| 684 |
{
|
| 685 |
if (T2)
|
| 686 |
GOTO_LABEL_PARAM(1);
|
| 687 |
RETURN(); |
| 688 |
} |
| 689 |
|
| 690 |
/* CP0 functions */
|
| 691 |
void op_mfc0_index (void) |
| 692 |
{
|
| 693 |
T0 = env->CP0_index; |
| 694 |
RETURN(); |
| 695 |
} |
| 696 |
|
| 697 |
void op_mfc0_random (void) |
| 698 |
{
|
| 699 |
CALL_FROM_TB0(do_mfc0_random); |
| 700 |
RETURN(); |
| 701 |
} |
| 702 |
|
| 703 |
void op_mfc0_entrylo0 (void) |
| 704 |
{
|
| 705 |
T0 = env->CP0_EntryLo0; |
| 706 |
RETURN(); |
| 707 |
} |
| 708 |
|
| 709 |
void op_mfc0_entrylo1 (void) |
| 710 |
{
|
| 711 |
T0 = env->CP0_EntryLo1; |
| 712 |
RETURN(); |
| 713 |
} |
| 714 |
|
| 715 |
void op_mfc0_context (void) |
| 716 |
{
|
| 717 |
T0 = env->CP0_Context; |
| 718 |
RETURN(); |
| 719 |
} |
| 720 |
|
| 721 |
void op_mfc0_pagemask (void) |
| 722 |
{
|
| 723 |
T0 = env->CP0_PageMask; |
| 724 |
RETURN(); |
| 725 |
} |
| 726 |
|
| 727 |
void op_mfc0_wired (void) |
| 728 |
{
|
| 729 |
T0 = env->CP0_Wired; |
| 730 |
RETURN(); |
| 731 |
} |
| 732 |
|
| 733 |
void op_mfc0_badvaddr (void) |
| 734 |
{
|
| 735 |
T0 = env->CP0_BadVAddr; |
| 736 |
RETURN(); |
| 737 |
} |
| 738 |
|
| 739 |
void op_mfc0_count (void) |
| 740 |
{
|
| 741 |
CALL_FROM_TB0(do_mfc0_count); |
| 742 |
RETURN(); |
| 743 |
} |
| 744 |
|
| 745 |
void op_mfc0_entryhi (void) |
| 746 |
{
|
| 747 |
T0 = env->CP0_EntryHi; |
| 748 |
RETURN(); |
| 749 |
} |
| 750 |
|
| 751 |
void op_mfc0_compare (void) |
| 752 |
{
|
| 753 |
T0 = env->CP0_Compare; |
| 754 |
RETURN(); |
| 755 |
} |
| 756 |
|
| 757 |
void op_mfc0_status (void) |
| 758 |
{
|
| 759 |
T0 = env->CP0_Status; |
| 760 |
if (env->hflags & MIPS_HFLAG_UM)
|
| 761 |
T0 |= (1 << CP0St_UM);
|
| 762 |
if (env->hflags & MIPS_HFLAG_ERL)
|
| 763 |
T0 |= (1 << CP0St_ERL);
|
| 764 |
if (env->hflags & MIPS_HFLAG_EXL)
|
| 765 |
T0 |= (1 << CP0St_EXL);
|
| 766 |
RETURN(); |
| 767 |
} |
| 768 |
|
| 769 |
void op_mfc0_cause (void) |
| 770 |
{
|
| 771 |
T0 = env->CP0_Cause; |
| 772 |
RETURN(); |
| 773 |
} |
| 774 |
|
| 775 |
void op_mfc0_epc (void) |
| 776 |
{
|
| 777 |
T0 = env->CP0_EPC; |
| 778 |
RETURN(); |
| 779 |
} |
| 780 |
|
| 781 |
void op_mfc0_prid (void) |
| 782 |
{
|
| 783 |
T0 = env->CP0_PRid; |
| 784 |
RETURN(); |
| 785 |
} |
| 786 |
|
| 787 |
void op_mfc0_config0 (void) |
| 788 |
{
|
| 789 |
T0 = env->CP0_Config0; |
| 790 |
RETURN(); |
| 791 |
} |
| 792 |
|
| 793 |
void op_mfc0_config1 (void) |
| 794 |
{
|
| 795 |
T0 = env->CP0_Config1; |
| 796 |
RETURN(); |
| 797 |
} |
| 798 |
|
| 799 |
void op_mfc0_lladdr (void) |
| 800 |
{
|
| 801 |
T0 = env->CP0_LLAddr >> 4;
|
| 802 |
RETURN(); |
| 803 |
} |
| 804 |
|
| 805 |
void op_mfc0_watchlo (void) |
| 806 |
{
|
| 807 |
T0 = env->CP0_WatchLo; |
| 808 |
RETURN(); |
| 809 |
} |
| 810 |
|
| 811 |
void op_mfc0_watchhi (void) |
| 812 |
{
|
| 813 |
T0 = env->CP0_WatchHi; |
| 814 |
RETURN(); |
| 815 |
} |
| 816 |
|
| 817 |
void op_mfc0_debug (void) |
| 818 |
{
|
| 819 |
T0 = env->CP0_Debug; |
| 820 |
if (env->hflags & MIPS_HFLAG_DM)
|
| 821 |
T0 |= 1 << CP0DB_DM;
|
| 822 |
RETURN(); |
| 823 |
} |
| 824 |
|
| 825 |
void op_mfc0_depc (void) |
| 826 |
{
|
| 827 |
T0 = env->CP0_DEPC; |
| 828 |
RETURN(); |
| 829 |
} |
| 830 |
|
| 831 |
void op_mfc0_taglo (void) |
| 832 |
{
|
| 833 |
T0 = env->CP0_TagLo; |
| 834 |
RETURN(); |
| 835 |
} |
| 836 |
|
| 837 |
void op_mfc0_datalo (void) |
| 838 |
{
|
| 839 |
T0 = env->CP0_DataLo; |
| 840 |
RETURN(); |
| 841 |
} |
| 842 |
|
| 843 |
void op_mfc0_errorepc (void) |
| 844 |
{
|
| 845 |
T0 = env->CP0_ErrorEPC; |
| 846 |
RETURN(); |
| 847 |
} |
| 848 |
|
| 849 |
void op_mfc0_desave (void) |
| 850 |
{
|
| 851 |
T0 = env->CP0_DESAVE; |
| 852 |
RETURN(); |
| 853 |
} |
| 854 |
|
| 855 |
void op_mtc0_index (void) |
| 856 |
{
|
| 857 |
env->CP0_index = (env->CP0_index & 0x80000000) | (T0 & 0x0000000F); |
| 858 |
RETURN(); |
| 859 |
} |
| 860 |
|
| 861 |
void op_mtc0_entrylo0 (void) |
| 862 |
{
|
| 863 |
env->CP0_EntryLo0 = T0 & 0x3FFFFFFF;
|
| 864 |
RETURN(); |
| 865 |
} |
| 866 |
|
| 867 |
void op_mtc0_entrylo1 (void) |
| 868 |
{
|
| 869 |
env->CP0_EntryLo1 = T0 & 0x3FFFFFFF;
|
| 870 |
RETURN(); |
| 871 |
} |
| 872 |
|
| 873 |
void op_mtc0_context (void) |
| 874 |
{
|
| 875 |
env->CP0_Context = (env->CP0_Context & 0xFF800000) | (T0 & 0x007FFFF0); |
| 876 |
RETURN(); |
| 877 |
} |
| 878 |
|
| 879 |
void op_mtc0_pagemask (void) |
| 880 |
{
|
| 881 |
env->CP0_PageMask = T0 & 0x01FFE000;
|
| 882 |
RETURN(); |
| 883 |
} |
| 884 |
|
| 885 |
void op_mtc0_wired (void) |
| 886 |
{
|
| 887 |
env->CP0_Wired = T0 & 0x0000000F;
|
| 888 |
RETURN(); |
| 889 |
} |
| 890 |
|
| 891 |
void op_mtc0_count (void) |
| 892 |
{
|
| 893 |
CALL_FROM_TB2(cpu_mips_store_count, env, T0); |
| 894 |
RETURN(); |
| 895 |
} |
| 896 |
|
| 897 |
void op_mtc0_entryhi (void) |
| 898 |
{
|
| 899 |
uint32_t old, val; |
| 900 |
|
| 901 |
val = T0 & 0xFFFFE0FF;
|
| 902 |
old = env->CP0_EntryHi; |
| 903 |
env->CP0_EntryHi = val; |
| 904 |
/* If the ASID changes, flush qemu's TLB. */
|
| 905 |
if ((old & 0xFF) != (val & 0xFF)) |
| 906 |
CALL_FROM_TB2(cpu_mips_tlb_flush, env, 1);
|
| 907 |
RETURN(); |
| 908 |
} |
| 909 |
|
| 910 |
void op_mtc0_compare (void) |
| 911 |
{
|
| 912 |
CALL_FROM_TB2(cpu_mips_store_compare, env, T0); |
| 913 |
RETURN(); |
| 914 |
} |
| 915 |
|
| 916 |
void op_mtc0_status (void) |
| 917 |
{
|
| 918 |
uint32_t val, old, mask; |
| 919 |
|
| 920 |
val = T0 & 0xFA78FF01;
|
| 921 |
old = env->CP0_Status; |
| 922 |
if (T0 & (1 << CP0St_UM)) |
| 923 |
env->hflags |= MIPS_HFLAG_UM; |
| 924 |
else
|
| 925 |
env->hflags &= ~MIPS_HFLAG_UM; |
| 926 |
if (T0 & (1 << CP0St_ERL)) |
| 927 |
env->hflags |= MIPS_HFLAG_ERL; |
| 928 |
else
|
| 929 |
env->hflags &= ~MIPS_HFLAG_ERL; |
| 930 |
if (T0 & (1 << CP0St_EXL)) |
| 931 |
env->hflags |= MIPS_HFLAG_EXL; |
| 932 |
else
|
| 933 |
env->hflags &= ~MIPS_HFLAG_EXL; |
| 934 |
env->CP0_Status = val; |
| 935 |
/* If we unmasked an asserted IRQ, raise it */
|
| 936 |
mask = 0x0000FF00;
|
| 937 |
if (loglevel & CPU_LOG_TB_IN_ASM)
|
| 938 |
CALL_FROM_TB2(do_mtc0_status_debug, old, val); |
| 939 |
if ((val & (1 << CP0St_IE)) && !(old & (1 << CP0St_IE)) && |
| 940 |
!(env->hflags & MIPS_HFLAG_EXL) && |
| 941 |
!(env->hflags & MIPS_HFLAG_ERL) && |
| 942 |
!(env->hflags & MIPS_HFLAG_DM) && |
| 943 |
(env->CP0_Status & env->CP0_Cause & mask)) {
|
| 944 |
env->interrupt_request |= CPU_INTERRUPT_HARD; |
| 945 |
if (logfile)
|
| 946 |
CALL_FROM_TB0(do_mtc0_status_irqraise_debug); |
| 947 |
} else if (!(val & (1 << CP0St_IE)) && (old & (1 << CP0St_IE))) { |
| 948 |
env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
| 949 |
} |
| 950 |
RETURN(); |
| 951 |
} |
| 952 |
|
| 953 |
void op_mtc0_cause (void) |
| 954 |
{
|
| 955 |
uint32_t val, old; |
| 956 |
|
| 957 |
val = (env->CP0_Cause & 0xB000F87C) | (T0 & 0x000C00300); |
| 958 |
old = env->CP0_Cause; |
| 959 |
env->CP0_Cause = val; |
| 960 |
#if 0
|
| 961 |
{
|
| 962 |
int i, mask;
|
| 963 |
|
| 964 |
/* Check if we ever asserted a software IRQ */
|
| 965 |
for (i = 0; i < 2; i++) {
|
| 966 |
mask = 0x100 << i;
|
| 967 |
if ((val & mask) & !(old & mask))
|
| 968 |
CALL_FROM_TB1(mips_set_irq, i);
|
| 969 |
}
|
| 970 |
}
|
| 971 |
#endif
|
| 972 |
RETURN(); |
| 973 |
} |
| 974 |
|
| 975 |
void op_mtc0_epc (void) |
| 976 |
{
|
| 977 |
env->CP0_EPC = T0; |
| 978 |
RETURN(); |
| 979 |
} |
| 980 |
|
| 981 |
void op_mtc0_config0 (void) |
| 982 |
{
|
| 983 |
#if defined(MIPS_USES_R4K_TLB)
|
| 984 |
env->CP0_Config0 = (env->CP0_Config0 & 0x8017FF80) | (T0 & 0x7E000001); |
| 985 |
#else
|
| 986 |
env->CP0_Config0 = (env->CP0_Config0 & 0xFE17FF80) | (T0 & 0x00000001); |
| 987 |
#endif
|
| 988 |
RETURN(); |
| 989 |
} |
| 990 |
|
| 991 |
void op_mtc0_watchlo (void) |
| 992 |
{
|
| 993 |
env->CP0_WatchLo = T0; |
| 994 |
RETURN(); |
| 995 |
} |
| 996 |
|
| 997 |
void op_mtc0_watchhi (void) |
| 998 |
{
|
| 999 |
env->CP0_WatchHi = T0 & 0x40FF0FF8;
|
| 1000 |
RETURN(); |
| 1001 |
} |
| 1002 |
|
| 1003 |
void op_mtc0_debug (void) |
| 1004 |
{
|
| 1005 |
env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120); |
| 1006 |
if (T0 & (1 << CP0DB_DM)) |
| 1007 |
env->hflags |= MIPS_HFLAG_DM; |
| 1008 |
else
|
| 1009 |
env->hflags &= ~MIPS_HFLAG_DM; |
| 1010 |
RETURN(); |
| 1011 |
} |
| 1012 |
|
| 1013 |
void op_mtc0_depc (void) |
| 1014 |
{
|
| 1015 |
env->CP0_DEPC = T0; |
| 1016 |
RETURN(); |
| 1017 |
} |
| 1018 |
|
| 1019 |
void op_mtc0_taglo (void) |
| 1020 |
{
|
| 1021 |
env->CP0_TagLo = T0 & 0xFFFFFCF6;
|
| 1022 |
RETURN(); |
| 1023 |
} |
| 1024 |
|
| 1025 |
void op_mtc0_errorepc (void) |
| 1026 |
{
|
| 1027 |
env->CP0_ErrorEPC = T0; |
| 1028 |
RETURN(); |
| 1029 |
} |
| 1030 |
|
| 1031 |
void op_mtc0_desave (void) |
| 1032 |
{
|
| 1033 |
env->CP0_DESAVE = T0; |
| 1034 |
RETURN(); |
| 1035 |
} |
| 1036 |
|
| 1037 |
#ifdef MIPS_USES_FPU
|
| 1038 |
|
| 1039 |
#if 0
|
| 1040 |
# define DEBUG_FPU_STATE() CALL_FROM_TB1(dump_fpu, env)
|
| 1041 |
#else
|
| 1042 |
# define DEBUG_FPU_STATE() do { } while(0) |
| 1043 |
#endif
|
| 1044 |
|
| 1045 |
void op_cp1_enabled(void) |
| 1046 |
{
|
| 1047 |
if (!(env->CP0_Status & (1 << CP0St_CU1))) { |
| 1048 |
CALL_FROM_TB2(do_raise_exception_err, EXCP_CpU, 1);
|
| 1049 |
} |
| 1050 |
RETURN(); |
| 1051 |
} |
| 1052 |
|
| 1053 |
/* CP1 functions */
|
| 1054 |
void op_cfc1 (void) |
| 1055 |
{
|
| 1056 |
if (T1 == 0) { |
| 1057 |
T0 = env->fcr0; |
| 1058 |
} |
| 1059 |
else {
|
| 1060 |
/* fetch fcr31, masking unused bits */
|
| 1061 |
T0 = env->fcr31 & 0x0183FFFF;
|
| 1062 |
} |
| 1063 |
DEBUG_FPU_STATE(); |
| 1064 |
RETURN(); |
| 1065 |
} |
| 1066 |
|
| 1067 |
/* convert MIPS rounding mode in FCR31 to IEEE library */
|
| 1068 |
unsigned int ieee_rm[] = { |
| 1069 |
float_round_nearest_even, |
| 1070 |
float_round_to_zero, |
| 1071 |
float_round_up, |
| 1072 |
float_round_down |
| 1073 |
}; |
| 1074 |
|
| 1075 |
#define RESTORE_ROUNDING_MODE \
|
| 1076 |
set_float_rounding_mode(ieee_rm[env->fcr31 & 3], &env->fp_status)
|
| 1077 |
|
| 1078 |
void op_ctc1 (void) |
| 1079 |
{
|
| 1080 |
if (T1 == 0) { |
| 1081 |
/* XXX should this throw an exception?
|
| 1082 |
* don't write to FCR0.
|
| 1083 |
* env->fcr0 = T0;
|
| 1084 |
*/
|
| 1085 |
} |
| 1086 |
else {
|
| 1087 |
/* store new fcr31, masking unused bits */
|
| 1088 |
env->fcr31 = T0 & 0x0183FFFF;
|
| 1089 |
|
| 1090 |
/* set rounding mode */
|
| 1091 |
RESTORE_ROUNDING_MODE; |
| 1092 |
|
| 1093 |
#ifndef CONFIG_SOFTFLOAT
|
| 1094 |
/* no floating point exception for native float */
|
| 1095 |
SET_FP_ENABLE(env->fcr31, 0);
|
| 1096 |
#endif
|
| 1097 |
} |
| 1098 |
DEBUG_FPU_STATE(); |
| 1099 |
RETURN(); |
| 1100 |
} |
| 1101 |
|
| 1102 |
void op_mfc1 (void) |
| 1103 |
{
|
| 1104 |
T0 = WT0; |
| 1105 |
DEBUG_FPU_STATE(); |
| 1106 |
RETURN(); |
| 1107 |
} |
| 1108 |
|
| 1109 |
void op_mtc1 (void) |
| 1110 |
{
|
| 1111 |
WT0 = T0; |
| 1112 |
DEBUG_FPU_STATE(); |
| 1113 |
RETURN(); |
| 1114 |
} |
| 1115 |
|
| 1116 |
/* Float support.
|
| 1117 |
Single precition routines have a "s" suffix, double precision a
|
| 1118 |
"d" suffix. */
|
| 1119 |
|
| 1120 |
#define FLOAT_OP(name, p) void OPPROTO op_float_##name##_##p(void) |
| 1121 |
|
| 1122 |
FLOAT_OP(cvtd, s) |
| 1123 |
{
|
| 1124 |
FDT2 = float32_to_float64(WT0, &env->fp_status); |
| 1125 |
DEBUG_FPU_STATE(); |
| 1126 |
RETURN(); |
| 1127 |
} |
| 1128 |
FLOAT_OP(cvtd, w) |
| 1129 |
{
|
| 1130 |
FDT2 = int32_to_float64(WT0, &env->fp_status); |
| 1131 |
DEBUG_FPU_STATE(); |
| 1132 |
RETURN(); |
| 1133 |
} |
| 1134 |
FLOAT_OP(cvts, d) |
| 1135 |
{
|
| 1136 |
FST2 = float64_to_float32(FDT0, &env->fp_status); |
| 1137 |
DEBUG_FPU_STATE(); |
| 1138 |
RETURN(); |
| 1139 |
} |
| 1140 |
FLOAT_OP(cvts, w) |
| 1141 |
{
|
| 1142 |
FST2 = int32_to_float32(WT0, &env->fp_status); |
| 1143 |
DEBUG_FPU_STATE(); |
| 1144 |
RETURN(); |
| 1145 |
} |
| 1146 |
FLOAT_OP(cvtw, s) |
| 1147 |
{
|
| 1148 |
WT2 = float32_to_int32(FST0, &env->fp_status); |
| 1149 |
DEBUG_FPU_STATE(); |
| 1150 |
RETURN(); |
| 1151 |
} |
| 1152 |
FLOAT_OP(cvtw, d) |
| 1153 |
{
|
| 1154 |
WT2 = float64_to_int32(FDT0, &env->fp_status); |
| 1155 |
DEBUG_FPU_STATE(); |
| 1156 |
RETURN(); |
| 1157 |
} |
| 1158 |
|
| 1159 |
FLOAT_OP(roundw, d) |
| 1160 |
{
|
| 1161 |
set_float_rounding_mode(float_round_nearest_even, &env->fp_status); |
| 1162 |
WT2 = float64_round_to_int(FDT0, &env->fp_status); |
| 1163 |
RESTORE_ROUNDING_MODE; |
| 1164 |
|
| 1165 |
DEBUG_FPU_STATE(); |
| 1166 |
RETURN(); |
| 1167 |
} |
| 1168 |
FLOAT_OP(roundw, s) |
| 1169 |
{
|
| 1170 |
set_float_rounding_mode(float_round_nearest_even, &env->fp_status); |
| 1171 |
WT2 = float32_round_to_int(FST0, &env->fp_status); |
| 1172 |
RESTORE_ROUNDING_MODE; |
| 1173 |
DEBUG_FPU_STATE(); |
| 1174 |
RETURN(); |
| 1175 |
} |
| 1176 |
|
| 1177 |
FLOAT_OP(truncw, d) |
| 1178 |
{
|
| 1179 |
WT2 = float64_to_int32_round_to_zero(FDT0, &env->fp_status); |
| 1180 |
DEBUG_FPU_STATE(); |
| 1181 |
RETURN(); |
| 1182 |
} |
| 1183 |
FLOAT_OP(truncw, s) |
| 1184 |
{
|
| 1185 |
WT2 = float32_to_int32_round_to_zero(FST0, &env->fp_status); |
| 1186 |
DEBUG_FPU_STATE(); |
| 1187 |
RETURN(); |
| 1188 |
} |
| 1189 |
|
| 1190 |
FLOAT_OP(ceilw, d) |
| 1191 |
{
|
| 1192 |
set_float_rounding_mode(float_round_up, &env->fp_status); |
| 1193 |
WT2 = float64_round_to_int(FDT0, &env->fp_status); |
| 1194 |
RESTORE_ROUNDING_MODE; |
| 1195 |
|
| 1196 |
DEBUG_FPU_STATE(); |
| 1197 |
RETURN(); |
| 1198 |
} |
| 1199 |
FLOAT_OP(ceilw, s) |
| 1200 |
{
|
| 1201 |
set_float_rounding_mode(float_round_up, &env->fp_status); |
| 1202 |
WT2 = float32_round_to_int(FST0, &env->fp_status); |
| 1203 |
RESTORE_ROUNDING_MODE; |
| 1204 |
DEBUG_FPU_STATE(); |
| 1205 |
RETURN(); |
| 1206 |
} |
| 1207 |
|
| 1208 |
FLOAT_OP(floorw, d) |
| 1209 |
{
|
| 1210 |
set_float_rounding_mode(float_round_down, &env->fp_status); |
| 1211 |
WT2 = float64_round_to_int(FDT0, &env->fp_status); |
| 1212 |
RESTORE_ROUNDING_MODE; |
| 1213 |
|
| 1214 |
DEBUG_FPU_STATE(); |
| 1215 |
RETURN(); |
| 1216 |
} |
| 1217 |
FLOAT_OP(floorw, s) |
| 1218 |
{
|
| 1219 |
set_float_rounding_mode(float_round_down, &env->fp_status); |
| 1220 |
WT2 = float32_round_to_int(FST0, &env->fp_status); |
| 1221 |
RESTORE_ROUNDING_MODE; |
| 1222 |
DEBUG_FPU_STATE(); |
| 1223 |
RETURN(); |
| 1224 |
} |
| 1225 |
|
| 1226 |
/* binary operations */
|
| 1227 |
#define FLOAT_BINOP(name) \
|
| 1228 |
FLOAT_OP(name, d) \ |
| 1229 |
{ \
|
| 1230 |
FDT2 = float64_ ## name (FDT0, FDT1, &env->fp_status); \ |
| 1231 |
DEBUG_FPU_STATE(); \ |
| 1232 |
} \ |
| 1233 |
FLOAT_OP(name, s) \ |
| 1234 |
{ \
|
| 1235 |
FST2 = float32_ ## name (FST0, FST1, &env->fp_status); \ |
| 1236 |
DEBUG_FPU_STATE(); \ |
| 1237 |
} |
| 1238 |
FLOAT_BINOP(add) |
| 1239 |
FLOAT_BINOP(sub) |
| 1240 |
FLOAT_BINOP(mul) |
| 1241 |
FLOAT_BINOP(div) |
| 1242 |
#undef FLOAT_BINOP
|
| 1243 |
|
| 1244 |
/* unary operations, modifying fp status */
|
| 1245 |
#define FLOAT_UNOP(name) \
|
| 1246 |
FLOAT_OP(name, d) \ |
| 1247 |
{ \
|
| 1248 |
FDT2 = float64_ ## name(FDT0, &env->fp_status); \ |
| 1249 |
DEBUG_FPU_STATE(); \ |
| 1250 |
} \ |
| 1251 |
FLOAT_OP(name, s) \ |
| 1252 |
{ \
|
| 1253 |
FST2 = float32_ ## name(FST0, &env->fp_status); \ |
| 1254 |
DEBUG_FPU_STATE(); \ |
| 1255 |
} |
| 1256 |
FLOAT_UNOP(sqrt) |
| 1257 |
#undef FLOAT_UNOP
|
| 1258 |
|
| 1259 |
/* unary operations, not modifying fp status */
|
| 1260 |
#define FLOAT_UNOP(name) \
|
| 1261 |
FLOAT_OP(name, d) \ |
| 1262 |
{ \
|
| 1263 |
FDT2 = float64_ ## name(FDT0); \ |
| 1264 |
DEBUG_FPU_STATE(); \ |
| 1265 |
} \ |
| 1266 |
FLOAT_OP(name, s) \ |
| 1267 |
{ \
|
| 1268 |
FST2 = float32_ ## name(FST0); \ |
| 1269 |
DEBUG_FPU_STATE(); \ |
| 1270 |
} |
| 1271 |
FLOAT_UNOP(abs) |
| 1272 |
FLOAT_UNOP(chs) |
| 1273 |
#undef FLOAT_UNOP
|
| 1274 |
|
| 1275 |
FLOAT_OP(mov, d) |
| 1276 |
{
|
| 1277 |
FDT2 = FDT0; |
| 1278 |
DEBUG_FPU_STATE(); |
| 1279 |
RETURN(); |
| 1280 |
} |
| 1281 |
FLOAT_OP(mov, s) |
| 1282 |
{
|
| 1283 |
FST2 = FST0; |
| 1284 |
DEBUG_FPU_STATE(); |
| 1285 |
RETURN(); |
| 1286 |
} |
| 1287 |
|
| 1288 |
#ifdef CONFIG_SOFTFLOAT
|
| 1289 |
#define clear_invalid() do { \ |
| 1290 |
int flags = get_float_exception_flags(&env->fp_status); \
|
| 1291 |
flags &= ~float_flag_invalid; \ |
| 1292 |
set_float_exception_flags(flags, &env->fp_status); \ |
| 1293 |
} while(0) |
| 1294 |
#else
|
| 1295 |
#define clear_invalid() do { } while(0) |
| 1296 |
#endif
|
| 1297 |
|
| 1298 |
extern void dump_fpu_s(CPUState *env); |
| 1299 |
|
| 1300 |
#define FOP_COND(fmt, op, sig, cond) \
|
| 1301 |
void op_cmp_ ## fmt ## _ ## op (void) \ |
| 1302 |
{ \
|
| 1303 |
if (cond) \
|
| 1304 |
SET_FP_COND(env->fcr31); \ |
| 1305 |
else \
|
| 1306 |
CLEAR_FP_COND(env->fcr31); \ |
| 1307 |
if (!sig) \
|
| 1308 |
clear_invalid(); \ |
| 1309 |
/*CALL_FROM_TB1(dump_fpu_s, env);*/ \
|
| 1310 |
DEBUG_FPU_STATE(); \ |
| 1311 |
RETURN(); \ |
| 1312 |
} |
| 1313 |
|
| 1314 |
int float64_is_unordered(float64 a, float64 b STATUS_PARAM)
|
| 1315 |
{
|
| 1316 |
if (float64_is_nan(a) || float64_is_nan(b)) {
|
| 1317 |
float_raise(float_flag_invalid, status); |
| 1318 |
return 1; |
| 1319 |
} |
| 1320 |
else {
|
| 1321 |
return 0; |
| 1322 |
} |
| 1323 |
} |
| 1324 |
|
| 1325 |
FOP_COND(d, f, 0, 0) |
| 1326 |
FOP_COND(d, un, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status))
|
| 1327 |
FOP_COND(d, eq, 0, float64_eq(FDT0, FDT1, &env->fp_status))
|
| 1328 |
FOP_COND(d, ueq, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_eq(FDT0, FDT1, &env->fp_status))
|
| 1329 |
FOP_COND(d, olt, 0, float64_lt(FDT0, FDT1, &env->fp_status))
|
| 1330 |
FOP_COND(d, ult, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_lt(FDT0, FDT1, &env->fp_status))
|
| 1331 |
FOP_COND(d, ole, 0, float64_le(FDT0, FDT1, &env->fp_status))
|
| 1332 |
FOP_COND(d, ule, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_le(FDT0, FDT1, &env->fp_status))
|
| 1333 |
/* NOTE: the comma operator will make "cond" to eval to false,
|
| 1334 |
* but float*_is_unordered() is still called
|
| 1335 |
*/
|
| 1336 |
FOP_COND(d, sf, 1, (float64_is_unordered(FDT0, FDT1, &env->fp_status), 0)) |
| 1337 |
FOP_COND(d, ngle,1, float64_is_unordered(FDT1, FDT0, &env->fp_status))
|
| 1338 |
FOP_COND(d, seq, 1, float64_eq(FDT0, FDT1, &env->fp_status))
|
| 1339 |
FOP_COND(d, ngl, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_eq(FDT0, FDT1, &env->fp_status))
|
| 1340 |
FOP_COND(d, lt, 1, float64_lt(FDT0, FDT1, &env->fp_status))
|
| 1341 |
FOP_COND(d, nge, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_lt(FDT0, FDT1, &env->fp_status))
|
| 1342 |
FOP_COND(d, le, 1, float64_le(FDT0, FDT1, &env->fp_status))
|
| 1343 |
FOP_COND(d, ngt, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_le(FDT0, FDT1, &env->fp_status))
|
| 1344 |
|
| 1345 |
flag float32_is_unordered(float32 a, float32 b STATUS_PARAM) |
| 1346 |
{
|
| 1347 |
extern flag float32_is_nan( float32 a );
|
| 1348 |
if (float32_is_nan(a) || float32_is_nan(b)) {
|
| 1349 |
float_raise(float_flag_invalid, status); |
| 1350 |
return 1; |
| 1351 |
} |
| 1352 |
else {
|
| 1353 |
return 0; |
| 1354 |
} |
| 1355 |
} |
| 1356 |
|
| 1357 |
/* NOTE: the comma operator will make "cond" to eval to false,
|
| 1358 |
* but float*_is_unordered() is still called
|
| 1359 |
*/
|
| 1360 |
FOP_COND(s, f, 0, 0) |
| 1361 |
FOP_COND(s, un, 0, float32_is_unordered(FST1, FST0, &env->fp_status))
|
| 1362 |
FOP_COND(s, eq, 0, float32_eq(FST0, FST1, &env->fp_status))
|
| 1363 |
FOP_COND(s, ueq, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status))
|
| 1364 |
FOP_COND(s, olt, 0, float32_lt(FST0, FST1, &env->fp_status))
|
| 1365 |
FOP_COND(s, ult, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status))
|
| 1366 |
FOP_COND(s, ole, 0, float32_le(FST0, FST1, &env->fp_status))
|
| 1367 |
FOP_COND(s, ule, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status))
|
| 1368 |
/* NOTE: the comma operator will make "cond" to eval to false,
|
| 1369 |
* but float*_is_unordered() is still called
|
| 1370 |
*/
|
| 1371 |
FOP_COND(s, sf, 1, (float32_is_unordered(FST0, FST1, &env->fp_status), 0)) |
| 1372 |
FOP_COND(s, ngle,1, float32_is_unordered(FST1, FST0, &env->fp_status))
|
| 1373 |
FOP_COND(s, seq, 1, float32_eq(FST0, FST1, &env->fp_status))
|
| 1374 |
FOP_COND(s, ngl, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status))
|
| 1375 |
FOP_COND(s, lt, 1, float32_lt(FST0, FST1, &env->fp_status))
|
| 1376 |
FOP_COND(s, nge, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status))
|
| 1377 |
FOP_COND(s, le, 1, float32_le(FST0, FST1, &env->fp_status))
|
| 1378 |
FOP_COND(s, ngt, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status))
|
| 1379 |
|
| 1380 |
void op_bc1f (void) |
| 1381 |
{
|
| 1382 |
T0 = ! IS_FP_COND_SET(env->fcr31); |
| 1383 |
DEBUG_FPU_STATE(); |
| 1384 |
RETURN(); |
| 1385 |
} |
| 1386 |
|
| 1387 |
void op_bc1t (void) |
| 1388 |
{
|
| 1389 |
T0 = IS_FP_COND_SET(env->fcr31); |
| 1390 |
DEBUG_FPU_STATE(); |
| 1391 |
RETURN(); |
| 1392 |
} |
| 1393 |
#endif /* MIPS_USES_FPU */ |
| 1394 |
|
| 1395 |
#if defined(MIPS_USES_R4K_TLB)
|
| 1396 |
void op_tlbwi (void) |
| 1397 |
{
|
| 1398 |
CALL_FROM_TB0(do_tlbwi); |
| 1399 |
RETURN(); |
| 1400 |
} |
| 1401 |
|
| 1402 |
void op_tlbwr (void) |
| 1403 |
{
|
| 1404 |
CALL_FROM_TB0(do_tlbwr); |
| 1405 |
RETURN(); |
| 1406 |
} |
| 1407 |
|
| 1408 |
void op_tlbp (void) |
| 1409 |
{
|
| 1410 |
CALL_FROM_TB0(do_tlbp); |
| 1411 |
RETURN(); |
| 1412 |
} |
| 1413 |
|
| 1414 |
void op_tlbr (void) |
| 1415 |
{
|
| 1416 |
CALL_FROM_TB0(do_tlbr); |
| 1417 |
RETURN(); |
| 1418 |
} |
| 1419 |
#endif
|
| 1420 |
|
| 1421 |
/* Specials */
|
| 1422 |
void op_pmon (void) |
| 1423 |
{
|
| 1424 |
CALL_FROM_TB1(do_pmon, PARAM1); |
| 1425 |
} |
| 1426 |
|
| 1427 |
void op_trap (void) |
| 1428 |
{
|
| 1429 |
if (T0) {
|
| 1430 |
CALL_FROM_TB1(do_raise_exception_direct, EXCP_TRAP); |
| 1431 |
} |
| 1432 |
RETURN(); |
| 1433 |
} |
| 1434 |
|
| 1435 |
void op_debug (void) |
| 1436 |
{
|
| 1437 |
CALL_FROM_TB1(do_raise_exception, EXCP_DEBUG); |
| 1438 |
} |
| 1439 |
|
| 1440 |
void op_set_lladdr (void) |
| 1441 |
{
|
| 1442 |
env->CP0_LLAddr = T2; |
| 1443 |
} |
| 1444 |
|
| 1445 |
void debug_eret (void); |
| 1446 |
void op_eret (void) |
| 1447 |
{
|
| 1448 |
CALL_FROM_TB0(debug_eret); |
| 1449 |
if (env->hflags & MIPS_HFLAG_ERL) {
|
| 1450 |
env->PC = env->CP0_ErrorEPC; |
| 1451 |
env->hflags &= ~MIPS_HFLAG_ERL; |
| 1452 |
env->CP0_Status &= ~(1 << CP0St_ERL);
|
| 1453 |
} else {
|
| 1454 |
env->PC = env->CP0_EPC; |
| 1455 |
env->hflags &= ~MIPS_HFLAG_EXL; |
| 1456 |
env->CP0_Status &= ~(1 << CP0St_EXL);
|
| 1457 |
} |
| 1458 |
env->CP0_LLAddr = 1;
|
| 1459 |
} |
| 1460 |
|
| 1461 |
void op_deret (void) |
| 1462 |
{
|
| 1463 |
CALL_FROM_TB0(debug_eret); |
| 1464 |
env->PC = env->CP0_DEPC; |
| 1465 |
} |
| 1466 |
|
| 1467 |
void op_save_state (void) |
| 1468 |
{
|
| 1469 |
env->hflags = PARAM1; |
| 1470 |
RETURN(); |
| 1471 |
} |
| 1472 |
|
| 1473 |
void op_save_pc (void) |
| 1474 |
{
|
| 1475 |
env->PC = PARAM1; |
| 1476 |
RETURN(); |
| 1477 |
} |
| 1478 |
|
| 1479 |
void op_raise_exception (void) |
| 1480 |
{
|
| 1481 |
CALL_FROM_TB1(do_raise_exception, PARAM1); |
| 1482 |
RETURN(); |
| 1483 |
} |
| 1484 |
|
| 1485 |
void op_raise_exception_err (void) |
| 1486 |
{
|
| 1487 |
CALL_FROM_TB2(do_raise_exception_err, PARAM1, PARAM2); |
| 1488 |
RETURN(); |
| 1489 |
} |
| 1490 |
|
| 1491 |
void op_exit_tb (void) |
| 1492 |
{
|
| 1493 |
EXIT_TB(); |
| 1494 |
} |
| 1495 |
|
| 1496 |
void op_wait (void) |
| 1497 |
{
|
| 1498 |
env->halted = 1;
|
| 1499 |
CALL_FROM_TB1(do_raise_exception, EXCP_HLT); |
| 1500 |
} |