Revision 8caa0065 hw/hpet.c
| b/hw/hpet.c | ||
|---|---|---|
| 39 | 39 |
#define DPRINTF(...) |
| 40 | 40 |
#endif |
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#define HPET_MSI_SUPPORT 0 |
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struct HPETState; |
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typedef struct HPETTimer { /* timers */
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uint8_t tn; /*timer number*/ |
| ... | ... | |
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/* Memory-mapped, software visible timer registers */ |
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uint64_t config; /* configuration/cap */ |
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uint64_t cmp; /* comparator */ |
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uint64_t fsb; /* FSB route, not supported now */
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uint64_t fsb; /* FSB route */ |
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/* Hidden register state */ |
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uint64_t period; /* Last value written to comparator */ |
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uint8_t wrap_flag; /* timer pop will indicate wrap for one-shot 32-bit |
| ... | ... | |
| 59 | 61 |
SysBusDevice busdev; |
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uint64_t hpet_offset; |
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qemu_irq irqs[HPET_NUM_IRQ_ROUTES]; |
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uint32_t flags; |
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uint8_t rtc_irq_level; |
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uint8_t num_timers; |
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HPETTimer timer[HPET_MAX_TIMERS]; |
| ... | ... | |
| 80 | 83 |
return (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT; |
| 81 | 84 |
} |
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static uint32_t timer_fsb_route(HPETTimer *t) |
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{
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return t->config & HPET_TN_FSB_ENABLE; |
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} |
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static uint32_t hpet_enabled(HPETState *s) |
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{
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return s->config & HPET_CFG_ENABLE; |
| ... | ... | |
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mask = 1 << timer->tn; |
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if (!set || !timer_enabled(timer) || !hpet_enabled(timer->state)) {
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s->isr &= ~mask; |
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qemu_irq_lower(s->irqs[route]); |
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if (!timer_fsb_route(timer)) {
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qemu_irq_lower(s->irqs[route]); |
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} |
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} else if (timer_fsb_route(timer)) {
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stl_phys(timer->fsb >> 32, timer->fsb & 0xffffffff); |
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| 183 | 195 |
} else if (timer->config & HPET_TN_TYPE_LEVEL) {
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s->isr |= mask; |
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qemu_irq_raise(s->irqs[route]); |
| ... | ... | |
| 216 | 228 |
/* Push number of timers into capability returned via HPET_ID */ |
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s->capability &= ~HPET_ID_NUM_TIM_MASK; |
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s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT; |
| 231 |
|
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/* Derive HPET_MSI_SUPPORT from the capability of the first timer. */ |
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s->flags &= ~(1 << HPET_MSI_SUPPORT); |
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if (s->timer[0].config & HPET_TN_FSB_CAP) {
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s->flags |= 1 << HPET_MSI_SUPPORT; |
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} |
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return 0; |
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} |
| 221 | 239 |
|
| ... | ... | |
| 361 | 379 |
case HPET_TN_CMP + 4: |
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return timer->cmp >> 32; |
| 363 | 381 |
case HPET_TN_ROUTE: |
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return timer->fsb; |
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case HPET_TN_ROUTE + 4: |
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return timer->fsb >> 32; |
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default: |
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DPRINTF("qemu: invalid hpet_ram_readl\n");
|
| ... | ... | |
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switch ((addr - 0x100) % 0x20) {
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case HPET_TN_CFG: |
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DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n");
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if (activating_bit(old_val, new_val, HPET_TN_FSB_ENABLE)) {
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update_irq(timer, 0); |
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} |
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val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK); |
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timer->config = (timer->config & 0xffffffff00000000ULL) | val; |
| 449 | 472 |
if (new_val & HPET_TN_32BIT) {
|
| ... | ... | |
| 501 | 524 |
hpet_set_timer(timer); |
| 502 | 525 |
} |
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break; |
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case HPET_TN_ROUTE: |
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timer->fsb = (timer->fsb & 0xffffffff00000000ULL) | new_val; |
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break; |
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case HPET_TN_ROUTE + 4: |
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DPRINTF("qemu: hpet_ram_writel HPET_TN_ROUTE + 4\n");
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timer->fsb = (new_val << 32) | (timer->fsb & 0xffffffff);
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break; |
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default: |
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DPRINTF("qemu: invalid hpet_ram_writel\n");
|
| ... | ... | |
| 610 | 636 |
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hpet_del_timer(timer); |
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timer->cmp = ~0ULL; |
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timer->config = HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP; |
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timer->config = HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP; |
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if (s->flags & (1 << HPET_MSI_SUPPORT)) {
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timer->config |= HPET_TN_FSB_CAP; |
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} |
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/* advertise availability of ioapic inti2 */ |
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timer->config |= 0x00000004ULL << 32; |
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timer->period = 0ULL; |
| ... | ... | |
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.init = hpet_init, |
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.qdev.props = (Property[]) {
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| 688 | 717 |
DEFINE_PROP_UINT8("timers", HPETState, num_timers, HPET_MIN_TIMERS),
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DEFINE_PROP_BIT("msi", HPETState, flags, HPET_MSI_SUPPORT, false),
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DEFINE_PROP_END_OF_LIST(), |
| 690 | 720 |
}, |
| 691 | 721 |
}; |
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