Revision 8d162c2b

b/target-mips/translate_init.c
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        .insn_flags = CPU_MIPS32 | ASE_MIPS16,
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    },
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    {
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        .name = "4Km",
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        .CP0_PRid = 0x00018300,
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        /* Config1 implemented, fixed mapping MMU,
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           no virtual icache, uncached coherency. */
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        .CP0_Config0 = (1 << CP0C0_M) |
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                    (0x3 << CP0C0_MT) | (0x2 << CP0C0_K0),
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        .CP0_Config1 = MIPS_CONFIG1 |
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		    (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
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		    (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
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        .CP0_Config2 = MIPS_CONFIG2,
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        .CP0_Config3 = MIPS_CONFIG3,
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        .SYNCI_Step = 32,
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        .CCRes = 2,
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        .CP0_Status_rw_bitmask = 0x1258FF17,
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        .insn_flags = CPU_MIPS32 | ASE_MIPS16,
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    },
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    {
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        .name = "4KEcR1",
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        .CP0_PRid = 0x00018400,
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        .CP0_Config0 = MIPS_CONFIG0,
......
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        .insn_flags = CPU_MIPS32 | ASE_MIPS16,
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    },
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    {
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        .name = "4KEmR1",
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        .CP0_PRid = 0x00018500,
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        /* Config1 implemented, fixed mapping MMU,
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           no virtual icache, uncached coherency. */
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        .CP0_Config0 = (1 << CP0C0_M) |
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                    (0x3 << CP0C0_MT) | (0x2 << CP0C0_K0),
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        .CP0_Config1 = MIPS_CONFIG1 |
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		    (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
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		    (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
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        .CP0_Config2 = MIPS_CONFIG2,
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        .CP0_Config3 = MIPS_CONFIG3,
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        .SYNCI_Step = 32,
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        .CCRes = 2,
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        .CP0_Status_rw_bitmask = 0x1258FF17,
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        .insn_flags = CPU_MIPS32 | ASE_MIPS16,
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    },
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    {
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        .name = "4KEc",
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        .CP0_PRid = 0x00019000,
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        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),

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