Revision 8d5f07fa hw/sun4m.c
b/hw/sun4m.c | ||
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28 | 28 |
#define MMU_CONTEXT_TBL 0x00003000 |
29 | 29 |
#define MMU_L1PTP (MMU_CONTEXT_TBL + 0x0400) |
30 | 30 |
#define MMU_L2PTP (MMU_CONTEXT_TBL + 0x0800) |
31 |
#define ROMVEC_DATA (MMU_CONTEXT_TBL + 0x1800) |
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32 | 31 |
#define PROM_ADDR 0xffd04000 |
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#define PROM_FILENAME "proll.bin" |
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#define PROM_FILENAMEB "proll.bin" |
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#define PROM_FILENAMEE "proll.elf" |
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#define PROLL_MAGIC_ADDR 0x20000000 |
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34 | 35 |
#define PHYS_JJ_EEPROM 0x71200000 /* [2000] MK48T08 */ |
35 | 36 |
#define PHYS_JJ_IDPROM_OFF 0x1FD8 |
36 | 37 |
#define PHYS_JJ_EEPROM_SIZE 0x2000 |
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#define PHYS_JJ_IOMMU 0x10000000 /* First page of sun4m IOMMU */ |
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#define PHYS_JJ_TCX_FB 0x50800000 /* Start address, frame buffer body */ |
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#define PHYS_JJ_TCX_0E 0x5E000000 /* Top address, one byte used. */ |
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#define PHYS_JJ_IOMMU 0x10000000 /* First page of sun4m IOMMU */ |
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#define PHYS_JJ_LEDMA 0x78400010 /* ledma, off by 10 from unused SCSI */ |
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#define PHYS_JJ_LE 0x78C00000 /* LANCE, typical sun4m */ |
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#define PHYS_JJ_LE_IRQ 6 |
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#define PHYS_JJ_CLOCK 0x71D00000 |
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#define PHYS_JJ_CLOCK_IRQ 10 |
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#define PHYS_JJ_CLOCK1 0x71D10000 |
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#define PHYS_JJ_CLOCK1_IRQ 14 |
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#define PHYS_JJ_INTR0 0x71E00000 /* CPU0 interrupt control registers */ |
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#define PHYS_JJ_INTR_G 0x71E10000 /* Master interrupt control registers */ |
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37 | 51 |
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38 | 52 |
/* TSC handling */ |
39 | 53 |
|
... | ... | |
44 | 58 |
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45 | 59 |
void DMA_run() {} |
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void SB16_run() {} |
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void vga_invalidate_display() {} |
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void vga_screen_dump(const char *filename) {} |
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49 | 61 |
int serial_can_receive(SerialState *s) { return 0; } |
50 | 62 |
void serial_receive_byte(SerialState *s, int ch) {} |
51 | 63 |
void serial_receive_break(SerialState *s) {} |
... | ... | |
59 | 71 |
const char *initrd_filename) |
60 | 72 |
{ |
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char buf[1024]; |
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int ret, linux_boot, bios_size;
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|
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int ret, linux_boot; |
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63 | 75 |
unsigned long bios_offset; |
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linux_boot = (kernel_filename != NULL); |
... | ... | |
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cpu_register_physical_memory(0, ram_size, 0); |
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bios_offset = ram_size; |
70 | 82 |
|
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iommu_init(); |
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sched_init(); |
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tcx_init(ds); |
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lance_init(&nd_table[0], 6); |
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nvram = m48t08_init(PHYS_JJ_EEPROM, PHYS_JJ_EEPROM_SIZE); |
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|
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magic_init(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
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#if 0 |
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAME); |
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bios_size = get_image_size(buf); |
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ret = load_image(buf, phys_ram_base + bios_offset); |
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if (ret != bios_size) { |
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fprintf(stderr, "qemu: could not load prom '%s'\n", buf); |
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exit(1); |
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} |
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cpu_register_physical_memory(PROM_ADDR, |
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bios_size, bios_offset | IO_MEM_ROM); |
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#endif |
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iommu_init(PHYS_JJ_IOMMU); |
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sched_init(PHYS_JJ_INTR0, PHYS_JJ_INTR_G); |
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tcx_init(ds, PHYS_JJ_TCX_FB); |
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lance_init(&nd_table[0], PHYS_JJ_LE_IRQ, PHYS_JJ_LE, PHYS_JJ_LEDMA); |
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nvram = m48t08_init(PHYS_JJ_EEPROM, PHYS_JJ_EEPROM_SIZE, &nd_table[0].macaddr); |
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timer_init(PHYS_JJ_CLOCK, PHYS_JJ_CLOCK_IRQ); |
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timer_init(PHYS_JJ_CLOCK1, PHYS_JJ_CLOCK1_IRQ); |
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magic_init(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR, PROLL_MAGIC_ADDR); |
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90 | 91 |
|
91 | 92 |
/* We load Proll as the kernel and start it. It will issue a magic |
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IO to load the real kernel */ |
93 | 94 |
if (linux_boot) { |
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAME); |
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEB);
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ret = load_kernel(buf, |
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phys_ram_base + KERNEL_LOAD_ADDR);
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|
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phys_ram_base + KERNEL_LOAD_ADDR);
|
|
97 | 98 |
if (ret < 0) { |
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fprintf(stderr, "qemu: could not load kernel '%s'\n", |
99 | 100 |
buf); |
... | ... | |
103 | 104 |
/* Setup a MMU entry for entire address space */ |
104 | 105 |
stl_raw(phys_ram_base + MMU_CONTEXT_TBL, (MMU_L1PTP >> 4) | 1); |
105 | 106 |
stl_raw(phys_ram_base + MMU_L1PTP, (MMU_L2PTP >> 4) | 1); |
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#if 0 |
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stl_raw(phys_ram_base + MMU_L1PTP + (0x50 << 2), (MMU_L2PTP >> 4) | 1); // frame buffer at 50.. |
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#endif |
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stl_raw(phys_ram_base + MMU_L1PTP + (0x01 << 2), (MMU_L2PTP >> 4) | 1); // 01.. == 00.. |
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109 | 108 |
stl_raw(phys_ram_base + MMU_L1PTP + (0xff << 2), (MMU_L2PTP >> 4) | 1); // ff.. == 00.. |
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stl_raw(phys_ram_base + MMU_L1PTP + (0xf0 << 2), (MMU_L2PTP >> 4) | 1); // f0.. == 00.. |
|
110 | 110 |
/* 3 = U:RWX S:RWX */ |
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stl_raw(phys_ram_base + MMU_L2PTP, (3 << PTE_ACCESS_SHIFT) | 2); |
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#if 0 |
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stl_raw(phys_ram_base + MMU_L2PTP + 0x84, (PHYS_JJ_TCX_FB >> 4) \ |
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| (3 << PTE_ACCESS_SHIFT) | 2); // frame buf |
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stl_raw(phys_ram_base + MMU_L2PTP + 0x88, (PHYS_JJ_TCX_FB >> 4) \ |
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| (3 << PTE_ACCESS_SHIFT) | 2); // frame buf |
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stl_raw(phys_ram_base + MMU_L2PTP + 0x140, (PHYS_JJ_TCX_FB >> 4) \ |
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| (3 << PTE_ACCESS_SHIFT) | 2); // frame buf |
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// "Empirical constant" |
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stl_raw(phys_ram_base + ROMVEC_DATA, 0x10010407); |
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|
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// Version: V3 prom |
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stl_raw(phys_ram_base + ROMVEC_DATA + 4, 3); |
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stl_raw(phys_ram_base + ROMVEC_DATA + 0x1c, ROMVEC_DATA+0x400); |
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stl_raw(phys_ram_base + ROMVEC_DATA + 0x400, ROMVEC_DATA+0x404); |
|
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stl_raw(phys_ram_base + ROMVEC_DATA + 0x404, 0x81c3e008); // retl |
|
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stl_raw(phys_ram_base + ROMVEC_DATA + 0x408, 0x01000000); // nop |
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#endif |
|
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stl_raw(phys_ram_base + MMU_L2PTP, ((0x01 << PTE_PPN_SHIFT) >> 4 ) | (3 << PTE_ACCESS_SHIFT) | 2); |
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130 | 113 |
} |
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