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root / target-sparc / op_helper.c @ 8d5f07fa

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#include <math.h>
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#include <fenv.h>
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#include "exec.h"
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void OPPROTO do_fabss(void)
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{
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    FT0 = fabsf(FT1);
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}
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void OPPROTO do_fsqrts(void)
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{
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    FT0 = sqrtf(FT1);
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}
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void OPPROTO do_fsqrtd(void)
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{
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    DT0 = sqrt(DT1);
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}
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void OPPROTO do_fcmps (void)
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{
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    if (isnan(FT0) || isnan(FT1)) {
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        T0 = FSR_FCC1 | FSR_FCC0;
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    } else if (FT0 < FT1) {
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        T0 = FSR_FCC0;
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    } else if (FT0 > FT1) {
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        T0 = FSR_FCC1;
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    } else {
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        T0 = 0;
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    }
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    env->fsr = T0;
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}
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void OPPROTO do_fcmpd (void)
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{
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    if (isnan(DT0) || isnan(DT1)) {
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        T0 = FSR_FCC1 | FSR_FCC0;
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    } else if (DT0 < DT1) {
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        T0 = FSR_FCC0;
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    } else if (DT0 > DT1) {
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        T0 = FSR_FCC1;
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    } else {
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        T0 = 0;
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    }
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    env->fsr = T0;
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}
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void OPPROTO helper_ld_asi(int asi, int size, int sign)
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{
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    switch(asi) {
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    case 3: /* MMU probe */
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        T1 = 0;
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        return;
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    case 4: /* read MMU regs */
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        {
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            int temp, reg = (T0 >> 8) & 0xf;
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            temp = env->mmuregs[reg];
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            if (reg == 3 || reg == 4) /* Fault status, addr cleared on read*/
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                env->mmuregs[reg] = 0;
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            T1 = temp;
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        }
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        return;
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    case 0x20 ... 0x2f: /* MMU passthrough */
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        {
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            int temp;
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            cpu_physical_memory_read(T0, (void *) &temp, size);
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            bswap32s(&temp);
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            T1 = temp;
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        }
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        return;
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    default:
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        T1 = 0;
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        return;
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    }
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}
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void OPPROTO helper_st_asi(int asi, int size, int sign)
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{
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    switch(asi) {
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    case 3: /* MMU flush */
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        return;
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    case 4: /* write MMU regs */
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        {
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            int reg = (T0 >> 8) & 0xf;
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            if (reg == 0) {
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                env->mmuregs[reg] &= ~(MMU_E | MMU_NF);
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                env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF);
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            } else
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                env->mmuregs[reg] = T1;
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            return;
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        }
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    case 0x20 ... 0x2f: /* MMU passthrough */
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        {
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            int temp = T1;
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            bswap32s(&temp);
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            cpu_physical_memory_write(T0, (void *) &temp, size);
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        }
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        return;
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    default:
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        return;
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    }
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}
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#if 0
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void do_ldd_raw(uint32_t addr)
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{
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    T1 = ldl_raw((void *) addr);
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    T0 = ldl_raw((void *) (addr + 4));
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}
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#if !defined(CONFIG_USER_ONLY)
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void do_ldd_user(uint32_t addr)
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{
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    T1 = ldl_user((void *) addr);
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    T0 = ldl_user((void *) (addr + 4));
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}
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void do_ldd_kernel(uint32_t addr)
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{
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    T1 = ldl_kernel((void *) addr);
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    T0 = ldl_kernel((void *) (addr + 4));
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}
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#endif
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#endif
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void OPPROTO helper_rett()
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{
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    int cwp;
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    env->psret = 1;
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    cwp = (env->cwp + 1) & (NWINDOWS - 1); 
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    if (env->wim & (1 << cwp)) {
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        raise_exception(TT_WIN_UNF);
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    }
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    set_cwp(cwp);
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    env->psrs = env->psrps;
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}
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void helper_ldfsr(void)
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{
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    switch (env->fsr & FSR_RD_MASK) {
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    case FSR_RD_NEAREST:
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        fesetround(FE_TONEAREST);
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        break;
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    case FSR_RD_ZERO:
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        fesetround(FE_TOWARDZERO);
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        break;
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    case FSR_RD_POS:
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        fesetround(FE_UPWARD);
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        break;
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    case FSR_RD_NEG:
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        fesetround(FE_DOWNWARD);
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        break;
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    }
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}