root / tcg / tcg-op.h @ 8d625cf1
History | View | Annotate | Download (69.4 kB)
1 | c896fe29 | bellard | /*
|
---|---|---|---|
2 | c896fe29 | bellard | * Tiny Code Generator for QEMU
|
3 | c896fe29 | bellard | *
|
4 | c896fe29 | bellard | * Copyright (c) 2008 Fabrice Bellard
|
5 | c896fe29 | bellard | *
|
6 | c896fe29 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 | c896fe29 | bellard | * of this software and associated documentation files (the "Software"), to deal
|
8 | c896fe29 | bellard | * in the Software without restriction, including without limitation the rights
|
9 | c896fe29 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 | c896fe29 | bellard | * copies of the Software, and to permit persons to whom the Software is
|
11 | c896fe29 | bellard | * furnished to do so, subject to the following conditions:
|
12 | c896fe29 | bellard | *
|
13 | c896fe29 | bellard | * The above copyright notice and this permission notice shall be included in
|
14 | c896fe29 | bellard | * all copies or substantial portions of the Software.
|
15 | c896fe29 | bellard | *
|
16 | c896fe29 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 | c896fe29 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 | c896fe29 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 | c896fe29 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 | c896fe29 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 | c896fe29 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 | c896fe29 | bellard | * THE SOFTWARE.
|
23 | c896fe29 | bellard | */
|
24 | c896fe29 | bellard | #include "tcg.h" |
25 | c896fe29 | bellard | |
26 | c896fe29 | bellard | int gen_new_label(void); |
27 | c896fe29 | bellard | |
28 | a9751609 | Richard Henderson | static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 arg1) |
29 | c896fe29 | bellard | { |
30 | c896fe29 | bellard | *gen_opc_ptr++ = opc; |
31 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
32 | a7812ae4 | pbrook | } |
33 | a7812ae4 | pbrook | |
34 | a9751609 | Richard Henderson | static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 arg1) |
35 | a7812ae4 | pbrook | { |
36 | a7812ae4 | pbrook | *gen_opc_ptr++ = opc; |
37 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
38 | c896fe29 | bellard | } |
39 | c896fe29 | bellard | |
40 | a9751609 | Richard Henderson | static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg arg1) |
41 | c896fe29 | bellard | { |
42 | c896fe29 | bellard | *gen_opc_ptr++ = opc; |
43 | c896fe29 | bellard | *gen_opparam_ptr++ = arg1; |
44 | c896fe29 | bellard | } |
45 | c896fe29 | bellard | |
46 | a9751609 | Richard Henderson | static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2) |
47 | a7812ae4 | pbrook | { |
48 | a7812ae4 | pbrook | *gen_opc_ptr++ = opc; |
49 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
50 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
51 | a7812ae4 | pbrook | } |
52 | a7812ae4 | pbrook | |
53 | a9751609 | Richard Henderson | static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2) |
54 | a7812ae4 | pbrook | { |
55 | a7812ae4 | pbrook | *gen_opc_ptr++ = opc; |
56 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
57 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
58 | a7812ae4 | pbrook | } |
59 | a7812ae4 | pbrook | |
60 | a9751609 | Richard Henderson | static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGArg arg2) |
61 | c896fe29 | bellard | { |
62 | c896fe29 | bellard | *gen_opc_ptr++ = opc; |
63 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
64 | a7812ae4 | pbrook | *gen_opparam_ptr++ = arg2; |
65 | c896fe29 | bellard | } |
66 | c896fe29 | bellard | |
67 | a9751609 | Richard Henderson | static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGArg arg2) |
68 | c896fe29 | bellard | { |
69 | c896fe29 | bellard | *gen_opc_ptr++ = opc; |
70 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
71 | c896fe29 | bellard | *gen_opparam_ptr++ = arg2; |
72 | ac56dd48 | pbrook | } |
73 | ac56dd48 | pbrook | |
74 | a9751609 | Richard Henderson | static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg arg1, TCGArg arg2) |
75 | bcb0126f | pbrook | { |
76 | bcb0126f | pbrook | *gen_opc_ptr++ = opc; |
77 | bcb0126f | pbrook | *gen_opparam_ptr++ = arg1; |
78 | bcb0126f | pbrook | *gen_opparam_ptr++ = arg2; |
79 | bcb0126f | pbrook | } |
80 | bcb0126f | pbrook | |
81 | a9751609 | Richard Henderson | static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
82 | a7812ae4 | pbrook | TCGv_i32 arg3) |
83 | a7812ae4 | pbrook | { |
84 | a7812ae4 | pbrook | *gen_opc_ptr++ = opc; |
85 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
86 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
87 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
88 | a7812ae4 | pbrook | } |
89 | a7812ae4 | pbrook | |
90 | a9751609 | Richard Henderson | static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
91 | a7812ae4 | pbrook | TCGv_i64 arg3) |
92 | a7812ae4 | pbrook | { |
93 | a7812ae4 | pbrook | *gen_opc_ptr++ = opc; |
94 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
95 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
96 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
97 | a7812ae4 | pbrook | } |
98 | a7812ae4 | pbrook | |
99 | a9751609 | Richard Henderson | static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 arg1, |
100 | a9751609 | Richard Henderson | TCGv_i32 arg2, TCGArg arg3) |
101 | ac56dd48 | pbrook | { |
102 | ac56dd48 | pbrook | *gen_opc_ptr++ = opc; |
103 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
104 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
105 | a7812ae4 | pbrook | *gen_opparam_ptr++ = arg3; |
106 | ac56dd48 | pbrook | } |
107 | ac56dd48 | pbrook | |
108 | a9751609 | Richard Henderson | static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 arg1, |
109 | a9751609 | Richard Henderson | TCGv_i64 arg2, TCGArg arg3) |
110 | ac56dd48 | pbrook | { |
111 | ac56dd48 | pbrook | *gen_opc_ptr++ = opc; |
112 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
113 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
114 | c896fe29 | bellard | *gen_opparam_ptr++ = arg3; |
115 | ac56dd48 | pbrook | } |
116 | ac56dd48 | pbrook | |
117 | a9751609 | Richard Henderson | static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val, |
118 | a9751609 | Richard Henderson | TCGv_ptr base, TCGArg offset) |
119 | a7812ae4 | pbrook | { |
120 | a7812ae4 | pbrook | *gen_opc_ptr++ = opc; |
121 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(val); |
122 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_PTR(base); |
123 | a7812ae4 | pbrook | *gen_opparam_ptr++ = offset; |
124 | a7812ae4 | pbrook | } |
125 | a7812ae4 | pbrook | |
126 | a9751609 | Richard Henderson | static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val, |
127 | a9751609 | Richard Henderson | TCGv_ptr base, TCGArg offset) |
128 | a7812ae4 | pbrook | { |
129 | a7812ae4 | pbrook | *gen_opc_ptr++ = opc; |
130 | a810a2de | blueswir1 | *gen_opparam_ptr++ = GET_TCGV_I64(val); |
131 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_PTR(base); |
132 | a7812ae4 | pbrook | *gen_opparam_ptr++ = offset; |
133 | a7812ae4 | pbrook | } |
134 | a7812ae4 | pbrook | |
135 | a9751609 | Richard Henderson | static inline void tcg_gen_qemu_ldst_op_i64_i32(TCGOpcode opc, TCGv_i64 val, |
136 | a9751609 | Richard Henderson | TCGv_i32 addr, TCGArg mem_index) |
137 | a7812ae4 | pbrook | { |
138 | a7812ae4 | pbrook | *gen_opc_ptr++ = opc; |
139 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(val); |
140 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(addr); |
141 | a7812ae4 | pbrook | *gen_opparam_ptr++ = mem_index; |
142 | a7812ae4 | pbrook | } |
143 | a7812ae4 | pbrook | |
144 | a9751609 | Richard Henderson | static inline void tcg_gen_qemu_ldst_op_i64_i64(TCGOpcode opc, TCGv_i64 val, |
145 | a9751609 | Richard Henderson | TCGv_i64 addr, TCGArg mem_index) |
146 | a7812ae4 | pbrook | { |
147 | a7812ae4 | pbrook | *gen_opc_ptr++ = opc; |
148 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(val); |
149 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(addr); |
150 | a7812ae4 | pbrook | *gen_opparam_ptr++ = mem_index; |
151 | a7812ae4 | pbrook | } |
152 | a7812ae4 | pbrook | |
153 | a9751609 | Richard Henderson | static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
154 | a7812ae4 | pbrook | TCGv_i32 arg3, TCGv_i32 arg4) |
155 | a7812ae4 | pbrook | { |
156 | a7812ae4 | pbrook | *gen_opc_ptr++ = opc; |
157 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
158 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
159 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
160 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
161 | a7812ae4 | pbrook | } |
162 | a7812ae4 | pbrook | |
163 | a9751609 | Richard Henderson | static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
164 | a810a2de | blueswir1 | TCGv_i64 arg3, TCGv_i64 arg4) |
165 | a7812ae4 | pbrook | { |
166 | a7812ae4 | pbrook | *gen_opc_ptr++ = opc; |
167 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
168 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
169 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
170 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
171 | a7812ae4 | pbrook | } |
172 | a7812ae4 | pbrook | |
173 | a9751609 | Richard Henderson | static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
174 | a7812ae4 | pbrook | TCGv_i32 arg3, TCGArg arg4) |
175 | a7812ae4 | pbrook | { |
176 | a7812ae4 | pbrook | *gen_opc_ptr++ = opc; |
177 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
178 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
179 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
180 | a7812ae4 | pbrook | *gen_opparam_ptr++ = arg4; |
181 | a7812ae4 | pbrook | } |
182 | a7812ae4 | pbrook | |
183 | a9751609 | Richard Henderson | static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
184 | a7812ae4 | pbrook | TCGv_i64 arg3, TCGArg arg4) |
185 | ac56dd48 | pbrook | { |
186 | ac56dd48 | pbrook | *gen_opc_ptr++ = opc; |
187 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
188 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
189 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
190 | a7812ae4 | pbrook | *gen_opparam_ptr++ = arg4; |
191 | ac56dd48 | pbrook | } |
192 | ac56dd48 | pbrook | |
193 | a9751609 | Richard Henderson | static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
194 | a7812ae4 | pbrook | TCGArg arg3, TCGArg arg4) |
195 | ac56dd48 | pbrook | { |
196 | ac56dd48 | pbrook | *gen_opc_ptr++ = opc; |
197 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
198 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
199 | a7812ae4 | pbrook | *gen_opparam_ptr++ = arg3; |
200 | c896fe29 | bellard | *gen_opparam_ptr++ = arg4; |
201 | c896fe29 | bellard | } |
202 | c896fe29 | bellard | |
203 | a9751609 | Richard Henderson | static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
204 | a7812ae4 | pbrook | TCGArg arg3, TCGArg arg4) |
205 | c896fe29 | bellard | { |
206 | c896fe29 | bellard | *gen_opc_ptr++ = opc; |
207 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
208 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
209 | c896fe29 | bellard | *gen_opparam_ptr++ = arg3; |
210 | c896fe29 | bellard | *gen_opparam_ptr++ = arg4; |
211 | ac56dd48 | pbrook | } |
212 | ac56dd48 | pbrook | |
213 | a9751609 | Richard Henderson | static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
214 | a7812ae4 | pbrook | TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5) |
215 | a7812ae4 | pbrook | { |
216 | a7812ae4 | pbrook | *gen_opc_ptr++ = opc; |
217 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
218 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
219 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
220 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
221 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(arg5); |
222 | a7812ae4 | pbrook | } |
223 | a7812ae4 | pbrook | |
224 | a9751609 | Richard Henderson | static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
225 | a7812ae4 | pbrook | TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5) |
226 | a7812ae4 | pbrook | { |
227 | a7812ae4 | pbrook | *gen_opc_ptr++ = opc; |
228 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
229 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
230 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
231 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
232 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(arg5); |
233 | a7812ae4 | pbrook | } |
234 | a7812ae4 | pbrook | |
235 | a9751609 | Richard Henderson | static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
236 | a7812ae4 | pbrook | TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5) |
237 | ac56dd48 | pbrook | { |
238 | ac56dd48 | pbrook | *gen_opc_ptr++ = opc; |
239 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
240 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
241 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
242 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
243 | a7812ae4 | pbrook | *gen_opparam_ptr++ = arg5; |
244 | ac56dd48 | pbrook | } |
245 | ac56dd48 | pbrook | |
246 | a9751609 | Richard Henderson | static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
247 | a7812ae4 | pbrook | TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5) |
248 | ac56dd48 | pbrook | { |
249 | ac56dd48 | pbrook | *gen_opc_ptr++ = opc; |
250 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
251 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
252 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
253 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
254 | c896fe29 | bellard | *gen_opparam_ptr++ = arg5; |
255 | c896fe29 | bellard | } |
256 | c896fe29 | bellard | |
257 | a9751609 | Richard Henderson | static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
258 | a7812ae4 | pbrook | TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5, |
259 | a7812ae4 | pbrook | TCGv_i32 arg6) |
260 | a7812ae4 | pbrook | { |
261 | a7812ae4 | pbrook | *gen_opc_ptr++ = opc; |
262 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
263 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
264 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
265 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
266 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(arg5); |
267 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(arg6); |
268 | a7812ae4 | pbrook | } |
269 | a7812ae4 | pbrook | |
270 | a9751609 | Richard Henderson | static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
271 | a7812ae4 | pbrook | TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5, |
272 | a7812ae4 | pbrook | TCGv_i64 arg6) |
273 | c896fe29 | bellard | { |
274 | c896fe29 | bellard | *gen_opc_ptr++ = opc; |
275 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
276 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
277 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
278 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
279 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(arg5); |
280 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(arg6); |
281 | ac56dd48 | pbrook | } |
282 | ac56dd48 | pbrook | |
283 | a9751609 | Richard Henderson | static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
284 | be210acb | Richard Henderson | TCGv_i32 arg3, TCGv_i32 arg4, |
285 | be210acb | Richard Henderson | TCGv_i32 arg5, TCGArg arg6) |
286 | be210acb | Richard Henderson | { |
287 | be210acb | Richard Henderson | *gen_opc_ptr++ = opc; |
288 | be210acb | Richard Henderson | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
289 | be210acb | Richard Henderson | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
290 | be210acb | Richard Henderson | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
291 | be210acb | Richard Henderson | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
292 | be210acb | Richard Henderson | *gen_opparam_ptr++ = GET_TCGV_I32(arg5); |
293 | be210acb | Richard Henderson | *gen_opparam_ptr++ = arg6; |
294 | be210acb | Richard Henderson | } |
295 | be210acb | Richard Henderson | |
296 | a9751609 | Richard Henderson | static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
297 | be210acb | Richard Henderson | TCGv_i64 arg3, TCGv_i64 arg4, |
298 | be210acb | Richard Henderson | TCGv_i64 arg5, TCGArg arg6) |
299 | be210acb | Richard Henderson | { |
300 | be210acb | Richard Henderson | *gen_opc_ptr++ = opc; |
301 | be210acb | Richard Henderson | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
302 | be210acb | Richard Henderson | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
303 | be210acb | Richard Henderson | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
304 | be210acb | Richard Henderson | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
305 | be210acb | Richard Henderson | *gen_opparam_ptr++ = GET_TCGV_I64(arg5); |
306 | be210acb | Richard Henderson | *gen_opparam_ptr++ = arg6; |
307 | be210acb | Richard Henderson | } |
308 | be210acb | Richard Henderson | |
309 | a9751609 | Richard Henderson | static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 arg1, |
310 | a9751609 | Richard Henderson | TCGv_i32 arg2, TCGv_i32 arg3, |
311 | a9751609 | Richard Henderson | TCGv_i32 arg4, TCGArg arg5, TCGArg arg6) |
312 | ac56dd48 | pbrook | { |
313 | ac56dd48 | pbrook | *gen_opc_ptr++ = opc; |
314 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
315 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
316 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
317 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
318 | a7812ae4 | pbrook | *gen_opparam_ptr++ = arg5; |
319 | a7812ae4 | pbrook | *gen_opparam_ptr++ = arg6; |
320 | a7812ae4 | pbrook | } |
321 | a7812ae4 | pbrook | |
322 | a9751609 | Richard Henderson | static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 arg1, |
323 | a9751609 | Richard Henderson | TCGv_i64 arg2, TCGv_i64 arg3, |
324 | a9751609 | Richard Henderson | TCGv_i64 arg4, TCGArg arg5, TCGArg arg6) |
325 | a7812ae4 | pbrook | { |
326 | a7812ae4 | pbrook | *gen_opc_ptr++ = opc; |
327 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
328 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
329 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
330 | a7812ae4 | pbrook | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
331 | c896fe29 | bellard | *gen_opparam_ptr++ = arg5; |
332 | c896fe29 | bellard | *gen_opparam_ptr++ = arg6; |
333 | c896fe29 | bellard | } |
334 | c896fe29 | bellard | |
335 | c896fe29 | bellard | static inline void gen_set_label(int n) |
336 | c896fe29 | bellard | { |
337 | ac56dd48 | pbrook | tcg_gen_op1i(INDEX_op_set_label, n); |
338 | c896fe29 | bellard | } |
339 | c896fe29 | bellard | |
340 | fb50d413 | blueswir1 | static inline void tcg_gen_br(int label) |
341 | fb50d413 | blueswir1 | { |
342 | fb50d413 | blueswir1 | tcg_gen_op1i(INDEX_op_br, label); |
343 | fb50d413 | blueswir1 | } |
344 | fb50d413 | blueswir1 | |
345 | a7812ae4 | pbrook | static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg) |
346 | c896fe29 | bellard | { |
347 | fe75bcf7 | aurel32 | if (!TCGV_EQUAL_I32(ret, arg))
|
348 | a7812ae4 | pbrook | tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg); |
349 | c896fe29 | bellard | } |
350 | c896fe29 | bellard | |
351 | a7812ae4 | pbrook | static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg) |
352 | c896fe29 | bellard | { |
353 | a7812ae4 | pbrook | tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg); |
354 | c896fe29 | bellard | } |
355 | c896fe29 | bellard | |
356 | c896fe29 | bellard | /* helper calls */
|
357 | a7812ae4 | pbrook | static inline void tcg_gen_helperN(void *func, int flags, int sizemask, |
358 | a7812ae4 | pbrook | TCGArg ret, int nargs, TCGArg *args)
|
359 | a7812ae4 | pbrook | { |
360 | a7812ae4 | pbrook | TCGv_ptr fn; |
361 | a7812ae4 | pbrook | fn = tcg_const_ptr((tcg_target_long)func); |
362 | a7812ae4 | pbrook | tcg_gen_callN(&tcg_ctx, fn, flags, sizemask, ret, |
363 | a7812ae4 | pbrook | nargs, args); |
364 | a7812ae4 | pbrook | tcg_temp_free_ptr(fn); |
365 | a7812ae4 | pbrook | } |
366 | c896fe29 | bellard | |
367 | dbfff4de | Aurelien Jarno | /* Note: Both tcg_gen_helper32() and tcg_gen_helper64() are currently
|
368 | dbfff4de | Aurelien Jarno | reserved for helpers in tcg-runtime.c. These helpers are all const
|
369 | dbfff4de | Aurelien Jarno | and pure, hence the call to tcg_gen_callN() with TCG_CALL_CONST |
|
370 | dbfff4de | Aurelien Jarno | TCG_CALL_PURE. This may need to be adjusted if these functions
|
371 | dbfff4de | Aurelien Jarno | start to be used with other helpers. */
|
372 | 31d66551 | Aurelien Jarno | static inline void tcg_gen_helper32(void *func, TCGv_i32 ret, |
373 | 31d66551 | Aurelien Jarno | TCGv_i32 a, TCGv_i32 b) |
374 | 31d66551 | Aurelien Jarno | { |
375 | 31d66551 | Aurelien Jarno | TCGv_ptr fn; |
376 | 31d66551 | Aurelien Jarno | TCGArg args[2];
|
377 | 31d66551 | Aurelien Jarno | fn = tcg_const_ptr((tcg_target_long)func); |
378 | 31d66551 | Aurelien Jarno | args[0] = GET_TCGV_I32(a);
|
379 | 31d66551 | Aurelien Jarno | args[1] = GET_TCGV_I32(b);
|
380 | dbfff4de | Aurelien Jarno | tcg_gen_callN(&tcg_ctx, fn, TCG_CALL_CONST | TCG_CALL_PURE, |
381 | dbfff4de | Aurelien Jarno | 0, GET_TCGV_I32(ret), 2, args); |
382 | 31d66551 | Aurelien Jarno | tcg_temp_free_ptr(fn); |
383 | 31d66551 | Aurelien Jarno | } |
384 | 31d66551 | Aurelien Jarno | |
385 | a7812ae4 | pbrook | static inline void tcg_gen_helper64(void *func, TCGv_i64 ret, |
386 | a7812ae4 | pbrook | TCGv_i64 a, TCGv_i64 b) |
387 | c896fe29 | bellard | { |
388 | a7812ae4 | pbrook | TCGv_ptr fn; |
389 | a7812ae4 | pbrook | TCGArg args[2];
|
390 | a7812ae4 | pbrook | fn = tcg_const_ptr((tcg_target_long)func); |
391 | a7812ae4 | pbrook | args[0] = GET_TCGV_I64(a);
|
392 | a7812ae4 | pbrook | args[1] = GET_TCGV_I64(b);
|
393 | dbfff4de | Aurelien Jarno | tcg_gen_callN(&tcg_ctx, fn, TCG_CALL_CONST | TCG_CALL_PURE, |
394 | dbfff4de | Aurelien Jarno | 7, GET_TCGV_I64(ret), 2, args); |
395 | a7812ae4 | pbrook | tcg_temp_free_ptr(fn); |
396 | f8422f52 | blueswir1 | } |
397 | f8422f52 | blueswir1 | |
398 | c896fe29 | bellard | /* 32 bit ops */
|
399 | c896fe29 | bellard | |
400 | a7812ae4 | pbrook | static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
401 | c896fe29 | bellard | { |
402 | a7812ae4 | pbrook | tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset); |
403 | c896fe29 | bellard | } |
404 | c896fe29 | bellard | |
405 | a7812ae4 | pbrook | static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
406 | c896fe29 | bellard | { |
407 | a7812ae4 | pbrook | tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset); |
408 | c896fe29 | bellard | } |
409 | c896fe29 | bellard | |
410 | a7812ae4 | pbrook | static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
411 | c896fe29 | bellard | { |
412 | a7812ae4 | pbrook | tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset); |
413 | c896fe29 | bellard | } |
414 | c896fe29 | bellard | |
415 | a7812ae4 | pbrook | static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
416 | c896fe29 | bellard | { |
417 | a7812ae4 | pbrook | tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset); |
418 | c896fe29 | bellard | } |
419 | c896fe29 | bellard | |
420 | a7812ae4 | pbrook | static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
421 | c896fe29 | bellard | { |
422 | a7812ae4 | pbrook | tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset); |
423 | c896fe29 | bellard | } |
424 | c896fe29 | bellard | |
425 | a7812ae4 | pbrook | static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
426 | c896fe29 | bellard | { |
427 | a7812ae4 | pbrook | tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset); |
428 | c896fe29 | bellard | } |
429 | c896fe29 | bellard | |
430 | a7812ae4 | pbrook | static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
431 | c896fe29 | bellard | { |
432 | a7812ae4 | pbrook | tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset); |
433 | c896fe29 | bellard | } |
434 | c896fe29 | bellard | |
435 | a7812ae4 | pbrook | static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
436 | c896fe29 | bellard | { |
437 | a7812ae4 | pbrook | tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset); |
438 | c896fe29 | bellard | } |
439 | c896fe29 | bellard | |
440 | a7812ae4 | pbrook | static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
441 | c896fe29 | bellard | { |
442 | a7812ae4 | pbrook | tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2); |
443 | c896fe29 | bellard | } |
444 | c896fe29 | bellard | |
445 | a7812ae4 | pbrook | static inline void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
446 | c896fe29 | bellard | { |
447 | 7089442c | blueswir1 | /* some cases can be optimized here */
|
448 | 7089442c | blueswir1 | if (arg2 == 0) { |
449 | 7089442c | blueswir1 | tcg_gen_mov_i32(ret, arg1); |
450 | 7089442c | blueswir1 | } else {
|
451 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_const_i32(arg2); |
452 | e8996ee0 | bellard | tcg_gen_add_i32(ret, arg1, t0); |
453 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
454 | 7089442c | blueswir1 | } |
455 | c896fe29 | bellard | } |
456 | c896fe29 | bellard | |
457 | a7812ae4 | pbrook | static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
458 | c896fe29 | bellard | { |
459 | a7812ae4 | pbrook | tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2); |
460 | c896fe29 | bellard | } |
461 | c896fe29 | bellard | |
462 | a7812ae4 | pbrook | static inline void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2) |
463 | 0045734a | aurel32 | { |
464 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_const_i32(arg1); |
465 | 0045734a | aurel32 | tcg_gen_sub_i32(ret, t0, arg2); |
466 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
467 | 0045734a | aurel32 | } |
468 | 0045734a | aurel32 | |
469 | a7812ae4 | pbrook | static inline void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
470 | c896fe29 | bellard | { |
471 | 7089442c | blueswir1 | /* some cases can be optimized here */
|
472 | 7089442c | blueswir1 | if (arg2 == 0) { |
473 | 7089442c | blueswir1 | tcg_gen_mov_i32(ret, arg1); |
474 | 7089442c | blueswir1 | } else {
|
475 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_const_i32(arg2); |
476 | e8996ee0 | bellard | tcg_gen_sub_i32(ret, arg1, t0); |
477 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
478 | 7089442c | blueswir1 | } |
479 | c896fe29 | bellard | } |
480 | c896fe29 | bellard | |
481 | a7812ae4 | pbrook | static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
482 | c896fe29 | bellard | { |
483 | 7fc81051 | aurel32 | if (TCGV_EQUAL_I32(arg1, arg2)) {
|
484 | 7fc81051 | aurel32 | tcg_gen_mov_i32(ret, arg1); |
485 | 7fc81051 | aurel32 | } else {
|
486 | 7fc81051 | aurel32 | tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2); |
487 | 7fc81051 | aurel32 | } |
488 | c896fe29 | bellard | } |
489 | c896fe29 | bellard | |
490 | a7812ae4 | pbrook | static inline void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
491 | c896fe29 | bellard | { |
492 | c896fe29 | bellard | /* some cases can be optimized here */
|
493 | c896fe29 | bellard | if (arg2 == 0) { |
494 | c896fe29 | bellard | tcg_gen_movi_i32(ret, 0);
|
495 | c896fe29 | bellard | } else if (arg2 == 0xffffffff) { |
496 | c896fe29 | bellard | tcg_gen_mov_i32(ret, arg1); |
497 | c896fe29 | bellard | } else {
|
498 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_const_i32(arg2); |
499 | e8996ee0 | bellard | tcg_gen_and_i32(ret, arg1, t0); |
500 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
501 | c896fe29 | bellard | } |
502 | c896fe29 | bellard | } |
503 | c896fe29 | bellard | |
504 | a7812ae4 | pbrook | static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
505 | c896fe29 | bellard | { |
506 | 7fc81051 | aurel32 | if (TCGV_EQUAL_I32(arg1, arg2)) {
|
507 | 7fc81051 | aurel32 | tcg_gen_mov_i32(ret, arg1); |
508 | 7fc81051 | aurel32 | } else {
|
509 | 7fc81051 | aurel32 | tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2); |
510 | 7fc81051 | aurel32 | } |
511 | c896fe29 | bellard | } |
512 | c896fe29 | bellard | |
513 | a7812ae4 | pbrook | static inline void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
514 | c896fe29 | bellard | { |
515 | c896fe29 | bellard | /* some cases can be optimized here */
|
516 | c896fe29 | bellard | if (arg2 == 0xffffffff) { |
517 | 7089442c | blueswir1 | tcg_gen_movi_i32(ret, 0xffffffff);
|
518 | c896fe29 | bellard | } else if (arg2 == 0) { |
519 | c896fe29 | bellard | tcg_gen_mov_i32(ret, arg1); |
520 | c896fe29 | bellard | } else {
|
521 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_const_i32(arg2); |
522 | e8996ee0 | bellard | tcg_gen_or_i32(ret, arg1, t0); |
523 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
524 | c896fe29 | bellard | } |
525 | c896fe29 | bellard | } |
526 | c896fe29 | bellard | |
527 | a7812ae4 | pbrook | static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
528 | c896fe29 | bellard | { |
529 | 7fc81051 | aurel32 | if (TCGV_EQUAL_I32(arg1, arg2)) {
|
530 | 7fc81051 | aurel32 | tcg_gen_movi_i32(ret, 0);
|
531 | 7fc81051 | aurel32 | } else {
|
532 | 7fc81051 | aurel32 | tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2); |
533 | 7fc81051 | aurel32 | } |
534 | c896fe29 | bellard | } |
535 | c896fe29 | bellard | |
536 | a7812ae4 | pbrook | static inline void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
537 | c896fe29 | bellard | { |
538 | c896fe29 | bellard | /* some cases can be optimized here */
|
539 | c896fe29 | bellard | if (arg2 == 0) { |
540 | c896fe29 | bellard | tcg_gen_mov_i32(ret, arg1); |
541 | c896fe29 | bellard | } else {
|
542 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_const_i32(arg2); |
543 | e8996ee0 | bellard | tcg_gen_xor_i32(ret, arg1, t0); |
544 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
545 | c896fe29 | bellard | } |
546 | c896fe29 | bellard | } |
547 | c896fe29 | bellard | |
548 | a7812ae4 | pbrook | static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
549 | c896fe29 | bellard | { |
550 | a7812ae4 | pbrook | tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2); |
551 | c896fe29 | bellard | } |
552 | c896fe29 | bellard | |
553 | a7812ae4 | pbrook | static inline void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
554 | c896fe29 | bellard | { |
555 | 34151a20 | bellard | if (arg2 == 0) { |
556 | 34151a20 | bellard | tcg_gen_mov_i32(ret, arg1); |
557 | 34151a20 | bellard | } else {
|
558 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_const_i32(arg2); |
559 | e8996ee0 | bellard | tcg_gen_shl_i32(ret, arg1, t0); |
560 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
561 | 34151a20 | bellard | } |
562 | c896fe29 | bellard | } |
563 | c896fe29 | bellard | |
564 | a7812ae4 | pbrook | static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
565 | c896fe29 | bellard | { |
566 | a7812ae4 | pbrook | tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2); |
567 | c896fe29 | bellard | } |
568 | c896fe29 | bellard | |
569 | a7812ae4 | pbrook | static inline void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
570 | c896fe29 | bellard | { |
571 | 34151a20 | bellard | if (arg2 == 0) { |
572 | 34151a20 | bellard | tcg_gen_mov_i32(ret, arg1); |
573 | 34151a20 | bellard | } else {
|
574 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_const_i32(arg2); |
575 | e8996ee0 | bellard | tcg_gen_shr_i32(ret, arg1, t0); |
576 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
577 | 34151a20 | bellard | } |
578 | c896fe29 | bellard | } |
579 | c896fe29 | bellard | |
580 | a7812ae4 | pbrook | static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
581 | c896fe29 | bellard | { |
582 | a7812ae4 | pbrook | tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2); |
583 | c896fe29 | bellard | } |
584 | c896fe29 | bellard | |
585 | a7812ae4 | pbrook | static inline void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
586 | c896fe29 | bellard | { |
587 | 34151a20 | bellard | if (arg2 == 0) { |
588 | 34151a20 | bellard | tcg_gen_mov_i32(ret, arg1); |
589 | 34151a20 | bellard | } else {
|
590 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_const_i32(arg2); |
591 | e8996ee0 | bellard | tcg_gen_sar_i32(ret, arg1, t0); |
592 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
593 | 34151a20 | bellard | } |
594 | c896fe29 | bellard | } |
595 | c896fe29 | bellard | |
596 | 8a56e840 | Richard Henderson | static inline void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, |
597 | 8a56e840 | Richard Henderson | TCGv_i32 arg2, int label_index)
|
598 | c896fe29 | bellard | { |
599 | a7812ae4 | pbrook | tcg_gen_op4ii_i32(INDEX_op_brcond_i32, arg1, arg2, cond, label_index); |
600 | c896fe29 | bellard | } |
601 | c896fe29 | bellard | |
602 | 8a56e840 | Richard Henderson | static inline void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, |
603 | 8a56e840 | Richard Henderson | int32_t arg2, int label_index)
|
604 | cb63669a | pbrook | { |
605 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_const_i32(arg2); |
606 | cb63669a | pbrook | tcg_gen_brcond_i32(cond, arg1, t0, label_index); |
607 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
608 | cb63669a | pbrook | } |
609 | cb63669a | pbrook | |
610 | 8a56e840 | Richard Henderson | static inline void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, |
611 | 5105c556 | Aurelien Jarno | TCGv_i32 arg1, TCGv_i32 arg2) |
612 | 5105c556 | Aurelien Jarno | { |
613 | 5105c556 | Aurelien Jarno | tcg_gen_op4i_i32(INDEX_op_setcond_i32, ret, arg1, arg2, cond); |
614 | 5105c556 | Aurelien Jarno | } |
615 | 5105c556 | Aurelien Jarno | |
616 | 8a56e840 | Richard Henderson | static inline void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret, |
617 | 8a56e840 | Richard Henderson | TCGv_i32 arg1, int32_t arg2) |
618 | 5105c556 | Aurelien Jarno | { |
619 | 5105c556 | Aurelien Jarno | TCGv_i32 t0 = tcg_const_i32(arg2); |
620 | 5105c556 | Aurelien Jarno | tcg_gen_setcond_i32(cond, ret, arg1, t0); |
621 | 5105c556 | Aurelien Jarno | tcg_temp_free_i32(t0); |
622 | 5105c556 | Aurelien Jarno | } |
623 | 5105c556 | Aurelien Jarno | |
624 | a7812ae4 | pbrook | static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
625 | c896fe29 | bellard | { |
626 | a7812ae4 | pbrook | tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2); |
627 | c896fe29 | bellard | } |
628 | c896fe29 | bellard | |
629 | a7812ae4 | pbrook | static inline void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
630 | f730fd27 | ths | { |
631 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_const_i32(arg2); |
632 | e8996ee0 | bellard | tcg_gen_mul_i32(ret, arg1, t0); |
633 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
634 | f730fd27 | ths | } |
635 | f730fd27 | ths | |
636 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_div_i32
|
637 | a7812ae4 | pbrook | static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
638 | c896fe29 | bellard | { |
639 | a7812ae4 | pbrook | tcg_gen_op3_i32(INDEX_op_div_i32, ret, arg1, arg2); |
640 | c896fe29 | bellard | } |
641 | c896fe29 | bellard | |
642 | a7812ae4 | pbrook | static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
643 | c896fe29 | bellard | { |
644 | a7812ae4 | pbrook | tcg_gen_op3_i32(INDEX_op_rem_i32, ret, arg1, arg2); |
645 | c896fe29 | bellard | } |
646 | c896fe29 | bellard | |
647 | a7812ae4 | pbrook | static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
648 | c896fe29 | bellard | { |
649 | a7812ae4 | pbrook | tcg_gen_op3_i32(INDEX_op_divu_i32, ret, arg1, arg2); |
650 | c896fe29 | bellard | } |
651 | c896fe29 | bellard | |
652 | a7812ae4 | pbrook | static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
653 | c896fe29 | bellard | { |
654 | a7812ae4 | pbrook | tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2); |
655 | c896fe29 | bellard | } |
656 | 31d66551 | Aurelien Jarno | #elif defined(TCG_TARGET_HAS_div2_i32)
|
657 | a7812ae4 | pbrook | static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
658 | c896fe29 | bellard | { |
659 | a7812ae4 | pbrook | TCGv_i32 t0; |
660 | a7812ae4 | pbrook | t0 = tcg_temp_new_i32(); |
661 | c896fe29 | bellard | tcg_gen_sari_i32(t0, arg1, 31);
|
662 | a7812ae4 | pbrook | tcg_gen_op5_i32(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2); |
663 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
664 | c896fe29 | bellard | } |
665 | c896fe29 | bellard | |
666 | a7812ae4 | pbrook | static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
667 | c896fe29 | bellard | { |
668 | a7812ae4 | pbrook | TCGv_i32 t0; |
669 | a7812ae4 | pbrook | t0 = tcg_temp_new_i32(); |
670 | c896fe29 | bellard | tcg_gen_sari_i32(t0, arg1, 31);
|
671 | a7812ae4 | pbrook | tcg_gen_op5_i32(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2); |
672 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
673 | c896fe29 | bellard | } |
674 | c896fe29 | bellard | |
675 | a7812ae4 | pbrook | static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
676 | c896fe29 | bellard | { |
677 | a7812ae4 | pbrook | TCGv_i32 t0; |
678 | a7812ae4 | pbrook | t0 = tcg_temp_new_i32(); |
679 | c896fe29 | bellard | tcg_gen_movi_i32(t0, 0);
|
680 | a7812ae4 | pbrook | tcg_gen_op5_i32(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2); |
681 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
682 | c896fe29 | bellard | } |
683 | c896fe29 | bellard | |
684 | a7812ae4 | pbrook | static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
685 | c896fe29 | bellard | { |
686 | a7812ae4 | pbrook | TCGv_i32 t0; |
687 | a7812ae4 | pbrook | t0 = tcg_temp_new_i32(); |
688 | c896fe29 | bellard | tcg_gen_movi_i32(t0, 0);
|
689 | a7812ae4 | pbrook | tcg_gen_op5_i32(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2); |
690 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
691 | c896fe29 | bellard | } |
692 | 31d66551 | Aurelien Jarno | #else
|
693 | 31d66551 | Aurelien Jarno | static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
694 | 31d66551 | Aurelien Jarno | { |
695 | 31d66551 | Aurelien Jarno | tcg_gen_helper32(tcg_helper_div_i32, ret, arg1, arg2); |
696 | 31d66551 | Aurelien Jarno | } |
697 | 31d66551 | Aurelien Jarno | |
698 | 31d66551 | Aurelien Jarno | static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
699 | 31d66551 | Aurelien Jarno | { |
700 | 31d66551 | Aurelien Jarno | tcg_gen_helper32(tcg_helper_rem_i32, ret, arg1, arg2); |
701 | 31d66551 | Aurelien Jarno | } |
702 | 31d66551 | Aurelien Jarno | |
703 | 31d66551 | Aurelien Jarno | static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
704 | 31d66551 | Aurelien Jarno | { |
705 | 31d66551 | Aurelien Jarno | tcg_gen_helper32(tcg_helper_divu_i32, ret, arg1, arg2); |
706 | 31d66551 | Aurelien Jarno | } |
707 | 31d66551 | Aurelien Jarno | |
708 | 31d66551 | Aurelien Jarno | static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
709 | 31d66551 | Aurelien Jarno | { |
710 | 31d66551 | Aurelien Jarno | tcg_gen_helper32(tcg_helper_remu_i32, ret, arg1, arg2); |
711 | 31d66551 | Aurelien Jarno | } |
712 | c896fe29 | bellard | #endif
|
713 | c896fe29 | bellard | |
714 | c896fe29 | bellard | #if TCG_TARGET_REG_BITS == 32 |
715 | c896fe29 | bellard | |
716 | a7812ae4 | pbrook | static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) |
717 | c896fe29 | bellard | { |
718 | fe75bcf7 | aurel32 | if (!TCGV_EQUAL_I64(ret, arg)) {
|
719 | a7812ae4 | pbrook | tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
720 | 4d07272d | blueswir1 | tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); |
721 | 4d07272d | blueswir1 | } |
722 | c896fe29 | bellard | } |
723 | c896fe29 | bellard | |
724 | a7812ae4 | pbrook | static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) |
725 | c896fe29 | bellard | { |
726 | a7812ae4 | pbrook | tcg_gen_movi_i32(TCGV_LOW(ret), arg); |
727 | ac56dd48 | pbrook | tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32);
|
728 | c896fe29 | bellard | } |
729 | c896fe29 | bellard | |
730 | a7812ae4 | pbrook | static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
731 | a7812ae4 | pbrook | tcg_target_long offset) |
732 | c896fe29 | bellard | { |
733 | a7812ae4 | pbrook | tcg_gen_ld8u_i32(TCGV_LOW(ret), arg2, offset); |
734 | ac56dd48 | pbrook | tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
735 | c896fe29 | bellard | } |
736 | c896fe29 | bellard | |
737 | a7812ae4 | pbrook | static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
738 | a7812ae4 | pbrook | tcg_target_long offset) |
739 | c896fe29 | bellard | { |
740 | a7812ae4 | pbrook | tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset); |
741 | a7812ae4 | pbrook | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), 31);
|
742 | c896fe29 | bellard | } |
743 | c896fe29 | bellard | |
744 | a7812ae4 | pbrook | static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
745 | a7812ae4 | pbrook | tcg_target_long offset) |
746 | c896fe29 | bellard | { |
747 | a747723b | aurel32 | tcg_gen_ld16u_i32(TCGV_LOW(ret), arg2, offset); |
748 | ac56dd48 | pbrook | tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
749 | c896fe29 | bellard | } |
750 | c896fe29 | bellard | |
751 | a7812ae4 | pbrook | static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
752 | a7812ae4 | pbrook | tcg_target_long offset) |
753 | c896fe29 | bellard | { |
754 | a7812ae4 | pbrook | tcg_gen_ld16s_i32(TCGV_LOW(ret), arg2, offset); |
755 | a7812ae4 | pbrook | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
756 | c896fe29 | bellard | } |
757 | c896fe29 | bellard | |
758 | a7812ae4 | pbrook | static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
759 | a7812ae4 | pbrook | tcg_target_long offset) |
760 | c896fe29 | bellard | { |
761 | a7812ae4 | pbrook | tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
762 | ac56dd48 | pbrook | tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
763 | c896fe29 | bellard | } |
764 | c896fe29 | bellard | |
765 | a7812ae4 | pbrook | static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
766 | a7812ae4 | pbrook | tcg_target_long offset) |
767 | c896fe29 | bellard | { |
768 | a7812ae4 | pbrook | tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
769 | a7812ae4 | pbrook | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
770 | c896fe29 | bellard | } |
771 | c896fe29 | bellard | |
772 | a7812ae4 | pbrook | static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, |
773 | a7812ae4 | pbrook | tcg_target_long offset) |
774 | c896fe29 | bellard | { |
775 | c896fe29 | bellard | /* since arg2 and ret have different types, they cannot be the
|
776 | c896fe29 | bellard | same temporary */
|
777 | c896fe29 | bellard | #ifdef TCG_TARGET_WORDS_BIGENDIAN
|
778 | ac56dd48 | pbrook | tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset); |
779 | a7812ae4 | pbrook | tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset + 4);
|
780 | c896fe29 | bellard | #else
|
781 | a7812ae4 | pbrook | tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
782 | ac56dd48 | pbrook | tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4);
|
783 | c896fe29 | bellard | #endif
|
784 | c896fe29 | bellard | } |
785 | c896fe29 | bellard | |
786 | a7812ae4 | pbrook | static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
787 | a7812ae4 | pbrook | tcg_target_long offset) |
788 | c896fe29 | bellard | { |
789 | a7812ae4 | pbrook | tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset); |
790 | c896fe29 | bellard | } |
791 | c896fe29 | bellard | |
792 | a7812ae4 | pbrook | static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
793 | a7812ae4 | pbrook | tcg_target_long offset) |
794 | c896fe29 | bellard | { |
795 | a7812ae4 | pbrook | tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset); |
796 | c896fe29 | bellard | } |
797 | c896fe29 | bellard | |
798 | a7812ae4 | pbrook | static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
799 | a7812ae4 | pbrook | tcg_target_long offset) |
800 | c896fe29 | bellard | { |
801 | a7812ae4 | pbrook | tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset); |
802 | c896fe29 | bellard | } |
803 | c896fe29 | bellard | |
804 | a7812ae4 | pbrook | static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
805 | a7812ae4 | pbrook | tcg_target_long offset) |
806 | c896fe29 | bellard | { |
807 | c896fe29 | bellard | #ifdef TCG_TARGET_WORDS_BIGENDIAN
|
808 | ac56dd48 | pbrook | tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset); |
809 | a7812ae4 | pbrook | tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset + 4);
|
810 | c896fe29 | bellard | #else
|
811 | a7812ae4 | pbrook | tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset); |
812 | ac56dd48 | pbrook | tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4);
|
813 | c896fe29 | bellard | #endif
|
814 | c896fe29 | bellard | } |
815 | c896fe29 | bellard | |
816 | a7812ae4 | pbrook | static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
817 | c896fe29 | bellard | { |
818 | a7812ae4 | pbrook | tcg_gen_op6_i32(INDEX_op_add2_i32, TCGV_LOW(ret), TCGV_HIGH(ret), |
819 | a7812ae4 | pbrook | TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), |
820 | a7812ae4 | pbrook | TCGV_HIGH(arg2)); |
821 | c896fe29 | bellard | } |
822 | c896fe29 | bellard | |
823 | a7812ae4 | pbrook | static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
824 | c896fe29 | bellard | { |
825 | a7812ae4 | pbrook | tcg_gen_op6_i32(INDEX_op_sub2_i32, TCGV_LOW(ret), TCGV_HIGH(ret), |
826 | a7812ae4 | pbrook | TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), |
827 | a7812ae4 | pbrook | TCGV_HIGH(arg2)); |
828 | c896fe29 | bellard | } |
829 | c896fe29 | bellard | |
830 | a7812ae4 | pbrook | static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
831 | c896fe29 | bellard | { |
832 | a7812ae4 | pbrook | tcg_gen_and_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
833 | ac56dd48 | pbrook | tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
834 | c896fe29 | bellard | } |
835 | c896fe29 | bellard | |
836 | a7812ae4 | pbrook | static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
837 | c896fe29 | bellard | { |
838 | e5105083 | aurel32 | tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
839 | e5105083 | aurel32 | tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
|
840 | c896fe29 | bellard | } |
841 | c896fe29 | bellard | |
842 | a7812ae4 | pbrook | static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
843 | c896fe29 | bellard | { |
844 | e5105083 | aurel32 | tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
845 | e5105083 | aurel32 | tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
846 | c896fe29 | bellard | } |
847 | c896fe29 | bellard | |
848 | a7812ae4 | pbrook | static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
849 | c896fe29 | bellard | { |
850 | a7812ae4 | pbrook | tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
851 | ac56dd48 | pbrook | tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
|
852 | c896fe29 | bellard | } |
853 | c896fe29 | bellard | |
854 | a7812ae4 | pbrook | static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
855 | c896fe29 | bellard | { |
856 | e5105083 | aurel32 | tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
857 | e5105083 | aurel32 | tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
858 | c896fe29 | bellard | } |
859 | c896fe29 | bellard | |
860 | a7812ae4 | pbrook | static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
861 | c896fe29 | bellard | { |
862 | a7812ae4 | pbrook | tcg_gen_xori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
863 | ac56dd48 | pbrook | tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
|
864 | c896fe29 | bellard | } |
865 | c896fe29 | bellard | |
866 | c896fe29 | bellard | /* XXX: use generic code when basic block handling is OK or CPU
|
867 | c896fe29 | bellard | specific code (x86) */
|
868 | a7812ae4 | pbrook | static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
869 | c896fe29 | bellard | { |
870 | a7812ae4 | pbrook | tcg_gen_helper64(tcg_helper_shl_i64, ret, arg1, arg2); |
871 | c896fe29 | bellard | } |
872 | c896fe29 | bellard | |
873 | a7812ae4 | pbrook | static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
874 | c896fe29 | bellard | { |
875 | c896fe29 | bellard | tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0); |
876 | c896fe29 | bellard | } |
877 | c896fe29 | bellard | |
878 | a7812ae4 | pbrook | static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
879 | c896fe29 | bellard | { |
880 | a7812ae4 | pbrook | tcg_gen_helper64(tcg_helper_shr_i64, ret, arg1, arg2); |
881 | c896fe29 | bellard | } |
882 | c896fe29 | bellard | |
883 | a7812ae4 | pbrook | static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
884 | c896fe29 | bellard | { |
885 | c896fe29 | bellard | tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0); |
886 | c896fe29 | bellard | } |
887 | c896fe29 | bellard | |
888 | a7812ae4 | pbrook | static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
889 | c896fe29 | bellard | { |
890 | a7812ae4 | pbrook | tcg_gen_helper64(tcg_helper_sar_i64, ret, arg1, arg2); |
891 | c896fe29 | bellard | } |
892 | c896fe29 | bellard | |
893 | a7812ae4 | pbrook | static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
894 | c896fe29 | bellard | { |
895 | c896fe29 | bellard | tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1); |
896 | c896fe29 | bellard | } |
897 | c896fe29 | bellard | |
898 | 8a56e840 | Richard Henderson | static inline void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, |
899 | 8a56e840 | Richard Henderson | TCGv_i64 arg2, int label_index)
|
900 | c896fe29 | bellard | { |
901 | a7812ae4 | pbrook | tcg_gen_op6ii_i32(INDEX_op_brcond2_i32, |
902 | a7812ae4 | pbrook | TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), |
903 | a7812ae4 | pbrook | TCGV_HIGH(arg2), cond, label_index); |
904 | c896fe29 | bellard | } |
905 | c896fe29 | bellard | |
906 | 8a56e840 | Richard Henderson | static inline void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, |
907 | 5105c556 | Aurelien Jarno | TCGv_i64 arg1, TCGv_i64 arg2) |
908 | 5105c556 | Aurelien Jarno | { |
909 | 5105c556 | Aurelien Jarno | tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret), |
910 | 5105c556 | Aurelien Jarno | TCGV_LOW(arg1), TCGV_HIGH(arg1), |
911 | 5105c556 | Aurelien Jarno | TCGV_LOW(arg2), TCGV_HIGH(arg2), cond); |
912 | 5105c556 | Aurelien Jarno | tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
913 | 5105c556 | Aurelien Jarno | } |
914 | 5105c556 | Aurelien Jarno | |
915 | a7812ae4 | pbrook | static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
916 | c896fe29 | bellard | { |
917 | a7812ae4 | pbrook | TCGv_i64 t0; |
918 | a7812ae4 | pbrook | TCGv_i32 t1; |
919 | c896fe29 | bellard | |
920 | a7812ae4 | pbrook | t0 = tcg_temp_new_i64(); |
921 | a7812ae4 | pbrook | t1 = tcg_temp_new_i32(); |
922 | a7812ae4 | pbrook | |
923 | a7812ae4 | pbrook | tcg_gen_op4_i32(INDEX_op_mulu2_i32, TCGV_LOW(t0), TCGV_HIGH(t0), |
924 | a7812ae4 | pbrook | TCGV_LOW(arg1), TCGV_LOW(arg2)); |
925 | a7812ae4 | pbrook | |
926 | a7812ae4 | pbrook | tcg_gen_mul_i32(t1, TCGV_LOW(arg1), TCGV_HIGH(arg2)); |
927 | ac56dd48 | pbrook | tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); |
928 | a7812ae4 | pbrook | tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), TCGV_LOW(arg2)); |
929 | ac56dd48 | pbrook | tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); |
930 | a7812ae4 | pbrook | |
931 | c896fe29 | bellard | tcg_gen_mov_i64(ret, t0); |
932 | a7812ae4 | pbrook | tcg_temp_free_i64(t0); |
933 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); |
934 | c896fe29 | bellard | } |
935 | c896fe29 | bellard | |
936 | a7812ae4 | pbrook | static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
937 | c896fe29 | bellard | { |
938 | a7812ae4 | pbrook | tcg_gen_helper64(tcg_helper_div_i64, ret, arg1, arg2); |
939 | c896fe29 | bellard | } |
940 | c896fe29 | bellard | |
941 | a7812ae4 | pbrook | static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
942 | c896fe29 | bellard | { |
943 | a7812ae4 | pbrook | tcg_gen_helper64(tcg_helper_rem_i64, ret, arg1, arg2); |
944 | c896fe29 | bellard | } |
945 | c896fe29 | bellard | |
946 | a7812ae4 | pbrook | static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
947 | c896fe29 | bellard | { |
948 | a7812ae4 | pbrook | tcg_gen_helper64(tcg_helper_divu_i64, ret, arg1, arg2); |
949 | c896fe29 | bellard | } |
950 | c896fe29 | bellard | |
951 | a7812ae4 | pbrook | static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
952 | c896fe29 | bellard | { |
953 | a7812ae4 | pbrook | tcg_gen_helper64(tcg_helper_remu_i64, ret, arg1, arg2); |
954 | c896fe29 | bellard | } |
955 | c896fe29 | bellard | |
956 | c896fe29 | bellard | #else
|
957 | c896fe29 | bellard | |
958 | a7812ae4 | pbrook | static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) |
959 | c896fe29 | bellard | { |
960 | fe75bcf7 | aurel32 | if (!TCGV_EQUAL_I64(ret, arg))
|
961 | a7812ae4 | pbrook | tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg); |
962 | c896fe29 | bellard | } |
963 | c896fe29 | bellard | |
964 | a7812ae4 | pbrook | static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) |
965 | c896fe29 | bellard | { |
966 | a7812ae4 | pbrook | tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg); |
967 | c896fe29 | bellard | } |
968 | c896fe29 | bellard | |
969 | a7812ae4 | pbrook | static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_i64 arg2, |
970 | ac56dd48 | pbrook | tcg_target_long offset) |
971 | c896fe29 | bellard | { |
972 | a7812ae4 | pbrook | tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset); |
973 | c896fe29 | bellard | } |
974 | c896fe29 | bellard | |
975 | a7812ae4 | pbrook | static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_i64 arg2, |
976 | ac56dd48 | pbrook | tcg_target_long offset) |
977 | c896fe29 | bellard | { |
978 | a7812ae4 | pbrook | tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset); |
979 | c896fe29 | bellard | } |
980 | c896fe29 | bellard | |
981 | a7812ae4 | pbrook | static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_i64 arg2, |
982 | ac56dd48 | pbrook | tcg_target_long offset) |
983 | c896fe29 | bellard | { |
984 | a7812ae4 | pbrook | tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset); |
985 | c896fe29 | bellard | } |
986 | c896fe29 | bellard | |
987 | a7812ae4 | pbrook | static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_i64 arg2, |
988 | ac56dd48 | pbrook | tcg_target_long offset) |
989 | c896fe29 | bellard | { |
990 | a7812ae4 | pbrook | tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset); |
991 | c896fe29 | bellard | } |
992 | c896fe29 | bellard | |
993 | a7812ae4 | pbrook | static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_i64 arg2, |
994 | ac56dd48 | pbrook | tcg_target_long offset) |
995 | c896fe29 | bellard | { |
996 | a7812ae4 | pbrook | tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset); |
997 | c896fe29 | bellard | } |
998 | c896fe29 | bellard | |
999 | a7812ae4 | pbrook | static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_i64 arg2, |
1000 | ac56dd48 | pbrook | tcg_target_long offset) |
1001 | c896fe29 | bellard | { |
1002 | a7812ae4 | pbrook | tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset); |
1003 | c896fe29 | bellard | } |
1004 | c896fe29 | bellard | |
1005 | a7812ae4 | pbrook | static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_i64 arg2, tcg_target_long offset) |
1006 | c896fe29 | bellard | { |
1007 | a7812ae4 | pbrook | tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset); |
1008 | c896fe29 | bellard | } |
1009 | c896fe29 | bellard | |
1010 | a7812ae4 | pbrook | static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_i64 arg2, |
1011 | ac56dd48 | pbrook | tcg_target_long offset) |
1012 | c896fe29 | bellard | { |
1013 | a7812ae4 | pbrook | tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset); |
1014 | c896fe29 | bellard | } |
1015 | c896fe29 | bellard | |
1016 | a7812ae4 | pbrook | static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_i64 arg2, |
1017 | ac56dd48 | pbrook | tcg_target_long offset) |
1018 | c896fe29 | bellard | { |
1019 | a7812ae4 | pbrook | tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset); |
1020 | c896fe29 | bellard | } |
1021 | c896fe29 | bellard | |
1022 | a7812ae4 | pbrook | static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_i64 arg2, |
1023 | ac56dd48 | pbrook | tcg_target_long offset) |
1024 | c896fe29 | bellard | { |
1025 | a7812ae4 | pbrook | tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset); |
1026 | c896fe29 | bellard | } |
1027 | c896fe29 | bellard | |
1028 | a7812ae4 | pbrook | static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_i64 arg2, tcg_target_long offset) |
1029 | c896fe29 | bellard | { |
1030 | a7812ae4 | pbrook | tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset); |
1031 | c896fe29 | bellard | } |
1032 | c896fe29 | bellard | |
1033 | a7812ae4 | pbrook | static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1034 | c896fe29 | bellard | { |
1035 | a7812ae4 | pbrook | tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2); |
1036 | c896fe29 | bellard | } |
1037 | c896fe29 | bellard | |
1038 | a7812ae4 | pbrook | static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1039 | c896fe29 | bellard | { |
1040 | a7812ae4 | pbrook | tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2); |
1041 | c896fe29 | bellard | } |
1042 | c896fe29 | bellard | |
1043 | a7812ae4 | pbrook | static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1044 | c896fe29 | bellard | { |
1045 | 7fc81051 | aurel32 | if (TCGV_EQUAL_I64(arg1, arg2)) {
|
1046 | 7fc81051 | aurel32 | tcg_gen_mov_i64(ret, arg1); |
1047 | 7fc81051 | aurel32 | } else {
|
1048 | 7fc81051 | aurel32 | tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2); |
1049 | 7fc81051 | aurel32 | } |
1050 | c896fe29 | bellard | } |
1051 | c896fe29 | bellard | |
1052 | a7812ae4 | pbrook | static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1053 | c896fe29 | bellard | { |
1054 | a7812ae4 | pbrook | TCGv_i64 t0 = tcg_const_i64(arg2); |
1055 | e8996ee0 | bellard | tcg_gen_and_i64(ret, arg1, t0); |
1056 | a7812ae4 | pbrook | tcg_temp_free_i64(t0); |
1057 | c896fe29 | bellard | } |
1058 | c896fe29 | bellard | |
1059 | a7812ae4 | pbrook | static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1060 | c896fe29 | bellard | { |
1061 | 7fc81051 | aurel32 | if (TCGV_EQUAL_I64(arg1, arg2)) {
|
1062 | 7fc81051 | aurel32 | tcg_gen_mov_i64(ret, arg1); |
1063 | 7fc81051 | aurel32 | } else {
|
1064 | 7fc81051 | aurel32 | tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2); |
1065 | 7fc81051 | aurel32 | } |
1066 | c896fe29 | bellard | } |
1067 | c896fe29 | bellard | |
1068 | a7812ae4 | pbrook | static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1069 | c896fe29 | bellard | { |
1070 | a7812ae4 | pbrook | TCGv_i64 t0 = tcg_const_i64(arg2); |
1071 | e8996ee0 | bellard | tcg_gen_or_i64(ret, arg1, t0); |
1072 | a7812ae4 | pbrook | tcg_temp_free_i64(t0); |
1073 | c896fe29 | bellard | } |
1074 | c896fe29 | bellard | |
1075 | a7812ae4 | pbrook | static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1076 | c896fe29 | bellard | { |
1077 | 7fc81051 | aurel32 | if (TCGV_EQUAL_I64(arg1, arg2)) {
|
1078 | 7fc81051 | aurel32 | tcg_gen_movi_i64(ret, 0);
|
1079 | 7fc81051 | aurel32 | } else {
|
1080 | 7fc81051 | aurel32 | tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2); |
1081 | 7fc81051 | aurel32 | } |
1082 | c896fe29 | bellard | } |
1083 | c896fe29 | bellard | |
1084 | a7812ae4 | pbrook | static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1085 | c896fe29 | bellard | { |
1086 | a7812ae4 | pbrook | TCGv_i64 t0 = tcg_const_i64(arg2); |
1087 | e8996ee0 | bellard | tcg_gen_xor_i64(ret, arg1, t0); |
1088 | a7812ae4 | pbrook | tcg_temp_free_i64(t0); |
1089 | c896fe29 | bellard | } |
1090 | c896fe29 | bellard | |
1091 | a7812ae4 | pbrook | static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1092 | c896fe29 | bellard | { |
1093 | a7812ae4 | pbrook | tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2); |
1094 | c896fe29 | bellard | } |
1095 | c896fe29 | bellard | |
1096 | a7812ae4 | pbrook | static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1097 | c896fe29 | bellard | { |
1098 | 34151a20 | bellard | if (arg2 == 0) { |
1099 | 34151a20 | bellard | tcg_gen_mov_i64(ret, arg1); |
1100 | 34151a20 | bellard | } else {
|
1101 | a7812ae4 | pbrook | TCGv_i64 t0 = tcg_const_i64(arg2); |
1102 | e8996ee0 | bellard | tcg_gen_shl_i64(ret, arg1, t0); |
1103 | a7812ae4 | pbrook | tcg_temp_free_i64(t0); |
1104 | 34151a20 | bellard | } |
1105 | c896fe29 | bellard | } |
1106 | c896fe29 | bellard | |
1107 | a7812ae4 | pbrook | static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1108 | c896fe29 | bellard | { |
1109 | a7812ae4 | pbrook | tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2); |
1110 | c896fe29 | bellard | } |
1111 | c896fe29 | bellard | |
1112 | a7812ae4 | pbrook | static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1113 | c896fe29 | bellard | { |
1114 | 34151a20 | bellard | if (arg2 == 0) { |
1115 | 34151a20 | bellard | tcg_gen_mov_i64(ret, arg1); |
1116 | 34151a20 | bellard | } else {
|
1117 | a7812ae4 | pbrook | TCGv_i64 t0 = tcg_const_i64(arg2); |
1118 | e8996ee0 | bellard | tcg_gen_shr_i64(ret, arg1, t0); |
1119 | a7812ae4 | pbrook | tcg_temp_free_i64(t0); |
1120 | 34151a20 | bellard | } |
1121 | c896fe29 | bellard | } |
1122 | c896fe29 | bellard | |
1123 | a7812ae4 | pbrook | static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1124 | c896fe29 | bellard | { |
1125 | a7812ae4 | pbrook | tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2); |
1126 | c896fe29 | bellard | } |
1127 | c896fe29 | bellard | |
1128 | a7812ae4 | pbrook | static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1129 | c896fe29 | bellard | { |
1130 | 34151a20 | bellard | if (arg2 == 0) { |
1131 | 34151a20 | bellard | tcg_gen_mov_i64(ret, arg1); |
1132 | 34151a20 | bellard | } else {
|
1133 | a7812ae4 | pbrook | TCGv_i64 t0 = tcg_const_i64(arg2); |
1134 | e8996ee0 | bellard | tcg_gen_sar_i64(ret, arg1, t0); |
1135 | a7812ae4 | pbrook | tcg_temp_free_i64(t0); |
1136 | 34151a20 | bellard | } |
1137 | c896fe29 | bellard | } |
1138 | c896fe29 | bellard | |
1139 | 8a56e840 | Richard Henderson | static inline void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, |
1140 | 8a56e840 | Richard Henderson | TCGv_i64 arg2, int label_index)
|
1141 | c896fe29 | bellard | { |
1142 | a7812ae4 | pbrook | tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond, label_index); |
1143 | c896fe29 | bellard | } |
1144 | c896fe29 | bellard | |
1145 | 8a56e840 | Richard Henderson | static inline void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, |
1146 | 5105c556 | Aurelien Jarno | TCGv_i64 arg1, TCGv_i64 arg2) |
1147 | 5105c556 | Aurelien Jarno | { |
1148 | 5105c556 | Aurelien Jarno | tcg_gen_op4i_i64(INDEX_op_setcond_i64, ret, arg1, arg2, cond); |
1149 | 5105c556 | Aurelien Jarno | } |
1150 | 5105c556 | Aurelien Jarno | |
1151 | a7812ae4 | pbrook | static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1152 | c896fe29 | bellard | { |
1153 | a7812ae4 | pbrook | tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2); |
1154 | c896fe29 | bellard | } |
1155 | c896fe29 | bellard | |
1156 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_div_i64
|
1157 | a7812ae4 | pbrook | static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1158 | c896fe29 | bellard | { |
1159 | a7812ae4 | pbrook | tcg_gen_op3_i64(INDEX_op_div_i64, ret, arg1, arg2); |
1160 | c896fe29 | bellard | } |
1161 | c896fe29 | bellard | |
1162 | a7812ae4 | pbrook | static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1163 | c896fe29 | bellard | { |
1164 | a7812ae4 | pbrook | tcg_gen_op3_i64(INDEX_op_rem_i64, ret, arg1, arg2); |
1165 | c896fe29 | bellard | } |
1166 | c896fe29 | bellard | |
1167 | a7812ae4 | pbrook | static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1168 | c896fe29 | bellard | { |
1169 | a7812ae4 | pbrook | tcg_gen_op3_i64(INDEX_op_divu_i64, ret, arg1, arg2); |
1170 | c896fe29 | bellard | } |
1171 | c896fe29 | bellard | |
1172 | a7812ae4 | pbrook | static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1173 | c896fe29 | bellard | { |
1174 | a7812ae4 | pbrook | tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2); |
1175 | c896fe29 | bellard | } |
1176 | 31d66551 | Aurelien Jarno | #elif defined(TCG_TARGET_HAS_div2_i64)
|
1177 | a7812ae4 | pbrook | static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1178 | c896fe29 | bellard | { |
1179 | a7812ae4 | pbrook | TCGv_i64 t0; |
1180 | a7812ae4 | pbrook | t0 = tcg_temp_new_i64(); |
1181 | c896fe29 | bellard | tcg_gen_sari_i64(t0, arg1, 63);
|
1182 | a7812ae4 | pbrook | tcg_gen_op5_i64(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2); |
1183 | a7812ae4 | pbrook | tcg_temp_free_i64(t0); |
1184 | c896fe29 | bellard | } |
1185 | c896fe29 | bellard | |
1186 | a7812ae4 | pbrook | static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1187 | c896fe29 | bellard | { |
1188 | a7812ae4 | pbrook | TCGv_i64 t0; |
1189 | a7812ae4 | pbrook | t0 = tcg_temp_new_i64(); |
1190 | c896fe29 | bellard | tcg_gen_sari_i64(t0, arg1, 63);
|
1191 | a7812ae4 | pbrook | tcg_gen_op5_i64(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2); |
1192 | a7812ae4 | pbrook | tcg_temp_free_i64(t0); |
1193 | c896fe29 | bellard | } |
1194 | c896fe29 | bellard | |
1195 | a7812ae4 | pbrook | static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1196 | c896fe29 | bellard | { |
1197 | a7812ae4 | pbrook | TCGv_i64 t0; |
1198 | a7812ae4 | pbrook | t0 = tcg_temp_new_i64(); |
1199 | c896fe29 | bellard | tcg_gen_movi_i64(t0, 0);
|
1200 | a7812ae4 | pbrook | tcg_gen_op5_i64(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2); |
1201 | a7812ae4 | pbrook | tcg_temp_free_i64(t0); |
1202 | c896fe29 | bellard | } |
1203 | c896fe29 | bellard | |
1204 | a7812ae4 | pbrook | static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1205 | c896fe29 | bellard | { |
1206 | a7812ae4 | pbrook | TCGv_i64 t0; |
1207 | a7812ae4 | pbrook | t0 = tcg_temp_new_i64(); |
1208 | c896fe29 | bellard | tcg_gen_movi_i64(t0, 0);
|
1209 | a7812ae4 | pbrook | tcg_gen_op5_i64(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2); |
1210 | a7812ae4 | pbrook | tcg_temp_free_i64(t0); |
1211 | c896fe29 | bellard | } |
1212 | 31d66551 | Aurelien Jarno | #else
|
1213 | 31d66551 | Aurelien Jarno | static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1214 | 31d66551 | Aurelien Jarno | { |
1215 | 31d66551 | Aurelien Jarno | tcg_gen_helper64(tcg_helper_div_i64, ret, arg1, arg2); |
1216 | 31d66551 | Aurelien Jarno | } |
1217 | 31d66551 | Aurelien Jarno | |
1218 | 31d66551 | Aurelien Jarno | static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1219 | 31d66551 | Aurelien Jarno | { |
1220 | 31d66551 | Aurelien Jarno | tcg_gen_helper64(tcg_helper_rem_i64, ret, arg1, arg2); |
1221 | 31d66551 | Aurelien Jarno | } |
1222 | 31d66551 | Aurelien Jarno | |
1223 | 31d66551 | Aurelien Jarno | static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1224 | 31d66551 | Aurelien Jarno | { |
1225 | 31d66551 | Aurelien Jarno | tcg_gen_helper64(tcg_helper_divu_i64, ret, arg1, arg2); |
1226 | 31d66551 | Aurelien Jarno | } |
1227 | 31d66551 | Aurelien Jarno | |
1228 | 31d66551 | Aurelien Jarno | static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1229 | 31d66551 | Aurelien Jarno | { |
1230 | 31d66551 | Aurelien Jarno | tcg_gen_helper64(tcg_helper_remu_i64, ret, arg1, arg2); |
1231 | 31d66551 | Aurelien Jarno | } |
1232 | c896fe29 | bellard | #endif
|
1233 | c896fe29 | bellard | |
1234 | c896fe29 | bellard | #endif
|
1235 | c896fe29 | bellard | |
1236 | a7812ae4 | pbrook | static inline void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1237 | 6359706f | aurel32 | { |
1238 | 6359706f | aurel32 | /* some cases can be optimized here */
|
1239 | 6359706f | aurel32 | if (arg2 == 0) { |
1240 | 6359706f | aurel32 | tcg_gen_mov_i64(ret, arg1); |
1241 | 6359706f | aurel32 | } else {
|
1242 | a7812ae4 | pbrook | TCGv_i64 t0 = tcg_const_i64(arg2); |
1243 | 6359706f | aurel32 | tcg_gen_add_i64(ret, arg1, t0); |
1244 | a7812ae4 | pbrook | tcg_temp_free_i64(t0); |
1245 | 6359706f | aurel32 | } |
1246 | 6359706f | aurel32 | } |
1247 | 6359706f | aurel32 | |
1248 | a7812ae4 | pbrook | static inline void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2) |
1249 | 0045734a | aurel32 | { |
1250 | a7812ae4 | pbrook | TCGv_i64 t0 = tcg_const_i64(arg1); |
1251 | 0045734a | aurel32 | tcg_gen_sub_i64(ret, t0, arg2); |
1252 | a7812ae4 | pbrook | tcg_temp_free_i64(t0); |
1253 | 0045734a | aurel32 | } |
1254 | 0045734a | aurel32 | |
1255 | a7812ae4 | pbrook | static inline void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1256 | 6359706f | aurel32 | { |
1257 | 6359706f | aurel32 | /* some cases can be optimized here */
|
1258 | 6359706f | aurel32 | if (arg2 == 0) { |
1259 | 6359706f | aurel32 | tcg_gen_mov_i64(ret, arg1); |
1260 | 6359706f | aurel32 | } else {
|
1261 | a7812ae4 | pbrook | TCGv_i64 t0 = tcg_const_i64(arg2); |
1262 | 6359706f | aurel32 | tcg_gen_sub_i64(ret, arg1, t0); |
1263 | a7812ae4 | pbrook | tcg_temp_free_i64(t0); |
1264 | 6359706f | aurel32 | } |
1265 | 6359706f | aurel32 | } |
1266 | 8a56e840 | Richard Henderson | static inline void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, |
1267 | 8a56e840 | Richard Henderson | int64_t arg2, int label_index)
|
1268 | f02bb954 | aurel32 | { |
1269 | a7812ae4 | pbrook | TCGv_i64 t0 = tcg_const_i64(arg2); |
1270 | f02bb954 | aurel32 | tcg_gen_brcond_i64(cond, arg1, t0, label_index); |
1271 | a7812ae4 | pbrook | tcg_temp_free_i64(t0); |
1272 | f02bb954 | aurel32 | } |
1273 | f02bb954 | aurel32 | |
1274 | 8a56e840 | Richard Henderson | static inline void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret, |
1275 | 8a56e840 | Richard Henderson | TCGv_i64 arg1, int64_t arg2) |
1276 | 5105c556 | Aurelien Jarno | { |
1277 | 5105c556 | Aurelien Jarno | TCGv_i64 t0 = tcg_const_i64(arg2); |
1278 | 5105c556 | Aurelien Jarno | tcg_gen_setcond_i64(cond, ret, arg1, t0); |
1279 | 5105c556 | Aurelien Jarno | tcg_temp_free_i64(t0); |
1280 | 5105c556 | Aurelien Jarno | } |
1281 | 5105c556 | Aurelien Jarno | |
1282 | a7812ae4 | pbrook | static inline void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1283 | f02bb954 | aurel32 | { |
1284 | a7812ae4 | pbrook | TCGv_i64 t0 = tcg_const_i64(arg2); |
1285 | f02bb954 | aurel32 | tcg_gen_mul_i64(ret, arg1, t0); |
1286 | a7812ae4 | pbrook | tcg_temp_free_i64(t0); |
1287 | f02bb954 | aurel32 | } |
1288 | f02bb954 | aurel32 | |
1289 | 6359706f | aurel32 | |
1290 | c896fe29 | bellard | /***************************************/
|
1291 | c896fe29 | bellard | /* optional operations */
|
1292 | c896fe29 | bellard | |
1293 | a7812ae4 | pbrook | static inline void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg) |
1294 | c896fe29 | bellard | { |
1295 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_ext8s_i32
|
1296 | a7812ae4 | pbrook | tcg_gen_op2_i32(INDEX_op_ext8s_i32, ret, arg); |
1297 | c896fe29 | bellard | #else
|
1298 | c896fe29 | bellard | tcg_gen_shli_i32(ret, arg, 24);
|
1299 | 5ff9d6a4 | bellard | tcg_gen_sari_i32(ret, ret, 24);
|
1300 | c896fe29 | bellard | #endif
|
1301 | c896fe29 | bellard | } |
1302 | c896fe29 | bellard | |
1303 | a7812ae4 | pbrook | static inline void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg) |
1304 | c896fe29 | bellard | { |
1305 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_ext16s_i32
|
1306 | a7812ae4 | pbrook | tcg_gen_op2_i32(INDEX_op_ext16s_i32, ret, arg); |
1307 | c896fe29 | bellard | #else
|
1308 | c896fe29 | bellard | tcg_gen_shli_i32(ret, arg, 16);
|
1309 | 5ff9d6a4 | bellard | tcg_gen_sari_i32(ret, ret, 16);
|
1310 | c896fe29 | bellard | #endif
|
1311 | c896fe29 | bellard | } |
1312 | c896fe29 | bellard | |
1313 | a7812ae4 | pbrook | static inline void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg) |
1314 | 86831435 | pbrook | { |
1315 | cfc86988 | Aurelien Jarno | #ifdef TCG_TARGET_HAS_ext8u_i32
|
1316 | cfc86988 | Aurelien Jarno | tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg); |
1317 | cfc86988 | Aurelien Jarno | #else
|
1318 | 86831435 | pbrook | tcg_gen_andi_i32(ret, arg, 0xffu);
|
1319 | cfc86988 | Aurelien Jarno | #endif
|
1320 | 86831435 | pbrook | } |
1321 | 86831435 | pbrook | |
1322 | a7812ae4 | pbrook | static inline void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg) |
1323 | 86831435 | pbrook | { |
1324 | cfc86988 | Aurelien Jarno | #ifdef TCG_TARGET_HAS_ext16u_i32
|
1325 | cfc86988 | Aurelien Jarno | tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg); |
1326 | cfc86988 | Aurelien Jarno | #else
|
1327 | 86831435 | pbrook | tcg_gen_andi_i32(ret, arg, 0xffffu);
|
1328 | cfc86988 | Aurelien Jarno | #endif
|
1329 | 86831435 | pbrook | } |
1330 | 86831435 | pbrook | |
1331 | c896fe29 | bellard | /* Note: we assume the two high bytes are set to zero */
|
1332 | a7812ae4 | pbrook | static inline void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg) |
1333 | c896fe29 | bellard | { |
1334 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_bswap16_i32
|
1335 | a7812ae4 | pbrook | tcg_gen_op2_i32(INDEX_op_bswap16_i32, ret, arg); |
1336 | c896fe29 | bellard | #else
|
1337 | dfa1a3f1 | aurel32 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1338 | c896fe29 | bellard | |
1339 | dfa1a3f1 | aurel32 | tcg_gen_ext8u_i32(t0, arg); |
1340 | dfa1a3f1 | aurel32 | tcg_gen_shli_i32(t0, t0, 8);
|
1341 | dfa1a3f1 | aurel32 | tcg_gen_shri_i32(ret, arg, 8);
|
1342 | dfa1a3f1 | aurel32 | tcg_gen_or_i32(ret, ret, t0); |
1343 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
1344 | c896fe29 | bellard | #endif
|
1345 | c896fe29 | bellard | } |
1346 | c896fe29 | bellard | |
1347 | 66896cb8 | aurel32 | static inline void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg) |
1348 | c896fe29 | bellard | { |
1349 | 66896cb8 | aurel32 | #ifdef TCG_TARGET_HAS_bswap32_i32
|
1350 | 66896cb8 | aurel32 | tcg_gen_op2_i32(INDEX_op_bswap32_i32, ret, arg); |
1351 | c896fe29 | bellard | #else
|
1352 | a7812ae4 | pbrook | TCGv_i32 t0, t1; |
1353 | a7812ae4 | pbrook | t0 = tcg_temp_new_i32(); |
1354 | a7812ae4 | pbrook | t1 = tcg_temp_new_i32(); |
1355 | c896fe29 | bellard | |
1356 | c896fe29 | bellard | tcg_gen_shli_i32(t0, arg, 24);
|
1357 | c896fe29 | bellard | |
1358 | c896fe29 | bellard | tcg_gen_andi_i32(t1, arg, 0x0000ff00);
|
1359 | c896fe29 | bellard | tcg_gen_shli_i32(t1, t1, 8);
|
1360 | c896fe29 | bellard | tcg_gen_or_i32(t0, t0, t1); |
1361 | c896fe29 | bellard | |
1362 | c896fe29 | bellard | tcg_gen_shri_i32(t1, arg, 8);
|
1363 | c896fe29 | bellard | tcg_gen_andi_i32(t1, t1, 0x0000ff00);
|
1364 | c896fe29 | bellard | tcg_gen_or_i32(t0, t0, t1); |
1365 | c896fe29 | bellard | |
1366 | c896fe29 | bellard | tcg_gen_shri_i32(t1, arg, 24);
|
1367 | c896fe29 | bellard | tcg_gen_or_i32(ret, t0, t1); |
1368 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
1369 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); |
1370 | c896fe29 | bellard | #endif
|
1371 | c896fe29 | bellard | } |
1372 | c896fe29 | bellard | |
1373 | c896fe29 | bellard | #if TCG_TARGET_REG_BITS == 32 |
1374 | a7812ae4 | pbrook | static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg) |
1375 | c896fe29 | bellard | { |
1376 | a7812ae4 | pbrook | tcg_gen_ext8s_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1377 | a7812ae4 | pbrook | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
1378 | c896fe29 | bellard | } |
1379 | c896fe29 | bellard | |
1380 | a7812ae4 | pbrook | static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg) |
1381 | c896fe29 | bellard | { |
1382 | a7812ae4 | pbrook | tcg_gen_ext16s_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1383 | a7812ae4 | pbrook | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
1384 | c896fe29 | bellard | } |
1385 | c896fe29 | bellard | |
1386 | a7812ae4 | pbrook | static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg) |
1387 | c896fe29 | bellard | { |
1388 | a7812ae4 | pbrook | tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1389 | a7812ae4 | pbrook | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
1390 | c896fe29 | bellard | } |
1391 | c896fe29 | bellard | |
1392 | a7812ae4 | pbrook | static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg) |
1393 | 86831435 | pbrook | { |
1394 | a7812ae4 | pbrook | tcg_gen_ext8u_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1395 | 86831435 | pbrook | tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
1396 | 86831435 | pbrook | } |
1397 | 86831435 | pbrook | |
1398 | a7812ae4 | pbrook | static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg) |
1399 | 86831435 | pbrook | { |
1400 | a7812ae4 | pbrook | tcg_gen_ext16u_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1401 | 86831435 | pbrook | tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
1402 | 86831435 | pbrook | } |
1403 | 86831435 | pbrook | |
1404 | a7812ae4 | pbrook | static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg) |
1405 | 86831435 | pbrook | { |
1406 | a7812ae4 | pbrook | tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1407 | 86831435 | pbrook | tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
1408 | 86831435 | pbrook | } |
1409 | 86831435 | pbrook | |
1410 | a7812ae4 | pbrook | static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg) |
1411 | c896fe29 | bellard | { |
1412 | a7812ae4 | pbrook | tcg_gen_mov_i32(ret, TCGV_LOW(arg)); |
1413 | c896fe29 | bellard | } |
1414 | c896fe29 | bellard | |
1415 | a7812ae4 | pbrook | static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
1416 | c896fe29 | bellard | { |
1417 | a7812ae4 | pbrook | tcg_gen_mov_i32(TCGV_LOW(ret), arg); |
1418 | ac56dd48 | pbrook | tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
1419 | c896fe29 | bellard | } |
1420 | c896fe29 | bellard | |
1421 | a7812ae4 | pbrook | static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
1422 | c896fe29 | bellard | { |
1423 | a7812ae4 | pbrook | tcg_gen_mov_i32(TCGV_LOW(ret), arg); |
1424 | a7812ae4 | pbrook | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
1425 | c896fe29 | bellard | } |
1426 | c896fe29 | bellard | |
1427 | 9a5c57fd | aurel32 | /* Note: we assume the six high bytes are set to zero */
|
1428 | 9a5c57fd | aurel32 | static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg) |
1429 | 9a5c57fd | aurel32 | { |
1430 | 9a5c57fd | aurel32 | tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); |
1431 | 9a5c57fd | aurel32 | tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1432 | 9a5c57fd | aurel32 | } |
1433 | 9a5c57fd | aurel32 | |
1434 | 9a5c57fd | aurel32 | /* Note: we assume the four high bytes are set to zero */
|
1435 | 9a5c57fd | aurel32 | static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) |
1436 | 9a5c57fd | aurel32 | { |
1437 | 9a5c57fd | aurel32 | tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); |
1438 | 9a5c57fd | aurel32 | tcg_gen_bswap32_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1439 | 9a5c57fd | aurel32 | } |
1440 | 9a5c57fd | aurel32 | |
1441 | 66896cb8 | aurel32 | static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) |
1442 | c896fe29 | bellard | { |
1443 | a7812ae4 | pbrook | TCGv_i32 t0, t1; |
1444 | a7812ae4 | pbrook | t0 = tcg_temp_new_i32(); |
1445 | a7812ae4 | pbrook | t1 = tcg_temp_new_i32(); |
1446 | c896fe29 | bellard | |
1447 | 66896cb8 | aurel32 | tcg_gen_bswap32_i32(t0, TCGV_LOW(arg)); |
1448 | 66896cb8 | aurel32 | tcg_gen_bswap32_i32(t1, TCGV_HIGH(arg)); |
1449 | a7812ae4 | pbrook | tcg_gen_mov_i32(TCGV_LOW(ret), t1); |
1450 | ac56dd48 | pbrook | tcg_gen_mov_i32(TCGV_HIGH(ret), t0); |
1451 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
1452 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); |
1453 | c896fe29 | bellard | } |
1454 | c896fe29 | bellard | #else
|
1455 | c896fe29 | bellard | |
1456 | a7812ae4 | pbrook | static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg) |
1457 | c896fe29 | bellard | { |
1458 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_ext8s_i64
|
1459 | a7812ae4 | pbrook | tcg_gen_op2_i64(INDEX_op_ext8s_i64, ret, arg); |
1460 | c896fe29 | bellard | #else
|
1461 | c896fe29 | bellard | tcg_gen_shli_i64(ret, arg, 56);
|
1462 | 5ff9d6a4 | bellard | tcg_gen_sari_i64(ret, ret, 56);
|
1463 | c896fe29 | bellard | #endif
|
1464 | c896fe29 | bellard | } |
1465 | c896fe29 | bellard | |
1466 | a7812ae4 | pbrook | static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg) |
1467 | c896fe29 | bellard | { |
1468 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_ext16s_i64
|
1469 | a7812ae4 | pbrook | tcg_gen_op2_i64(INDEX_op_ext16s_i64, ret, arg); |
1470 | c896fe29 | bellard | #else
|
1471 | c896fe29 | bellard | tcg_gen_shli_i64(ret, arg, 48);
|
1472 | 5ff9d6a4 | bellard | tcg_gen_sari_i64(ret, ret, 48);
|
1473 | c896fe29 | bellard | #endif
|
1474 | c896fe29 | bellard | } |
1475 | c896fe29 | bellard | |
1476 | a7812ae4 | pbrook | static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg) |
1477 | c896fe29 | bellard | { |
1478 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_ext32s_i64
|
1479 | a7812ae4 | pbrook | tcg_gen_op2_i64(INDEX_op_ext32s_i64, ret, arg); |
1480 | c896fe29 | bellard | #else
|
1481 | c896fe29 | bellard | tcg_gen_shli_i64(ret, arg, 32);
|
1482 | 5ff9d6a4 | bellard | tcg_gen_sari_i64(ret, ret, 32);
|
1483 | c896fe29 | bellard | #endif
|
1484 | c896fe29 | bellard | } |
1485 | c896fe29 | bellard | |
1486 | a7812ae4 | pbrook | static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg) |
1487 | 86831435 | pbrook | { |
1488 | cfc86988 | Aurelien Jarno | #ifdef TCG_TARGET_HAS_ext8u_i64
|
1489 | cfc86988 | Aurelien Jarno | tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg); |
1490 | cfc86988 | Aurelien Jarno | #else
|
1491 | 86831435 | pbrook | tcg_gen_andi_i64(ret, arg, 0xffu);
|
1492 | cfc86988 | Aurelien Jarno | #endif
|
1493 | 86831435 | pbrook | } |
1494 | 86831435 | pbrook | |
1495 | a7812ae4 | pbrook | static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg) |
1496 | 86831435 | pbrook | { |
1497 | cfc86988 | Aurelien Jarno | #ifdef TCG_TARGET_HAS_ext16u_i64
|
1498 | cfc86988 | Aurelien Jarno | tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg); |
1499 | cfc86988 | Aurelien Jarno | #else
|
1500 | 86831435 | pbrook | tcg_gen_andi_i64(ret, arg, 0xffffu);
|
1501 | cfc86988 | Aurelien Jarno | #endif
|
1502 | 86831435 | pbrook | } |
1503 | 86831435 | pbrook | |
1504 | a7812ae4 | pbrook | static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg) |
1505 | 86831435 | pbrook | { |
1506 | cfc86988 | Aurelien Jarno | #ifdef TCG_TARGET_HAS_ext32u_i64
|
1507 | cfc86988 | Aurelien Jarno | tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg); |
1508 | cfc86988 | Aurelien Jarno | #else
|
1509 | 86831435 | pbrook | tcg_gen_andi_i64(ret, arg, 0xffffffffu);
|
1510 | cfc86988 | Aurelien Jarno | #endif
|
1511 | 86831435 | pbrook | } |
1512 | 86831435 | pbrook | |
1513 | c896fe29 | bellard | /* Note: we assume the target supports move between 32 and 64 bit
|
1514 | ac56dd48 | pbrook | registers. This will probably break MIPS64 targets. */
|
1515 | a7812ae4 | pbrook | static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg) |
1516 | c896fe29 | bellard | { |
1517 | a7812ae4 | pbrook | tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg))); |
1518 | c896fe29 | bellard | } |
1519 | c896fe29 | bellard | |
1520 | c896fe29 | bellard | /* Note: we assume the target supports move between 32 and 64 bit
|
1521 | c896fe29 | bellard | registers */
|
1522 | a7812ae4 | pbrook | static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
1523 | c896fe29 | bellard | { |
1524 | cfc86988 | Aurelien Jarno | tcg_gen_ext32u_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg))); |
1525 | c896fe29 | bellard | } |
1526 | c896fe29 | bellard | |
1527 | c896fe29 | bellard | /* Note: we assume the target supports move between 32 and 64 bit
|
1528 | c896fe29 | bellard | registers */
|
1529 | a7812ae4 | pbrook | static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
1530 | c896fe29 | bellard | { |
1531 | a7812ae4 | pbrook | tcg_gen_ext32s_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg))); |
1532 | c896fe29 | bellard | } |
1533 | c896fe29 | bellard | |
1534 | 9a5c57fd | aurel32 | /* Note: we assume the six high bytes are set to zero */
|
1535 | 9a5c57fd | aurel32 | static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg) |
1536 | 9a5c57fd | aurel32 | { |
1537 | 9a5c57fd | aurel32 | #ifdef TCG_TARGET_HAS_bswap16_i64
|
1538 | 9a5c57fd | aurel32 | tcg_gen_op2_i64(INDEX_op_bswap16_i64, ret, arg); |
1539 | 9a5c57fd | aurel32 | #else
|
1540 | 9a5c57fd | aurel32 | TCGv_i64 t0 = tcg_temp_new_i64(); |
1541 | 9a5c57fd | aurel32 | |
1542 | 9a5c57fd | aurel32 | tcg_gen_ext8u_i64(t0, arg); |
1543 | 9a5c57fd | aurel32 | tcg_gen_shli_i64(t0, t0, 8);
|
1544 | 9a5c57fd | aurel32 | tcg_gen_shri_i64(ret, arg, 8);
|
1545 | 9a5c57fd | aurel32 | tcg_gen_or_i64(ret, ret, t0); |
1546 | 9a5c57fd | aurel32 | tcg_temp_free_i64(t0); |
1547 | 9a5c57fd | aurel32 | #endif
|
1548 | 9a5c57fd | aurel32 | } |
1549 | 9a5c57fd | aurel32 | |
1550 | 9a5c57fd | aurel32 | /* Note: we assume the four high bytes are set to zero */
|
1551 | 9a5c57fd | aurel32 | static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) |
1552 | 9a5c57fd | aurel32 | { |
1553 | 9a5c57fd | aurel32 | #ifdef TCG_TARGET_HAS_bswap32_i64
|
1554 | 9a5c57fd | aurel32 | tcg_gen_op2_i64(INDEX_op_bswap32_i64, ret, arg); |
1555 | 9a5c57fd | aurel32 | #else
|
1556 | 9a5c57fd | aurel32 | TCGv_i64 t0, t1; |
1557 | 9a5c57fd | aurel32 | t0 = tcg_temp_new_i64(); |
1558 | 9a5c57fd | aurel32 | t1 = tcg_temp_new_i64(); |
1559 | 9a5c57fd | aurel32 | |
1560 | 9a5c57fd | aurel32 | tcg_gen_shli_i64(t0, arg, 24);
|
1561 | 9a5c57fd | aurel32 | tcg_gen_ext32u_i64(t0, t0); |
1562 | 9a5c57fd | aurel32 | |
1563 | 9a5c57fd | aurel32 | tcg_gen_andi_i64(t1, arg, 0x0000ff00);
|
1564 | 9a5c57fd | aurel32 | tcg_gen_shli_i64(t1, t1, 8);
|
1565 | 9a5c57fd | aurel32 | tcg_gen_or_i64(t0, t0, t1); |
1566 | 9a5c57fd | aurel32 | |
1567 | 9a5c57fd | aurel32 | tcg_gen_shri_i64(t1, arg, 8);
|
1568 | 9a5c57fd | aurel32 | tcg_gen_andi_i64(t1, t1, 0x0000ff00);
|
1569 | 9a5c57fd | aurel32 | tcg_gen_or_i64(t0, t0, t1); |
1570 | 9a5c57fd | aurel32 | |
1571 | 9a5c57fd | aurel32 | tcg_gen_shri_i64(t1, arg, 24);
|
1572 | 9a5c57fd | aurel32 | tcg_gen_or_i64(ret, t0, t1); |
1573 | 9a5c57fd | aurel32 | tcg_temp_free_i64(t0); |
1574 | 9a5c57fd | aurel32 | tcg_temp_free_i64(t1); |
1575 | 9a5c57fd | aurel32 | #endif
|
1576 | 9a5c57fd | aurel32 | } |
1577 | 9a5c57fd | aurel32 | |
1578 | 66896cb8 | aurel32 | static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) |
1579 | c896fe29 | bellard | { |
1580 | 66896cb8 | aurel32 | #ifdef TCG_TARGET_HAS_bswap64_i64
|
1581 | 66896cb8 | aurel32 | tcg_gen_op2_i64(INDEX_op_bswap64_i64, ret, arg); |
1582 | c896fe29 | bellard | #else
|
1583 | b348113d | Stefan Weil | TCGv_i64 t0 = tcg_temp_new_i64(); |
1584 | b348113d | Stefan Weil | TCGv_i64 t1 = tcg_temp_new_i64(); |
1585 | c896fe29 | bellard | |
1586 | c896fe29 | bellard | tcg_gen_shli_i64(t0, arg, 56);
|
1587 | c896fe29 | bellard | |
1588 | c896fe29 | bellard | tcg_gen_andi_i64(t1, arg, 0x0000ff00);
|
1589 | c896fe29 | bellard | tcg_gen_shli_i64(t1, t1, 40);
|
1590 | c896fe29 | bellard | tcg_gen_or_i64(t0, t0, t1); |
1591 | c896fe29 | bellard | |
1592 | c896fe29 | bellard | tcg_gen_andi_i64(t1, arg, 0x00ff0000);
|
1593 | c896fe29 | bellard | tcg_gen_shli_i64(t1, t1, 24);
|
1594 | c896fe29 | bellard | tcg_gen_or_i64(t0, t0, t1); |
1595 | c896fe29 | bellard | |
1596 | c896fe29 | bellard | tcg_gen_andi_i64(t1, arg, 0xff000000);
|
1597 | c896fe29 | bellard | tcg_gen_shli_i64(t1, t1, 8);
|
1598 | c896fe29 | bellard | tcg_gen_or_i64(t0, t0, t1); |
1599 | c896fe29 | bellard | |
1600 | c896fe29 | bellard | tcg_gen_shri_i64(t1, arg, 8);
|
1601 | c896fe29 | bellard | tcg_gen_andi_i64(t1, t1, 0xff000000);
|
1602 | c896fe29 | bellard | tcg_gen_or_i64(t0, t0, t1); |
1603 | c896fe29 | bellard | |
1604 | c896fe29 | bellard | tcg_gen_shri_i64(t1, arg, 24);
|
1605 | c896fe29 | bellard | tcg_gen_andi_i64(t1, t1, 0x00ff0000);
|
1606 | c896fe29 | bellard | tcg_gen_or_i64(t0, t0, t1); |
1607 | c896fe29 | bellard | |
1608 | c896fe29 | bellard | tcg_gen_shri_i64(t1, arg, 40);
|
1609 | c896fe29 | bellard | tcg_gen_andi_i64(t1, t1, 0x0000ff00);
|
1610 | c896fe29 | bellard | tcg_gen_or_i64(t0, t0, t1); |
1611 | c896fe29 | bellard | |
1612 | c896fe29 | bellard | tcg_gen_shri_i64(t1, arg, 56);
|
1613 | c896fe29 | bellard | tcg_gen_or_i64(ret, t0, t1); |
1614 | b348113d | Stefan Weil | tcg_temp_free_i64(t0); |
1615 | b348113d | Stefan Weil | tcg_temp_free_i64(t1); |
1616 | c896fe29 | bellard | #endif
|
1617 | c896fe29 | bellard | } |
1618 | c896fe29 | bellard | |
1619 | c896fe29 | bellard | #endif
|
1620 | c896fe29 | bellard | |
1621 | a7812ae4 | pbrook | static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg) |
1622 | 390efc54 | pbrook | { |
1623 | 390efc54 | pbrook | #ifdef TCG_TARGET_HAS_neg_i32
|
1624 | a7812ae4 | pbrook | tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg); |
1625 | 390efc54 | pbrook | #else
|
1626 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_const_i32(0);
|
1627 | e8996ee0 | bellard | tcg_gen_sub_i32(ret, t0, arg); |
1628 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
1629 | 390efc54 | pbrook | #endif
|
1630 | 390efc54 | pbrook | } |
1631 | 390efc54 | pbrook | |
1632 | a7812ae4 | pbrook | static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg) |
1633 | 390efc54 | pbrook | { |
1634 | 390efc54 | pbrook | #ifdef TCG_TARGET_HAS_neg_i64
|
1635 | a7812ae4 | pbrook | tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg); |
1636 | 390efc54 | pbrook | #else
|
1637 | a7812ae4 | pbrook | TCGv_i64 t0 = tcg_const_i64(0);
|
1638 | e8996ee0 | bellard | tcg_gen_sub_i64(ret, t0, arg); |
1639 | a7812ae4 | pbrook | tcg_temp_free_i64(t0); |
1640 | 390efc54 | pbrook | #endif
|
1641 | 390efc54 | pbrook | } |
1642 | 390efc54 | pbrook | |
1643 | a7812ae4 | pbrook | static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) |
1644 | 0b6ce4cf | bellard | { |
1645 | d2604285 | aurel32 | #ifdef TCG_TARGET_HAS_not_i32
|
1646 | d2604285 | aurel32 | tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg); |
1647 | d2604285 | aurel32 | #else
|
1648 | e8996ee0 | bellard | tcg_gen_xori_i32(ret, arg, -1);
|
1649 | d2604285 | aurel32 | #endif
|
1650 | 0b6ce4cf | bellard | } |
1651 | 0b6ce4cf | bellard | |
1652 | a7812ae4 | pbrook | static inline void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg) |
1653 | 0b6ce4cf | bellard | { |
1654 | d2604285 | aurel32 | #ifdef TCG_TARGET_HAS_not_i64
|
1655 | 43e860ef | aurel32 | tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg); |
1656 | a10f9f4f | Richard Henderson | #elif defined(TCG_TARGET_HAS_not_i32) && TCG_TARGET_REG_BITS == 32 |
1657 | a10f9f4f | Richard Henderson | tcg_gen_not_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1658 | a10f9f4f | Richard Henderson | tcg_gen_not_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); |
1659 | d2604285 | aurel32 | #else
|
1660 | e8996ee0 | bellard | tcg_gen_xori_i64(ret, arg, -1);
|
1661 | d2604285 | aurel32 | #endif
|
1662 | 0b6ce4cf | bellard | } |
1663 | 5ff9d6a4 | bellard | |
1664 | a7812ae4 | pbrook | static inline void tcg_gen_discard_i32(TCGv_i32 arg) |
1665 | 5ff9d6a4 | bellard | { |
1666 | a7812ae4 | pbrook | tcg_gen_op1_i32(INDEX_op_discard, arg); |
1667 | 5ff9d6a4 | bellard | } |
1668 | 5ff9d6a4 | bellard | |
1669 | 5ff9d6a4 | bellard | #if TCG_TARGET_REG_BITS == 32 |
1670 | a7812ae4 | pbrook | static inline void tcg_gen_discard_i64(TCGv_i64 arg) |
1671 | 5ff9d6a4 | bellard | { |
1672 | a7812ae4 | pbrook | tcg_gen_discard_i32(TCGV_LOW(arg)); |
1673 | 5ff9d6a4 | bellard | tcg_gen_discard_i32(TCGV_HIGH(arg)); |
1674 | 5ff9d6a4 | bellard | } |
1675 | 5ff9d6a4 | bellard | #else
|
1676 | a7812ae4 | pbrook | static inline void tcg_gen_discard_i64(TCGv_i64 arg) |
1677 | 5ff9d6a4 | bellard | { |
1678 | a7812ae4 | pbrook | tcg_gen_op1_i64(INDEX_op_discard, arg); |
1679 | 5ff9d6a4 | bellard | } |
1680 | 5ff9d6a4 | bellard | #endif
|
1681 | 5ff9d6a4 | bellard | |
1682 | a7812ae4 | pbrook | static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high) |
1683 | 36aa55dc | pbrook | { |
1684 | 36aa55dc | pbrook | #if TCG_TARGET_REG_BITS == 32 |
1685 | a7812ae4 | pbrook | tcg_gen_mov_i32(TCGV_LOW(dest), low); |
1686 | 36aa55dc | pbrook | tcg_gen_mov_i32(TCGV_HIGH(dest), high); |
1687 | 36aa55dc | pbrook | #else
|
1688 | a7812ae4 | pbrook | TCGv_i64 tmp = tcg_temp_new_i64(); |
1689 | 36aa55dc | pbrook | /* This extension is only needed for type correctness.
|
1690 | 36aa55dc | pbrook | We may be able to do better given target specific information. */
|
1691 | 36aa55dc | pbrook | tcg_gen_extu_i32_i64(tmp, high); |
1692 | 36aa55dc | pbrook | tcg_gen_shli_i64(tmp, tmp, 32);
|
1693 | 36aa55dc | pbrook | tcg_gen_extu_i32_i64(dest, low); |
1694 | 36aa55dc | pbrook | tcg_gen_or_i64(dest, dest, tmp); |
1695 | a7812ae4 | pbrook | tcg_temp_free_i64(tmp); |
1696 | 36aa55dc | pbrook | #endif
|
1697 | 36aa55dc | pbrook | } |
1698 | 36aa55dc | pbrook | |
1699 | a7812ae4 | pbrook | static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, TCGv_i64 high) |
1700 | 945ca823 | blueswir1 | { |
1701 | 945ca823 | blueswir1 | #if TCG_TARGET_REG_BITS == 32 |
1702 | a7812ae4 | pbrook | tcg_gen_concat_i32_i64(dest, TCGV_LOW(low), TCGV_LOW(high)); |
1703 | 945ca823 | blueswir1 | #else
|
1704 | a7812ae4 | pbrook | TCGv_i64 tmp = tcg_temp_new_i64(); |
1705 | 88422e2e | pbrook | tcg_gen_ext32u_i64(dest, low); |
1706 | 945ca823 | blueswir1 | tcg_gen_shli_i64(tmp, high, 32);
|
1707 | 88422e2e | pbrook | tcg_gen_or_i64(dest, dest, tmp); |
1708 | a7812ae4 | pbrook | tcg_temp_free_i64(tmp); |
1709 | 945ca823 | blueswir1 | #endif
|
1710 | 945ca823 | blueswir1 | } |
1711 | 945ca823 | blueswir1 | |
1712 | a7812ae4 | pbrook | static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
1713 | f24cb33e | aurel32 | { |
1714 | 241cbed4 | Richard Henderson | #ifdef TCG_TARGET_HAS_andc_i32
|
1715 | 241cbed4 | Richard Henderson | tcg_gen_op3_i32(INDEX_op_andc_i32, ret, arg1, arg2); |
1716 | 241cbed4 | Richard Henderson | #else
|
1717 | a7812ae4 | pbrook | TCGv_i32 t0; |
1718 | a7812ae4 | pbrook | t0 = tcg_temp_new_i32(); |
1719 | f24cb33e | aurel32 | tcg_gen_not_i32(t0, arg2); |
1720 | f24cb33e | aurel32 | tcg_gen_and_i32(ret, arg1, t0); |
1721 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
1722 | 241cbed4 | Richard Henderson | #endif
|
1723 | f24cb33e | aurel32 | } |
1724 | f24cb33e | aurel32 | |
1725 | a7812ae4 | pbrook | static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1726 | f24cb33e | aurel32 | { |
1727 | 241cbed4 | Richard Henderson | #ifdef TCG_TARGET_HAS_andc_i64
|
1728 | 241cbed4 | Richard Henderson | tcg_gen_op3_i64(INDEX_op_andc_i64, ret, arg1, arg2); |
1729 | 241cbed4 | Richard Henderson | #elif defined(TCG_TARGET_HAS_andc_i32) && TCG_TARGET_REG_BITS == 32 |
1730 | 241cbed4 | Richard Henderson | tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
1731 | 241cbed4 | Richard Henderson | tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
1732 | 241cbed4 | Richard Henderson | #else
|
1733 | a7812ae4 | pbrook | TCGv_i64 t0; |
1734 | a7812ae4 | pbrook | t0 = tcg_temp_new_i64(); |
1735 | f24cb33e | aurel32 | tcg_gen_not_i64(t0, arg2); |
1736 | f24cb33e | aurel32 | tcg_gen_and_i64(ret, arg1, t0); |
1737 | a7812ae4 | pbrook | tcg_temp_free_i64(t0); |
1738 | 241cbed4 | Richard Henderson | #endif
|
1739 | f24cb33e | aurel32 | } |
1740 | f24cb33e | aurel32 | |
1741 | a7812ae4 | pbrook | static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
1742 | f24cb33e | aurel32 | { |
1743 | 8d625cf1 | Richard Henderson | #ifdef TCG_TARGET_HAS_eqv_i32
|
1744 | 8d625cf1 | Richard Henderson | tcg_gen_op3_i32(INDEX_op_eqv_i32, ret, arg1, arg2); |
1745 | 8d625cf1 | Richard Henderson | #else
|
1746 | 7fc81051 | aurel32 | tcg_gen_xor_i32(ret, arg1, arg2); |
1747 | 7fc81051 | aurel32 | tcg_gen_not_i32(ret, ret); |
1748 | 8d625cf1 | Richard Henderson | #endif
|
1749 | f24cb33e | aurel32 | } |
1750 | f24cb33e | aurel32 | |
1751 | a7812ae4 | pbrook | static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1752 | f24cb33e | aurel32 | { |
1753 | 8d625cf1 | Richard Henderson | #ifdef TCG_TARGET_HAS_eqv_i64
|
1754 | 8d625cf1 | Richard Henderson | tcg_gen_op3_i64(INDEX_op_eqv_i64, ret, arg1, arg2); |
1755 | 8d625cf1 | Richard Henderson | #elif defined(TCG_TARGET_HAS_eqv_i32) && TCG_TARGET_REG_BITS == 32 |
1756 | 8d625cf1 | Richard Henderson | tcg_gen_eqv_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
1757 | 8d625cf1 | Richard Henderson | tcg_gen_eqv_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
1758 | 8d625cf1 | Richard Henderson | #else
|
1759 | 7fc81051 | aurel32 | tcg_gen_xor_i64(ret, arg1, arg2); |
1760 | 7fc81051 | aurel32 | tcg_gen_not_i64(ret, ret); |
1761 | 8d625cf1 | Richard Henderson | #endif
|
1762 | f24cb33e | aurel32 | } |
1763 | f24cb33e | aurel32 | |
1764 | a7812ae4 | pbrook | static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
1765 | f24cb33e | aurel32 | { |
1766 | 7fc81051 | aurel32 | tcg_gen_and_i32(ret, arg1, arg2); |
1767 | 7fc81051 | aurel32 | tcg_gen_not_i32(ret, ret); |
1768 | f24cb33e | aurel32 | } |
1769 | f24cb33e | aurel32 | |
1770 | a7812ae4 | pbrook | static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1771 | f24cb33e | aurel32 | { |
1772 | 7fc81051 | aurel32 | tcg_gen_and_i64(ret, arg1, arg2); |
1773 | 7fc81051 | aurel32 | tcg_gen_not_i64(ret, ret); |
1774 | f24cb33e | aurel32 | } |
1775 | f24cb33e | aurel32 | |
1776 | a7812ae4 | pbrook | static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
1777 | f24cb33e | aurel32 | { |
1778 | 7fc81051 | aurel32 | tcg_gen_or_i32(ret, arg1, arg2); |
1779 | 7fc81051 | aurel32 | tcg_gen_not_i32(ret, ret); |
1780 | f24cb33e | aurel32 | } |
1781 | f24cb33e | aurel32 | |
1782 | a7812ae4 | pbrook | static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1783 | f24cb33e | aurel32 | { |
1784 | 7fc81051 | aurel32 | tcg_gen_or_i64(ret, arg1, arg2); |
1785 | 7fc81051 | aurel32 | tcg_gen_not_i64(ret, ret); |
1786 | f24cb33e | aurel32 | } |
1787 | f24cb33e | aurel32 | |
1788 | a7812ae4 | pbrook | static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
1789 | f24cb33e | aurel32 | { |
1790 | 791d1262 | Richard Henderson | #ifdef TCG_TARGET_HAS_orc_i32
|
1791 | 791d1262 | Richard Henderson | tcg_gen_op3_i32(INDEX_op_orc_i32, ret, arg1, arg2); |
1792 | 791d1262 | Richard Henderson | #else
|
1793 | a7812ae4 | pbrook | TCGv_i32 t0; |
1794 | a7812ae4 | pbrook | t0 = tcg_temp_new_i32(); |
1795 | f24cb33e | aurel32 | tcg_gen_not_i32(t0, arg2); |
1796 | f24cb33e | aurel32 | tcg_gen_or_i32(ret, arg1, t0); |
1797 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
1798 | 791d1262 | Richard Henderson | #endif
|
1799 | f24cb33e | aurel32 | } |
1800 | f24cb33e | aurel32 | |
1801 | a7812ae4 | pbrook | static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1802 | f24cb33e | aurel32 | { |
1803 | 791d1262 | Richard Henderson | #ifdef TCG_TARGET_HAS_orc_i64
|
1804 | 791d1262 | Richard Henderson | tcg_gen_op3_i64(INDEX_op_orc_i64, ret, arg1, arg2); |
1805 | 791d1262 | Richard Henderson | #elif defined(TCG_TARGET_HAS_orc_i32) && TCG_TARGET_REG_BITS == 32 |
1806 | 791d1262 | Richard Henderson | tcg_gen_orc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
1807 | 791d1262 | Richard Henderson | tcg_gen_orc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
1808 | 791d1262 | Richard Henderson | #else
|
1809 | a7812ae4 | pbrook | TCGv_i64 t0; |
1810 | a7812ae4 | pbrook | t0 = tcg_temp_new_i64(); |
1811 | f24cb33e | aurel32 | tcg_gen_not_i64(t0, arg2); |
1812 | f24cb33e | aurel32 | tcg_gen_or_i64(ret, arg1, t0); |
1813 | a7812ae4 | pbrook | tcg_temp_free_i64(t0); |
1814 | 791d1262 | Richard Henderson | #endif
|
1815 | f24cb33e | aurel32 | } |
1816 | f24cb33e | aurel32 | |
1817 | a7812ae4 | pbrook | static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
1818 | 15824571 | aurel32 | { |
1819 | d42f183c | aurel32 | #ifdef TCG_TARGET_HAS_rot_i32
|
1820 | d42f183c | aurel32 | tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, arg2); |
1821 | d42f183c | aurel32 | #else
|
1822 | a7812ae4 | pbrook | TCGv_i32 t0, t1; |
1823 | 15824571 | aurel32 | |
1824 | a7812ae4 | pbrook | t0 = tcg_temp_new_i32(); |
1825 | a7812ae4 | pbrook | t1 = tcg_temp_new_i32(); |
1826 | 15824571 | aurel32 | tcg_gen_shl_i32(t0, arg1, arg2); |
1827 | 15824571 | aurel32 | tcg_gen_subfi_i32(t1, 32, arg2);
|
1828 | 15824571 | aurel32 | tcg_gen_shr_i32(t1, arg1, t1); |
1829 | 15824571 | aurel32 | tcg_gen_or_i32(ret, t0, t1); |
1830 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
1831 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); |
1832 | d42f183c | aurel32 | #endif
|
1833 | 15824571 | aurel32 | } |
1834 | 15824571 | aurel32 | |
1835 | a7812ae4 | pbrook | static inline void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1836 | 15824571 | aurel32 | { |
1837 | d42f183c | aurel32 | #ifdef TCG_TARGET_HAS_rot_i64
|
1838 | d42f183c | aurel32 | tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, arg2); |
1839 | d42f183c | aurel32 | #else
|
1840 | a7812ae4 | pbrook | TCGv_i64 t0, t1; |
1841 | 15824571 | aurel32 | |
1842 | a7812ae4 | pbrook | t0 = tcg_temp_new_i64(); |
1843 | a7812ae4 | pbrook | t1 = tcg_temp_new_i64(); |
1844 | 15824571 | aurel32 | tcg_gen_shl_i64(t0, arg1, arg2); |
1845 | 15824571 | aurel32 | tcg_gen_subfi_i64(t1, 64, arg2);
|
1846 | 15824571 | aurel32 | tcg_gen_shr_i64(t1, arg1, t1); |
1847 | 15824571 | aurel32 | tcg_gen_or_i64(ret, t0, t1); |
1848 | a7812ae4 | pbrook | tcg_temp_free_i64(t0); |
1849 | a7812ae4 | pbrook | tcg_temp_free_i64(t1); |
1850 | d42f183c | aurel32 | #endif
|
1851 | 15824571 | aurel32 | } |
1852 | 15824571 | aurel32 | |
1853 | a7812ae4 | pbrook | static inline void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
1854 | 15824571 | aurel32 | { |
1855 | 15824571 | aurel32 | /* some cases can be optimized here */
|
1856 | 15824571 | aurel32 | if (arg2 == 0) { |
1857 | 15824571 | aurel32 | tcg_gen_mov_i32(ret, arg1); |
1858 | 15824571 | aurel32 | } else {
|
1859 | d42f183c | aurel32 | #ifdef TCG_TARGET_HAS_rot_i32
|
1860 | d42f183c | aurel32 | TCGv_i32 t0 = tcg_const_i32(arg2); |
1861 | d42f183c | aurel32 | tcg_gen_rotl_i32(ret, arg1, t0); |
1862 | d42f183c | aurel32 | tcg_temp_free_i32(t0); |
1863 | d42f183c | aurel32 | #else
|
1864 | a7812ae4 | pbrook | TCGv_i32 t0, t1; |
1865 | a7812ae4 | pbrook | t0 = tcg_temp_new_i32(); |
1866 | a7812ae4 | pbrook | t1 = tcg_temp_new_i32(); |
1867 | 15824571 | aurel32 | tcg_gen_shli_i32(t0, arg1, arg2); |
1868 | 15824571 | aurel32 | tcg_gen_shri_i32(t1, arg1, 32 - arg2);
|
1869 | 15824571 | aurel32 | tcg_gen_or_i32(ret, t0, t1); |
1870 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
1871 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); |
1872 | d42f183c | aurel32 | #endif
|
1873 | 15824571 | aurel32 | } |
1874 | 15824571 | aurel32 | } |
1875 | 15824571 | aurel32 | |
1876 | a7812ae4 | pbrook | static inline void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1877 | 15824571 | aurel32 | { |
1878 | 15824571 | aurel32 | /* some cases can be optimized here */
|
1879 | 15824571 | aurel32 | if (arg2 == 0) { |
1880 | 15824571 | aurel32 | tcg_gen_mov_i64(ret, arg1); |
1881 | 15824571 | aurel32 | } else {
|
1882 | d42f183c | aurel32 | #ifdef TCG_TARGET_HAS_rot_i64
|
1883 | d42f183c | aurel32 | TCGv_i64 t0 = tcg_const_i64(arg2); |
1884 | d42f183c | aurel32 | tcg_gen_rotl_i64(ret, arg1, t0); |
1885 | d42f183c | aurel32 | tcg_temp_free_i64(t0); |
1886 | d42f183c | aurel32 | #else
|
1887 | a7812ae4 | pbrook | TCGv_i64 t0, t1; |
1888 | a7812ae4 | pbrook | t0 = tcg_temp_new_i64(); |
1889 | a7812ae4 | pbrook | t1 = tcg_temp_new_i64(); |
1890 | 15824571 | aurel32 | tcg_gen_shli_i64(t0, arg1, arg2); |
1891 | 15824571 | aurel32 | tcg_gen_shri_i64(t1, arg1, 64 - arg2);
|
1892 | 15824571 | aurel32 | tcg_gen_or_i64(ret, t0, t1); |
1893 | a7812ae4 | pbrook | tcg_temp_free_i64(t0); |
1894 | a7812ae4 | pbrook | tcg_temp_free_i64(t1); |
1895 | d42f183c | aurel32 | #endif
|
1896 | 15824571 | aurel32 | } |
1897 | 15824571 | aurel32 | } |
1898 | 15824571 | aurel32 | |
1899 | a7812ae4 | pbrook | static inline void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
1900 | 15824571 | aurel32 | { |
1901 | d42f183c | aurel32 | #ifdef TCG_TARGET_HAS_rot_i32
|
1902 | d42f183c | aurel32 | tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, arg2); |
1903 | d42f183c | aurel32 | #else
|
1904 | a7812ae4 | pbrook | TCGv_i32 t0, t1; |
1905 | 15824571 | aurel32 | |
1906 | a7812ae4 | pbrook | t0 = tcg_temp_new_i32(); |
1907 | a7812ae4 | pbrook | t1 = tcg_temp_new_i32(); |
1908 | 15824571 | aurel32 | tcg_gen_shr_i32(t0, arg1, arg2); |
1909 | 15824571 | aurel32 | tcg_gen_subfi_i32(t1, 32, arg2);
|
1910 | 15824571 | aurel32 | tcg_gen_shl_i32(t1, arg1, t1); |
1911 | 15824571 | aurel32 | tcg_gen_or_i32(ret, t0, t1); |
1912 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
1913 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); |
1914 | d42f183c | aurel32 | #endif
|
1915 | 15824571 | aurel32 | } |
1916 | 15824571 | aurel32 | |
1917 | a7812ae4 | pbrook | static inline void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1918 | 15824571 | aurel32 | { |
1919 | d42f183c | aurel32 | #ifdef TCG_TARGET_HAS_rot_i64
|
1920 | d42f183c | aurel32 | tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, arg2); |
1921 | d42f183c | aurel32 | #else
|
1922 | a7812ae4 | pbrook | TCGv_i64 t0, t1; |
1923 | 15824571 | aurel32 | |
1924 | a7812ae4 | pbrook | t0 = tcg_temp_new_i64(); |
1925 | a7812ae4 | pbrook | t1 = tcg_temp_new_i64(); |
1926 | d9885a0b | Aurelien Jarno | tcg_gen_shr_i64(t0, arg1, arg2); |
1927 | 15824571 | aurel32 | tcg_gen_subfi_i64(t1, 64, arg2);
|
1928 | 15824571 | aurel32 | tcg_gen_shl_i64(t1, arg1, t1); |
1929 | 15824571 | aurel32 | tcg_gen_or_i64(ret, t0, t1); |
1930 | a7812ae4 | pbrook | tcg_temp_free_i64(t0); |
1931 | a7812ae4 | pbrook | tcg_temp_free_i64(t1); |
1932 | d42f183c | aurel32 | #endif
|
1933 | 15824571 | aurel32 | } |
1934 | 15824571 | aurel32 | |
1935 | a7812ae4 | pbrook | static inline void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
1936 | 15824571 | aurel32 | { |
1937 | 15824571 | aurel32 | /* some cases can be optimized here */
|
1938 | 15824571 | aurel32 | if (arg2 == 0) { |
1939 | 15824571 | aurel32 | tcg_gen_mov_i32(ret, arg1); |
1940 | 15824571 | aurel32 | } else {
|
1941 | 15824571 | aurel32 | tcg_gen_rotli_i32(ret, arg1, 32 - arg2);
|
1942 | 15824571 | aurel32 | } |
1943 | 15824571 | aurel32 | } |
1944 | 15824571 | aurel32 | |
1945 | a7812ae4 | pbrook | static inline void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1946 | 15824571 | aurel32 | { |
1947 | 15824571 | aurel32 | /* some cases can be optimized here */
|
1948 | 15824571 | aurel32 | if (arg2 == 0) { |
1949 | de3526b2 | pbrook | tcg_gen_mov_i64(ret, arg1); |
1950 | 15824571 | aurel32 | } else {
|
1951 | 15824571 | aurel32 | tcg_gen_rotli_i64(ret, arg1, 64 - arg2);
|
1952 | 15824571 | aurel32 | } |
1953 | 15824571 | aurel32 | } |
1954 | 15824571 | aurel32 | |
1955 | c896fe29 | bellard | /***************************************/
|
1956 | c896fe29 | bellard | /* QEMU specific operations. Their type depend on the QEMU CPU
|
1957 | c896fe29 | bellard | type. */
|
1958 | c896fe29 | bellard | #ifndef TARGET_LONG_BITS
|
1959 | c896fe29 | bellard | #error must include QEMU headers
|
1960 | c896fe29 | bellard | #endif
|
1961 | c896fe29 | bellard | |
1962 | a7812ae4 | pbrook | #if TARGET_LONG_BITS == 32 |
1963 | a7812ae4 | pbrook | #define TCGv TCGv_i32
|
1964 | a7812ae4 | pbrook | #define tcg_temp_new() tcg_temp_new_i32()
|
1965 | a7812ae4 | pbrook | #define tcg_global_reg_new tcg_global_reg_new_i32
|
1966 | a7812ae4 | pbrook | #define tcg_global_mem_new tcg_global_mem_new_i32
|
1967 | df9247b2 | aurel32 | #define tcg_temp_local_new() tcg_temp_local_new_i32()
|
1968 | a7812ae4 | pbrook | #define tcg_temp_free tcg_temp_free_i32
|
1969 | a7812ae4 | pbrook | #define tcg_gen_qemu_ldst_op tcg_gen_op3i_i32
|
1970 | a7812ae4 | pbrook | #define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i32
|
1971 | a7812ae4 | pbrook | #define TCGV_UNUSED(x) TCGV_UNUSED_I32(x)
|
1972 | fe75bcf7 | aurel32 | #define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b)
|
1973 | a7812ae4 | pbrook | #else
|
1974 | a7812ae4 | pbrook | #define TCGv TCGv_i64
|
1975 | a7812ae4 | pbrook | #define tcg_temp_new() tcg_temp_new_i64()
|
1976 | a7812ae4 | pbrook | #define tcg_global_reg_new tcg_global_reg_new_i64
|
1977 | a7812ae4 | pbrook | #define tcg_global_mem_new tcg_global_mem_new_i64
|
1978 | df9247b2 | aurel32 | #define tcg_temp_local_new() tcg_temp_local_new_i64()
|
1979 | a7812ae4 | pbrook | #define tcg_temp_free tcg_temp_free_i64
|
1980 | a7812ae4 | pbrook | #define tcg_gen_qemu_ldst_op tcg_gen_op3i_i64
|
1981 | a7812ae4 | pbrook | #define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i64
|
1982 | a7812ae4 | pbrook | #define TCGV_UNUSED(x) TCGV_UNUSED_I64(x)
|
1983 | fe75bcf7 | aurel32 | #define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b)
|
1984 | a7812ae4 | pbrook | #endif
|
1985 | a7812ae4 | pbrook | |
1986 | 7e4597d7 | bellard | /* debug info: write the PC of the corresponding QEMU CPU instruction */
|
1987 | 7e4597d7 | bellard | static inline void tcg_gen_debug_insn_start(uint64_t pc) |
1988 | 7e4597d7 | bellard | { |
1989 | 7e4597d7 | bellard | /* XXX: must really use a 32 bit size for TCGArg in all cases */
|
1990 | 7e4597d7 | bellard | #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
|
1991 | bcb0126f | pbrook | tcg_gen_op2ii(INDEX_op_debug_insn_start, |
1992 | bcb0126f | pbrook | (uint32_t)(pc), (uint32_t)(pc >> 32));
|
1993 | 7e4597d7 | bellard | #else
|
1994 | 7e4597d7 | bellard | tcg_gen_op1i(INDEX_op_debug_insn_start, pc); |
1995 | 7e4597d7 | bellard | #endif
|
1996 | 7e4597d7 | bellard | } |
1997 | 7e4597d7 | bellard | |
1998 | c896fe29 | bellard | static inline void tcg_gen_exit_tb(tcg_target_long val) |
1999 | c896fe29 | bellard | { |
2000 | ac56dd48 | pbrook | tcg_gen_op1i(INDEX_op_exit_tb, val); |
2001 | c896fe29 | bellard | } |
2002 | c896fe29 | bellard | |
2003 | c896fe29 | bellard | static inline void tcg_gen_goto_tb(int idx) |
2004 | c896fe29 | bellard | { |
2005 | ac56dd48 | pbrook | tcg_gen_op1i(INDEX_op_goto_tb, idx); |
2006 | c896fe29 | bellard | } |
2007 | c896fe29 | bellard | |
2008 | c896fe29 | bellard | #if TCG_TARGET_REG_BITS == 32 |
2009 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
2010 | c896fe29 | bellard | { |
2011 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
2012 | a7812ae4 | pbrook | tcg_gen_op3i_i32(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
2013 | c896fe29 | bellard | #else
|
2014 | a7812ae4 | pbrook | tcg_gen_op4i_i32(INDEX_op_qemu_ld8u, TCGV_LOW(ret), TCGV_LOW(addr), |
2015 | a7812ae4 | pbrook | TCGV_HIGH(addr), mem_index); |
2016 | ac56dd48 | pbrook | tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
2017 | c896fe29 | bellard | #endif
|
2018 | c896fe29 | bellard | } |
2019 | c896fe29 | bellard | |
2020 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
2021 | c896fe29 | bellard | { |
2022 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
2023 | a7812ae4 | pbrook | tcg_gen_op3i_i32(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
2024 | c896fe29 | bellard | #else
|
2025 | a7812ae4 | pbrook | tcg_gen_op4i_i32(INDEX_op_qemu_ld8s, TCGV_LOW(ret), TCGV_LOW(addr), |
2026 | a7812ae4 | pbrook | TCGV_HIGH(addr), mem_index); |
2027 | a7812ae4 | pbrook | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
2028 | c896fe29 | bellard | #endif
|
2029 | c896fe29 | bellard | } |
2030 | c896fe29 | bellard | |
2031 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
2032 | c896fe29 | bellard | { |
2033 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
2034 | a7812ae4 | pbrook | tcg_gen_op3i_i32(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
2035 | c896fe29 | bellard | #else
|
2036 | a7812ae4 | pbrook | tcg_gen_op4i_i32(INDEX_op_qemu_ld16u, TCGV_LOW(ret), TCGV_LOW(addr), |
2037 | a7812ae4 | pbrook | TCGV_HIGH(addr), mem_index); |
2038 | ac56dd48 | pbrook | tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
2039 | c896fe29 | bellard | #endif
|
2040 | c896fe29 | bellard | } |
2041 | c896fe29 | bellard | |
2042 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
2043 | c896fe29 | bellard | { |
2044 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
2045 | a7812ae4 | pbrook | tcg_gen_op3i_i32(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
2046 | c896fe29 | bellard | #else
|
2047 | a7812ae4 | pbrook | tcg_gen_op4i_i32(INDEX_op_qemu_ld16s, TCGV_LOW(ret), TCGV_LOW(addr), |
2048 | a7812ae4 | pbrook | TCGV_HIGH(addr), mem_index); |
2049 | a7812ae4 | pbrook | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
2050 | c896fe29 | bellard | #endif
|
2051 | c896fe29 | bellard | } |
2052 | c896fe29 | bellard | |
2053 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
2054 | c896fe29 | bellard | { |
2055 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
2056 | a7812ae4 | pbrook | tcg_gen_op3i_i32(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
2057 | c896fe29 | bellard | #else
|
2058 | a7812ae4 | pbrook | tcg_gen_op4i_i32(INDEX_op_qemu_ld32u, TCGV_LOW(ret), TCGV_LOW(addr), |
2059 | a7812ae4 | pbrook | TCGV_HIGH(addr), mem_index); |
2060 | ac56dd48 | pbrook | tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
2061 | c896fe29 | bellard | #endif
|
2062 | c896fe29 | bellard | } |
2063 | c896fe29 | bellard | |
2064 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
2065 | c896fe29 | bellard | { |
2066 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
2067 | a7812ae4 | pbrook | tcg_gen_op3i_i32(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
2068 | c896fe29 | bellard | #else
|
2069 | a7812ae4 | pbrook | tcg_gen_op4i_i32(INDEX_op_qemu_ld32u, TCGV_LOW(ret), TCGV_LOW(addr), |
2070 | a7812ae4 | pbrook | TCGV_HIGH(addr), mem_index); |
2071 | a7812ae4 | pbrook | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
2072 | c896fe29 | bellard | #endif
|
2073 | c896fe29 | bellard | } |
2074 | c896fe29 | bellard | |
2075 | a7812ae4 | pbrook | static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index) |
2076 | c896fe29 | bellard | { |
2077 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
2078 | a7812ae4 | pbrook | tcg_gen_op4i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), addr, mem_index); |
2079 | c896fe29 | bellard | #else
|
2080 | a7812ae4 | pbrook | tcg_gen_op5i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), |
2081 | a7812ae4 | pbrook | TCGV_LOW(addr), TCGV_HIGH(addr), mem_index); |
2082 | c896fe29 | bellard | #endif
|
2083 | c896fe29 | bellard | } |
2084 | c896fe29 | bellard | |
2085 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
2086 | c896fe29 | bellard | { |
2087 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
2088 | a7812ae4 | pbrook | tcg_gen_op3i_i32(INDEX_op_qemu_st8, arg, addr, mem_index); |
2089 | c896fe29 | bellard | #else
|
2090 | a7812ae4 | pbrook | tcg_gen_op4i_i32(INDEX_op_qemu_st8, TCGV_LOW(arg), TCGV_LOW(addr), |
2091 | a7812ae4 | pbrook | TCGV_HIGH(addr), mem_index); |
2092 | c896fe29 | bellard | #endif
|
2093 | c896fe29 | bellard | } |
2094 | c896fe29 | bellard | |
2095 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
2096 | c896fe29 | bellard | { |
2097 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
2098 | a7812ae4 | pbrook | tcg_gen_op3i_i32(INDEX_op_qemu_st16, arg, addr, mem_index); |
2099 | c896fe29 | bellard | #else
|
2100 | a7812ae4 | pbrook | tcg_gen_op4i_i32(INDEX_op_qemu_st16, TCGV_LOW(arg), TCGV_LOW(addr), |
2101 | a7812ae4 | pbrook | TCGV_HIGH(addr), mem_index); |
2102 | c896fe29 | bellard | #endif
|
2103 | c896fe29 | bellard | } |
2104 | c896fe29 | bellard | |
2105 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
2106 | c896fe29 | bellard | { |
2107 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
2108 | a7812ae4 | pbrook | tcg_gen_op3i_i32(INDEX_op_qemu_st32, arg, addr, mem_index); |
2109 | c896fe29 | bellard | #else
|
2110 | a7812ae4 | pbrook | tcg_gen_op4i_i32(INDEX_op_qemu_st32, TCGV_LOW(arg), TCGV_LOW(addr), |
2111 | a7812ae4 | pbrook | TCGV_HIGH(addr), mem_index); |
2112 | c896fe29 | bellard | #endif
|
2113 | c896fe29 | bellard | } |
2114 | c896fe29 | bellard | |
2115 | a7812ae4 | pbrook | static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index) |
2116 | c896fe29 | bellard | { |
2117 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
2118 | a7812ae4 | pbrook | tcg_gen_op4i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), addr, |
2119 | a7812ae4 | pbrook | mem_index); |
2120 | c896fe29 | bellard | #else
|
2121 | a7812ae4 | pbrook | tcg_gen_op5i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), |
2122 | a7812ae4 | pbrook | TCGV_LOW(addr), TCGV_HIGH(addr), mem_index); |
2123 | c896fe29 | bellard | #endif
|
2124 | c896fe29 | bellard | } |
2125 | c896fe29 | bellard | |
2126 | 56b8f567 | blueswir1 | #define tcg_gen_ld_ptr tcg_gen_ld_i32
|
2127 | a768e4b2 | blueswir1 | #define tcg_gen_discard_ptr tcg_gen_discard_i32
|
2128 | f8422f52 | blueswir1 | |
2129 | c896fe29 | bellard | #else /* TCG_TARGET_REG_BITS == 32 */ |
2130 | c896fe29 | bellard | |
2131 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
2132 | c896fe29 | bellard | { |
2133 | a7812ae4 | pbrook | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
2134 | c896fe29 | bellard | } |
2135 | c896fe29 | bellard | |
2136 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
2137 | c896fe29 | bellard | { |
2138 | a7812ae4 | pbrook | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
2139 | c896fe29 | bellard | } |
2140 | c896fe29 | bellard | |
2141 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
2142 | c896fe29 | bellard | { |
2143 | a7812ae4 | pbrook | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
2144 | c896fe29 | bellard | } |
2145 | c896fe29 | bellard | |
2146 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
2147 | c896fe29 | bellard | { |
2148 | a7812ae4 | pbrook | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
2149 | c896fe29 | bellard | } |
2150 | c896fe29 | bellard | |
2151 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
2152 | c896fe29 | bellard | { |
2153 | a7812ae4 | pbrook | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
2154 | c896fe29 | bellard | } |
2155 | c896fe29 | bellard | |
2156 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
2157 | c896fe29 | bellard | { |
2158 | a7812ae4 | pbrook | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32s, ret, addr, mem_index); |
2159 | c896fe29 | bellard | } |
2160 | c896fe29 | bellard | |
2161 | a7812ae4 | pbrook | static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index) |
2162 | c896fe29 | bellard | { |
2163 | a7812ae4 | pbrook | tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_ld64, ret, addr, mem_index); |
2164 | c896fe29 | bellard | } |
2165 | c896fe29 | bellard | |
2166 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
2167 | c896fe29 | bellard | { |
2168 | a7812ae4 | pbrook | tcg_gen_qemu_ldst_op(INDEX_op_qemu_st8, arg, addr, mem_index); |
2169 | c896fe29 | bellard | } |
2170 | c896fe29 | bellard | |
2171 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
2172 | c896fe29 | bellard | { |
2173 | a7812ae4 | pbrook | tcg_gen_qemu_ldst_op(INDEX_op_qemu_st16, arg, addr, mem_index); |
2174 | c896fe29 | bellard | } |
2175 | c896fe29 | bellard | |
2176 | ac56dd48 | pbrook | static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
2177 | c896fe29 | bellard | { |
2178 | a7812ae4 | pbrook | tcg_gen_qemu_ldst_op(INDEX_op_qemu_st32, arg, addr, mem_index); |
2179 | c896fe29 | bellard | } |
2180 | c896fe29 | bellard | |
2181 | a7812ae4 | pbrook | static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index) |
2182 | c896fe29 | bellard | { |
2183 | a7812ae4 | pbrook | tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_st64, arg, addr, mem_index); |
2184 | c896fe29 | bellard | } |
2185 | c896fe29 | bellard | |
2186 | 56b8f567 | blueswir1 | #define tcg_gen_ld_ptr tcg_gen_ld_i64
|
2187 | a768e4b2 | blueswir1 | #define tcg_gen_discard_ptr tcg_gen_discard_i64
|
2188 | f8422f52 | blueswir1 | |
2189 | c896fe29 | bellard | #endif /* TCG_TARGET_REG_BITS != 32 */ |
2190 | f8422f52 | blueswir1 | |
2191 | f8422f52 | blueswir1 | #if TARGET_LONG_BITS == 64 |
2192 | f8422f52 | blueswir1 | #define tcg_gen_movi_tl tcg_gen_movi_i64
|
2193 | f8422f52 | blueswir1 | #define tcg_gen_mov_tl tcg_gen_mov_i64
|
2194 | f8422f52 | blueswir1 | #define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
|
2195 | f8422f52 | blueswir1 | #define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
|
2196 | f8422f52 | blueswir1 | #define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
|
2197 | f8422f52 | blueswir1 | #define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
|
2198 | f8422f52 | blueswir1 | #define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
|
2199 | f8422f52 | blueswir1 | #define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
|
2200 | f8422f52 | blueswir1 | #define tcg_gen_ld_tl tcg_gen_ld_i64
|
2201 | f8422f52 | blueswir1 | #define tcg_gen_st8_tl tcg_gen_st8_i64
|
2202 | f8422f52 | blueswir1 | #define tcg_gen_st16_tl tcg_gen_st16_i64
|
2203 | f8422f52 | blueswir1 | #define tcg_gen_st32_tl tcg_gen_st32_i64
|
2204 | f8422f52 | blueswir1 | #define tcg_gen_st_tl tcg_gen_st_i64
|
2205 | f8422f52 | blueswir1 | #define tcg_gen_add_tl tcg_gen_add_i64
|
2206 | f8422f52 | blueswir1 | #define tcg_gen_addi_tl tcg_gen_addi_i64
|
2207 | f8422f52 | blueswir1 | #define tcg_gen_sub_tl tcg_gen_sub_i64
|
2208 | 390efc54 | pbrook | #define tcg_gen_neg_tl tcg_gen_neg_i64
|
2209 | 10460c8a | pbrook | #define tcg_gen_subfi_tl tcg_gen_subfi_i64
|
2210 | f8422f52 | blueswir1 | #define tcg_gen_subi_tl tcg_gen_subi_i64
|
2211 | f8422f52 | blueswir1 | #define tcg_gen_and_tl tcg_gen_and_i64
|
2212 | f8422f52 | blueswir1 | #define tcg_gen_andi_tl tcg_gen_andi_i64
|
2213 | f8422f52 | blueswir1 | #define tcg_gen_or_tl tcg_gen_or_i64
|
2214 | f8422f52 | blueswir1 | #define tcg_gen_ori_tl tcg_gen_ori_i64
|
2215 | f8422f52 | blueswir1 | #define tcg_gen_xor_tl tcg_gen_xor_i64
|
2216 | f8422f52 | blueswir1 | #define tcg_gen_xori_tl tcg_gen_xori_i64
|
2217 | 0b6ce4cf | bellard | #define tcg_gen_not_tl tcg_gen_not_i64
|
2218 | f8422f52 | blueswir1 | #define tcg_gen_shl_tl tcg_gen_shl_i64
|
2219 | f8422f52 | blueswir1 | #define tcg_gen_shli_tl tcg_gen_shli_i64
|
2220 | f8422f52 | blueswir1 | #define tcg_gen_shr_tl tcg_gen_shr_i64
|
2221 | f8422f52 | blueswir1 | #define tcg_gen_shri_tl tcg_gen_shri_i64
|
2222 | f8422f52 | blueswir1 | #define tcg_gen_sar_tl tcg_gen_sar_i64
|
2223 | f8422f52 | blueswir1 | #define tcg_gen_sari_tl tcg_gen_sari_i64
|
2224 | 0cf767d6 | blueswir1 | #define tcg_gen_brcond_tl tcg_gen_brcond_i64
|
2225 | cb63669a | pbrook | #define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
|
2226 | be210acb | Richard Henderson | #define tcg_gen_setcond_tl tcg_gen_setcond_i64
|
2227 | add1e7ea | Aurelien Jarno | #define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
|
2228 | f730fd27 | ths | #define tcg_gen_mul_tl tcg_gen_mul_i64
|
2229 | f730fd27 | ths | #define tcg_gen_muli_tl tcg_gen_muli_i64
|
2230 | ab36421e | aurel32 | #define tcg_gen_div_tl tcg_gen_div_i64
|
2231 | ab36421e | aurel32 | #define tcg_gen_rem_tl tcg_gen_rem_i64
|
2232 | 864951af | aurel32 | #define tcg_gen_divu_tl tcg_gen_divu_i64
|
2233 | 864951af | aurel32 | #define tcg_gen_remu_tl tcg_gen_remu_i64
|
2234 | a768e4b2 | blueswir1 | #define tcg_gen_discard_tl tcg_gen_discard_i64
|
2235 | e429073d | blueswir1 | #define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32
|
2236 | e429073d | blueswir1 | #define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
|
2237 | e429073d | blueswir1 | #define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
|
2238 | e429073d | blueswir1 | #define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
|
2239 | e429073d | blueswir1 | #define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
|
2240 | e429073d | blueswir1 | #define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
|
2241 | 0b6ce4cf | bellard | #define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
|
2242 | 0b6ce4cf | bellard | #define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
|
2243 | 0b6ce4cf | bellard | #define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
|
2244 | 0b6ce4cf | bellard | #define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
|
2245 | 0b6ce4cf | bellard | #define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
|
2246 | 0b6ce4cf | bellard | #define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
|
2247 | 911d79ba | aurel32 | #define tcg_gen_bswap16_tl tcg_gen_bswap16_i64
|
2248 | 911d79ba | aurel32 | #define tcg_gen_bswap32_tl tcg_gen_bswap32_i64
|
2249 | 911d79ba | aurel32 | #define tcg_gen_bswap64_tl tcg_gen_bswap64_i64
|
2250 | 945ca823 | blueswir1 | #define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
|
2251 | f24cb33e | aurel32 | #define tcg_gen_andc_tl tcg_gen_andc_i64
|
2252 | f24cb33e | aurel32 | #define tcg_gen_eqv_tl tcg_gen_eqv_i64
|
2253 | f24cb33e | aurel32 | #define tcg_gen_nand_tl tcg_gen_nand_i64
|
2254 | f24cb33e | aurel32 | #define tcg_gen_nor_tl tcg_gen_nor_i64
|
2255 | f24cb33e | aurel32 | #define tcg_gen_orc_tl tcg_gen_orc_i64
|
2256 | 15824571 | aurel32 | #define tcg_gen_rotl_tl tcg_gen_rotl_i64
|
2257 | 15824571 | aurel32 | #define tcg_gen_rotli_tl tcg_gen_rotli_i64
|
2258 | 15824571 | aurel32 | #define tcg_gen_rotr_tl tcg_gen_rotr_i64
|
2259 | 15824571 | aurel32 | #define tcg_gen_rotri_tl tcg_gen_rotri_i64
|
2260 | a98824ac | blueswir1 | #define tcg_const_tl tcg_const_i64
|
2261 | bdffd4a9 | aurel32 | #define tcg_const_local_tl tcg_const_local_i64
|
2262 | f8422f52 | blueswir1 | #else
|
2263 | f8422f52 | blueswir1 | #define tcg_gen_movi_tl tcg_gen_movi_i32
|
2264 | f8422f52 | blueswir1 | #define tcg_gen_mov_tl tcg_gen_mov_i32
|
2265 | f8422f52 | blueswir1 | #define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
|
2266 | f8422f52 | blueswir1 | #define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
|
2267 | f8422f52 | blueswir1 | #define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
|
2268 | f8422f52 | blueswir1 | #define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
|
2269 | f8422f52 | blueswir1 | #define tcg_gen_ld32u_tl tcg_gen_ld_i32
|
2270 | f8422f52 | blueswir1 | #define tcg_gen_ld32s_tl tcg_gen_ld_i32
|
2271 | f8422f52 | blueswir1 | #define tcg_gen_ld_tl tcg_gen_ld_i32
|
2272 | f8422f52 | blueswir1 | #define tcg_gen_st8_tl tcg_gen_st8_i32
|
2273 | f8422f52 | blueswir1 | #define tcg_gen_st16_tl tcg_gen_st16_i32
|
2274 | f8422f52 | blueswir1 | #define tcg_gen_st32_tl tcg_gen_st_i32
|
2275 | f8422f52 | blueswir1 | #define tcg_gen_st_tl tcg_gen_st_i32
|
2276 | f8422f52 | blueswir1 | #define tcg_gen_add_tl tcg_gen_add_i32
|
2277 | f8422f52 | blueswir1 | #define tcg_gen_addi_tl tcg_gen_addi_i32
|
2278 | f8422f52 | blueswir1 | #define tcg_gen_sub_tl tcg_gen_sub_i32
|
2279 | 390efc54 | pbrook | #define tcg_gen_neg_tl tcg_gen_neg_i32
|
2280 | 0045734a | aurel32 | #define tcg_gen_subfi_tl tcg_gen_subfi_i32
|
2281 | f8422f52 | blueswir1 | #define tcg_gen_subi_tl tcg_gen_subi_i32
|
2282 | f8422f52 | blueswir1 | #define tcg_gen_and_tl tcg_gen_and_i32
|
2283 | f8422f52 | blueswir1 | #define tcg_gen_andi_tl tcg_gen_andi_i32
|
2284 | f8422f52 | blueswir1 | #define tcg_gen_or_tl tcg_gen_or_i32
|
2285 | f8422f52 | blueswir1 | #define tcg_gen_ori_tl tcg_gen_ori_i32
|
2286 | f8422f52 | blueswir1 | #define tcg_gen_xor_tl tcg_gen_xor_i32
|
2287 | f8422f52 | blueswir1 | #define tcg_gen_xori_tl tcg_gen_xori_i32
|
2288 | 0b6ce4cf | bellard | #define tcg_gen_not_tl tcg_gen_not_i32
|
2289 | f8422f52 | blueswir1 | #define tcg_gen_shl_tl tcg_gen_shl_i32
|
2290 | f8422f52 | blueswir1 | #define tcg_gen_shli_tl tcg_gen_shli_i32
|
2291 | f8422f52 | blueswir1 | #define tcg_gen_shr_tl tcg_gen_shr_i32
|
2292 | f8422f52 | blueswir1 | #define tcg_gen_shri_tl tcg_gen_shri_i32
|
2293 | f8422f52 | blueswir1 | #define tcg_gen_sar_tl tcg_gen_sar_i32
|
2294 | f8422f52 | blueswir1 | #define tcg_gen_sari_tl tcg_gen_sari_i32
|
2295 | 0cf767d6 | blueswir1 | #define tcg_gen_brcond_tl tcg_gen_brcond_i32
|
2296 | cb63669a | pbrook | #define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
|
2297 | be210acb | Richard Henderson | #define tcg_gen_setcond_tl tcg_gen_setcond_i32
|
2298 | add1e7ea | Aurelien Jarno | #define tcg_gen_setcondi_tl tcg_gen_setcondi_i32
|
2299 | f730fd27 | ths | #define tcg_gen_mul_tl tcg_gen_mul_i32
|
2300 | f730fd27 | ths | #define tcg_gen_muli_tl tcg_gen_muli_i32
|
2301 | ab36421e | aurel32 | #define tcg_gen_div_tl tcg_gen_div_i32
|
2302 | ab36421e | aurel32 | #define tcg_gen_rem_tl tcg_gen_rem_i32
|
2303 | 864951af | aurel32 | #define tcg_gen_divu_tl tcg_gen_divu_i32
|
2304 | 864951af | aurel32 | #define tcg_gen_remu_tl tcg_gen_remu_i32
|
2305 | a768e4b2 | blueswir1 | #define tcg_gen_discard_tl tcg_gen_discard_i32
|
2306 | e429073d | blueswir1 | #define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
|
2307 | e429073d | blueswir1 | #define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32
|
2308 | e429073d | blueswir1 | #define tcg_gen_extu_i32_tl tcg_gen_mov_i32
|
2309 | e429073d | blueswir1 | #define tcg_gen_ext_i32_tl tcg_gen_mov_i32
|
2310 | e429073d | blueswir1 | #define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
|
2311 | e429073d | blueswir1 | #define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
|
2312 | 0b6ce4cf | bellard | #define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
|
2313 | 0b6ce4cf | bellard | #define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
|
2314 | 0b6ce4cf | bellard | #define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
|
2315 | 0b6ce4cf | bellard | #define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
|
2316 | 0b6ce4cf | bellard | #define tcg_gen_ext32u_tl tcg_gen_mov_i32
|
2317 | 0b6ce4cf | bellard | #define tcg_gen_ext32s_tl tcg_gen_mov_i32
|
2318 | 911d79ba | aurel32 | #define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
|
2319 | 911d79ba | aurel32 | #define tcg_gen_bswap32_tl tcg_gen_bswap32_i32
|
2320 | 945ca823 | blueswir1 | #define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
|
2321 | f24cb33e | aurel32 | #define tcg_gen_andc_tl tcg_gen_andc_i32
|
2322 | f24cb33e | aurel32 | #define tcg_gen_eqv_tl tcg_gen_eqv_i32
|
2323 | f24cb33e | aurel32 | #define tcg_gen_nand_tl tcg_gen_nand_i32
|
2324 | f24cb33e | aurel32 | #define tcg_gen_nor_tl tcg_gen_nor_i32
|
2325 | f24cb33e | aurel32 | #define tcg_gen_orc_tl tcg_gen_orc_i32
|
2326 | 15824571 | aurel32 | #define tcg_gen_rotl_tl tcg_gen_rotl_i32
|
2327 | 15824571 | aurel32 | #define tcg_gen_rotli_tl tcg_gen_rotli_i32
|
2328 | 15824571 | aurel32 | #define tcg_gen_rotr_tl tcg_gen_rotr_i32
|
2329 | 15824571 | aurel32 | #define tcg_gen_rotri_tl tcg_gen_rotri_i32
|
2330 | a98824ac | blueswir1 | #define tcg_const_tl tcg_const_i32
|
2331 | bdffd4a9 | aurel32 | #define tcg_const_local_tl tcg_const_local_i32
|
2332 | f8422f52 | blueswir1 | #endif
|
2333 | 6ddbc6e4 | pbrook | |
2334 | 6ddbc6e4 | pbrook | #if TCG_TARGET_REG_BITS == 32 |
2335 | 48d38ca5 | ths | #define tcg_gen_add_ptr tcg_gen_add_i32
|
2336 | 6ddbc6e4 | pbrook | #define tcg_gen_addi_ptr tcg_gen_addi_i32
|
2337 | 48d38ca5 | ths | #define tcg_gen_ext_i32_ptr tcg_gen_mov_i32
|
2338 | 6ddbc6e4 | pbrook | #else /* TCG_TARGET_REG_BITS == 32 */ |
2339 | 48d38ca5 | ths | #define tcg_gen_add_ptr tcg_gen_add_i64
|
2340 | 6ddbc6e4 | pbrook | #define tcg_gen_addi_ptr tcg_gen_addi_i64
|
2341 | 48d38ca5 | ths | #define tcg_gen_ext_i32_ptr tcg_gen_ext_i32_i64
|
2342 | 6ddbc6e4 | pbrook | #endif /* TCG_TARGET_REG_BITS != 32 */ |