tcg: Allow target-specific implementation of EQV.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg: Use TCGCond where appropriate.
Use the TCGCond enumeration type in the brcond and setcondrelated prototypes in tcg-op.h and each code generator.
tcg: Name the opcode enumeration.
Give the enumeration formed from tcg-opc.h a name: TCGOpcode.Use that enumeration type instead of "int" whereever appropriate.
remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg/ppc64: Only define addend load helpers in softmmu case
Signed-off-by: malc <av1474@comtv.ru>
tcg/ppc64: Use C90 style comments
tcg: Add comments for all optional instructions not implemented.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tcg/ppc64: implement setcond
tcg/ppc64: Fix loading of 32bit constants
TCG: Mac OS X support for ppc64 target
Darwin/ppc64 does not use function descriptors,adapt prologue and tcg_out_call accordingly.GPR2 is available for general use, so let's use it.
http://developer.apple.com/mac/library/documentation/DeveloperTools/Conceptual/LowLevelABI/110-64-bit_PowerPC_Function_Calling_Conventions/64bitPowerPC.html...
tcg/ppc64,x86_64: fix constraints of op_qemu_st64
This op only takes two arguments, not two.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
PPC 32/64 GUEST_BASE support
Fix LHZX opcode value
Remove reserved registers from tcg_target_reg_alloc_order
Noticed by Andreas Faerber
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7082 c046a42c-6fe2-441c-8c8c-71466251a162
Whack [LS]MW
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7081 c046a42c-6fe2-441c-8c8c-71466251a162
Prune unused TCG_AREGs
Remove definitions for TCG_AREGs corresponding to AREG definitionsremoved in r6778.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6779 c046a42c-6fe2-441c-8c8c-71466251a162
Add missing r24..r26 to callee save registers
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6613 c046a42c-6fe2-441c-8c8c-71466251a162
Use the ARRAY_SIZE() macro where appropriate.
Change from v1: Avoid changing the existing coding style in certain files.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6120 c046a42c-6fe2-441c-8c8c-71466251a162
Introduce and use cache-utils.[ch]
Thanks to Segher Boessenkool and Holis Blanchard.
AIX and Darwin cache inquiry:http://gcc.gnu.org/ml/gcc-patches/2007-08/msg00388.html
Auxiliary vectors:http://manugarg.googlepages.com/aboutelfauxiliaryvectors
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5973 c046a42c-6fe2-441c-8c8c-71466251a162
Avoid compiler warning
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5710 c046a42c-6fe2-441c-8c8c-71466251a162
Fix alignment problem with some 64bit load/store instructions
LD/STD/LWA require displacement to be multiple of 4, providetcg_out_ldsta which checks the supplied displacement and fallsback on indexed variant when the check fails. All uses ofLD/STD/LWA outside of tcg_out_ldst appear to be safe....
Add some missing static and const qualifiers, reg_names only used if NDEBUG set
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5421 c046a42c-6fe2-441c-8c8c-71466251a162
Optimize 64 bit bswap
Use rldimi instead of rldicr/or pair, saves us one instruction.Suggested by Hollis Blanchard.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5404 c046a42c-6fe2-441c-8c8c-71466251a162
Fix some warnings that would be generated by gcc -Wredundant-decls
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162
Relax qemu_ld/st constraints for !SOFTMMU case
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5034 c046a42c-6fe2-441c-8c8c-71466251a162
Avoid clobbering input/aliased registers in !SOFTMMU+64bit+bswap case
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5033 c046a42c-6fe2-441c-8c8c-71466251a162
Clear the upper 32 bits of addr_reg in TARGET_LONG_BITS == 32 case
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5032 c046a42c-6fe2-441c-8c8c-71466251a162
Move tcg_out_tlb_read into #ifdef CONFIG_SOFTMMU block to avoid compiler warning
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5031 c046a42c-6fe2-441c-8c8c-71466251a162
Immediate versions of some operations
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4962 c046a42c-6fe2-441c-8c8c-71466251a162
Do not try handle "special" arguments of and/or/xor/shl/shr, upper level does it
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4961 c046a42c-6fe2-441c-8c8c-71466251a162
Set the L field of CMP[L][I] when dealing with 64 bit quantities
This (along with previous 2 commits) makes X86_64 work on ppc64 too.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4960 c046a42c-6fe2-441c-8c8c-71466251a162
Fix preprocessor guard condition
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4959 c046a42c-6fe2-441c-8c8c-71466251a162
Remove leftover from previous way to load 64 bit constants
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4958 c046a42c-6fe2-441c-8c8c-71466251a162
Special-case some paths inside tcg_out_tlb_read
a. Use 32bit arithmetics in TARGET_LONG_BITS 32 caseb. Optimize byte access case in TARGET_LONG_BITS 64 case
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4955 c046a42c-6fe2-441c-8c8c-71466251a162
Fix the opcode value of LWA
That should teach one to not blindly trust documentation that will(out of the blue) use decimal and binary representation for numbers inthe same chart for no apparent reason and without any prefixes, sigh..
Unbreaks MIPS.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4954 c046a42c-6fe2-441c-8c8c-71466251a162
Relax memory operations constraints
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4950 c046a42c-6fe2-441c-8c8c-71466251a162
Fix qemu_ld64 constraint list
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4949 c046a42c-6fe2-441c-8c8c-71466251a162
Use proper offset for LR save slot
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4948 c046a42c-6fe2-441c-8c8c-71466251a162
Reduce amount of space reserved for tb jump
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4947 c046a42c-6fe2-441c-8c8c-71466251a162
Fix and improve 64 bit immediate loading
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4946 c046a42c-6fe2-441c-8c8c-71466251a162
Fix EXTSW arguments
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4945 c046a42c-6fe2-441c-8c8c-71466251a162
Use proper value for TCG_TARGET_CALL_STACK_OFFSET
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4941 c046a42c-6fe2-441c-8c8c-71466251a162
Emit and use adhoc function descriptor for code_gen_prologue on PPC64
Thus avoiding fragile inline assembly hackery to call into generatedcode.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4939 c046a42c-6fe2-441c-8c8c-71466251a162
Remove neg_i32 debugging leftover
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4935 c046a42c-6fe2-441c-8c8c-71466251a162
Provide extNs_M instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4934 c046a42c-6fe2-441c-8c8c-71466251a162
Remove stray "i" from mul_i64
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4933 c046a42c-6fe2-441c-8c8c-71466251a162
Preliminary PPC64/Linux host support
ppc64.ld from Heikki Lindholm's patchhttp://marc.info/?l=qemu-devel&m=114086179024634&w=2
Issues:x86_64 tripple faults shortly after decompressing the kernelNo immediate versions of most 64 bit operationsMore......