Revision 8d625cf1
| b/tcg/README | ||
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| 213 | 213 |
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| 214 | 214 |
* eqv_i32/i64 t0, t1, t2 |
| 215 | 215 |
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t0=~(t1^t2) |
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t0=~(t1^t2), or equivalently, t0=t1^~t2
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| 217 | 217 |
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| 218 | 218 |
* nand_i32/i64 t0, t1, t2 |
| 219 | 219 |
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| b/tcg/arm/tcg-target.h | ||
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| 67 | 67 |
// #define TCG_TARGET_HAS_rot_i32 |
| 68 | 68 |
#define TCG_TARGET_HAS_andc_i32 |
| 69 | 69 |
// #define TCG_TARGET_HAS_orc_i32 |
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// #define TCG_TARGET_HAS_eqv_i32 |
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| 70 | 71 |
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| 71 | 72 |
#define TCG_TARGET_HAS_GUEST_BASE |
| 72 | 73 |
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| b/tcg/i386/tcg-target.h | ||
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| 57 | 57 |
#define TCG_TARGET_HAS_not_i32 |
| 58 | 58 |
// #define TCG_TARGET_HAS_andc_i32 |
| 59 | 59 |
// #define TCG_TARGET_HAS_orc_i32 |
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// #define TCG_TARGET_HAS_eqv_i32 |
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| 60 | 61 |
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| 61 | 62 |
#define TCG_TARGET_HAS_GUEST_BASE |
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| b/tcg/mips/tcg-target.h | ||
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| 87 | 87 |
#undef TCG_TARGET_HAS_bswap16_i32 |
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#undef TCG_TARGET_HAS_andc_i32 |
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#undef TCG_TARGET_HAS_orc_i32 |
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#undef TCG_TARGET_HAS_eqv_i32 |
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| 90 | 91 |
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| 91 | 92 |
/* optional instructions automatically implemented */ |
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#undef TCG_TARGET_HAS_neg_i32 /* sub rd, zero, rt */ |
| b/tcg/ppc/tcg-target.h | ||
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| 89 | 89 |
#define TCG_TARGET_HAS_neg_i32 |
| 90 | 90 |
#define TCG_TARGET_HAS_andc_i32 |
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#define TCG_TARGET_HAS_orc_i32 |
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/* #define TCG_TARGET_HAS_eqv_i32 */ |
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| 92 | 93 |
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| 93 | 94 |
#define TCG_AREG0 TCG_REG_R27 |
| 94 | 95 |
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| b/tcg/ppc64/tcg-target.h | ||
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| 80 | 80 |
#define TCG_TARGET_HAS_neg_i32 |
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/* #define TCG_TARGET_HAS_andc_i32 */ |
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/* #define TCG_TARGET_HAS_orc_i32 */ |
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/* #define TCG_TARGET_HAS_eqv_i32 */ |
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| 83 | 84 |
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| 84 | 85 |
#define TCG_TARGET_HAS_div_i64 |
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/* #define TCG_TARGET_HAS_rot_i64 */ |
| ... | ... | |
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#define TCG_TARGET_HAS_neg_i64 |
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/* #define TCG_TARGET_HAS_andc_i64 */ |
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/* #define TCG_TARGET_HAS_orc_i64 */ |
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/* #define TCG_TARGET_HAS_eqv_i64 */ |
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| 99 | 101 |
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| 100 | 102 |
#define TCG_AREG0 TCG_REG_R27 |
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| b/tcg/s390/tcg-target.h | ||
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| 59 | 59 |
// #define TCG_TARGET_HAS_neg_i32 |
| 60 | 60 |
// #define TCG_TARGET_HAS_andc_i32 |
| 61 | 61 |
// #define TCG_TARGET_HAS_orc_i32 |
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// #define TCG_TARGET_HAS_eqv_i32 |
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| 62 | 63 |
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| 63 | 64 |
// #define TCG_TARGET_HAS_div_i64 |
| 64 | 65 |
// #define TCG_TARGET_HAS_rot_i64 |
| ... | ... | |
| 75 | 76 |
// #define TCG_TARGET_HAS_neg_i64 |
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// #define TCG_TARGET_HAS_andc_i64 |
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// #define TCG_TARGET_HAS_orc_i64 |
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// #define TCG_TARGET_HAS_eqv_i64 |
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/* used for function call generation */ |
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#define TCG_REG_CALL_STACK TCG_REG_R15 |
| b/tcg/sparc/tcg-target.h | ||
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| 100 | 100 |
#define TCG_TARGET_HAS_not_i32 |
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#define TCG_TARGET_HAS_andc_i32 |
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#define TCG_TARGET_HAS_orc_i32 |
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// #define TCG_TARGET_HAS_eqv_i32 |
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| 103 | 104 |
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| 104 | 105 |
#if TCG_TARGET_REG_BITS == 64 |
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#define TCG_TARGET_HAS_div_i64 |
| ... | ... | |
| 117 | 118 |
#define TCG_TARGET_HAS_not_i64 |
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#define TCG_TARGET_HAS_andc_i64 |
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#define TCG_TARGET_HAS_orc_i64 |
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// #define TCG_TARGET_HAS_eqv_i64 |
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#endif |
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| 122 | 124 |
/* Note: must be synced with dyngen-exec.h */ |
| b/tcg/tcg-op.h | ||
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| 1740 | 1740 |
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| 1741 | 1741 |
static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
| 1742 | 1742 |
{
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#ifdef TCG_TARGET_HAS_eqv_i32 |
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tcg_gen_op3_i32(INDEX_op_eqv_i32, ret, arg1, arg2); |
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#else |
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tcg_gen_xor_i32(ret, arg1, arg2); |
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tcg_gen_not_i32(ret, ret); |
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#endif |
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} |
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static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
| 1748 | 1752 |
{
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#ifdef TCG_TARGET_HAS_eqv_i64 |
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tcg_gen_op3_i64(INDEX_op_eqv_i64, ret, arg1, arg2); |
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#elif defined(TCG_TARGET_HAS_eqv_i32) && TCG_TARGET_REG_BITS == 32 |
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tcg_gen_eqv_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
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tcg_gen_eqv_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
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#else |
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tcg_gen_xor_i64(ret, arg1, arg2); |
| 1750 | 1760 |
tcg_gen_not_i64(ret, ret); |
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#endif |
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} |
| 1752 | 1763 |
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static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
| b/tcg/tcg-opc.h | ||
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| 116 | 116 |
#ifdef TCG_TARGET_HAS_orc_i32 |
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DEF2(orc_i32, 1, 2, 0, 0) |
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#endif |
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#ifdef TCG_TARGET_HAS_eqv_i32 |
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DEF2(eqv_i32, 1, 2, 0, 0) |
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#endif |
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#if TCG_TARGET_REG_BITS == 64 |
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DEF2(mov_i64, 1, 1, 0, 0) |
| ... | ... | |
| 199 | 202 |
#ifdef TCG_TARGET_HAS_orc_i64 |
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DEF2(orc_i64, 1, 2, 0, 0) |
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#endif |
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#ifdef TCG_TARGET_HAS_eqv_i64 |
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DEF2(eqv_i64, 1, 2, 0, 0) |
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#endif |
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#endif |
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/* QEMU specific */ |
| b/tcg/x86_64/tcg-target.h | ||
|---|---|---|
| 84 | 84 |
// #define TCG_TARGET_HAS_andc_i64 |
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// #define TCG_TARGET_HAS_orc_i32 |
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// #define TCG_TARGET_HAS_orc_i64 |
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// #define TCG_TARGET_HAS_eqv_i32 |
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// #define TCG_TARGET_HAS_eqv_i64 |
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| 87 | 89 |
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| 88 | 90 |
#define TCG_TARGET_HAS_GUEST_BASE |
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