Revision 8da3ff18
| b/cpu-all.h | ||
|---|---|---|
| 877 | 877 |
typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value); |
| 878 | 878 |
typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr); |
| 879 | 879 |
|
| 880 |
void cpu_register_physical_memory(target_phys_addr_t start_addr, |
|
| 881 |
ram_addr_t size, |
|
| 882 |
ram_addr_t phys_offset); |
|
| 880 |
void cpu_register_physical_memory_offset(target_phys_addr_t start_addr, |
|
| 881 |
ram_addr_t size, |
|
| 882 |
ram_addr_t phys_offset, |
|
| 883 |
ram_addr_t region_offset); |
|
| 884 |
static inline void cpu_register_physical_memory(target_phys_addr_t start_addr, |
|
| 885 |
ram_addr_t size, |
|
| 886 |
ram_addr_t phys_offset) |
|
| 887 |
{
|
|
| 888 |
cpu_register_physical_memory_offset(start_addr, size, phys_offset, 0); |
|
| 889 |
} |
|
| 890 |
|
|
| 883 | 891 |
ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr); |
| 884 | 892 |
ram_addr_t qemu_ram_alloc(ram_addr_t); |
| 885 | 893 |
void qemu_ram_free(ram_addr_t addr); |
| b/exec.c | ||
|---|---|---|
| 146 | 146 |
typedef struct PhysPageDesc {
|
| 147 | 147 |
/* offset in host memory of the page + io_index in the low bits */ |
| 148 | 148 |
ram_addr_t phys_offset; |
| 149 |
ram_addr_t region_offset; |
|
| 149 | 150 |
} PhysPageDesc; |
| 150 | 151 |
|
| 151 | 152 |
#define L2_BITS 10 |
| ... | ... | |
| 199 | 200 |
CPUReadMemoryFunc **mem_read[TARGET_PAGE_SIZE][4]; |
| 200 | 201 |
CPUWriteMemoryFunc **mem_write[TARGET_PAGE_SIZE][4]; |
| 201 | 202 |
void *opaque[TARGET_PAGE_SIZE][2][4]; |
| 203 |
ram_addr_t region_offset[TARGET_PAGE_SIZE][2][4]; |
|
| 202 | 204 |
} subpage_t; |
| 203 | 205 |
|
| 204 | 206 |
#ifdef _WIN32 |
| ... | ... | |
| 1969 | 1971 |
and avoid full address decoding in every device. |
| 1970 | 1972 |
We can't use the high bits of pd for this because |
| 1971 | 1973 |
IO_MEM_ROMD uses these as a ram address. */ |
| 1972 |
iotlb = (pd & ~TARGET_PAGE_MASK) + paddr; |
|
| 1974 |
iotlb = (pd & ~TARGET_PAGE_MASK); |
|
| 1975 |
if (p) {
|
|
| 1976 |
/* FIXME: What if this isn't page aligned? */ |
|
| 1977 |
iotlb += p->region_offset; |
|
| 1978 |
} else {
|
|
| 1979 |
iotlb += paddr; |
|
| 1980 |
} |
|
| 1973 | 1981 |
} |
| 1974 | 1982 |
|
| 1975 | 1983 |
code_address = address; |
| ... | ... | |
| 2209 | 2217 |
#endif /* defined(CONFIG_USER_ONLY) */ |
| 2210 | 2218 |
|
| 2211 | 2219 |
#if !defined(CONFIG_USER_ONLY) |
| 2220 |
|
|
| 2212 | 2221 |
static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
| 2213 |
ram_addr_t memory); |
|
| 2222 |
ram_addr_t memory, ram_addr_t region_offset);
|
|
| 2214 | 2223 |
static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys, |
| 2215 |
ram_addr_t orig_memory); |
|
| 2224 |
ram_addr_t orig_memory, ram_addr_t region_offset);
|
|
| 2216 | 2225 |
#define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \ |
| 2217 | 2226 |
need_subpage) \ |
| 2218 | 2227 |
do { \
|
| ... | ... | |
| 2235 | 2244 |
|
| 2236 | 2245 |
/* register physical memory. 'size' must be a multiple of the target |
| 2237 | 2246 |
page size. If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an |
| 2238 |
io memory page */ |
|
| 2239 |
void cpu_register_physical_memory(target_phys_addr_t start_addr, |
|
| 2240 |
ram_addr_t size, |
|
| 2241 |
ram_addr_t phys_offset) |
|
| 2247 |
io memory page. The address used when calling the IO function is |
|
| 2248 |
the offset from the start of the region, plus region_offset. Both |
|
| 2249 |
start_region and regon_offset are rounded down to a page boundary |
|
| 2250 |
before calculating this offset. This should not be a problem unless |
|
| 2251 |
the low bits of start_addr and region_offset differ. */ |
|
| 2252 |
void cpu_register_physical_memory_offset(target_phys_addr_t start_addr, |
|
| 2253 |
ram_addr_t size, |
|
| 2254 |
ram_addr_t phys_offset, |
|
| 2255 |
ram_addr_t region_offset) |
|
| 2242 | 2256 |
{
|
| 2243 | 2257 |
target_phys_addr_t addr, end_addr; |
| 2244 | 2258 |
PhysPageDesc *p; |
| ... | ... | |
| 2256 | 2270 |
if (kvm_enabled()) |
| 2257 | 2271 |
kvm_set_phys_mem(start_addr, size, phys_offset); |
| 2258 | 2272 |
|
| 2273 |
region_offset &= TARGET_PAGE_MASK; |
|
| 2259 | 2274 |
size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; |
| 2260 | 2275 |
end_addr = start_addr + (target_phys_addr_t)size; |
| 2261 | 2276 |
for(addr = start_addr; addr != end_addr; addr += TARGET_PAGE_SIZE) {
|
| ... | ... | |
| 2270 | 2285 |
if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) {
|
| 2271 | 2286 |
if (!(orig_memory & IO_MEM_SUBPAGE)) {
|
| 2272 | 2287 |
subpage = subpage_init((addr & TARGET_PAGE_MASK), |
| 2273 |
&p->phys_offset, orig_memory); |
|
| 2288 |
&p->phys_offset, orig_memory, |
|
| 2289 |
p->region_offset); |
|
| 2274 | 2290 |
} else {
|
| 2275 | 2291 |
subpage = io_mem_opaque[(orig_memory & ~TARGET_PAGE_MASK) |
| 2276 | 2292 |
>> IO_MEM_SHIFT]; |
| 2277 | 2293 |
} |
| 2278 |
subpage_register(subpage, start_addr2, end_addr2, phys_offset); |
|
| 2294 |
subpage_register(subpage, start_addr2, end_addr2, phys_offset, |
|
| 2295 |
region_offset); |
|
| 2296 |
p->region_offset = 0; |
|
| 2279 | 2297 |
} else {
|
| 2280 | 2298 |
p->phys_offset = phys_offset; |
| 2281 | 2299 |
if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM || |
| ... | ... | |
| 2285 | 2303 |
} else {
|
| 2286 | 2304 |
p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1); |
| 2287 | 2305 |
p->phys_offset = phys_offset; |
| 2306 |
p->region_offset = region_offset; |
|
| 2288 | 2307 |
if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM || |
| 2289 |
(phys_offset & IO_MEM_ROMD)) |
|
| 2308 |
(phys_offset & IO_MEM_ROMD)) {
|
|
| 2290 | 2309 |
phys_offset += TARGET_PAGE_SIZE; |
| 2291 |
else {
|
|
| 2310 |
}else {
|
|
| 2292 | 2311 |
target_phys_addr_t start_addr2, end_addr2; |
| 2293 | 2312 |
int need_subpage = 0; |
| 2294 | 2313 |
|
| ... | ... | |
| 2297 | 2316 |
|
| 2298 | 2317 |
if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) {
|
| 2299 | 2318 |
subpage = subpage_init((addr & TARGET_PAGE_MASK), |
| 2300 |
&p->phys_offset, IO_MEM_UNASSIGNED); |
|
| 2319 |
&p->phys_offset, IO_MEM_UNASSIGNED, |
|
| 2320 |
0); |
|
| 2301 | 2321 |
subpage_register(subpage, start_addr2, end_addr2, |
| 2302 |
phys_offset); |
|
| 2322 |
phys_offset, region_offset); |
|
| 2323 |
p->region_offset = 0; |
|
| 2303 | 2324 |
} |
| 2304 | 2325 |
} |
| 2305 | 2326 |
} |
| 2327 |
region_offset += TARGET_PAGE_SIZE; |
|
| 2306 | 2328 |
} |
| 2307 | 2329 |
|
| 2308 | 2330 |
/* since each CPU stores ram addresses in its TLB cache, we must |
| ... | ... | |
| 2609 | 2631 |
uint32_t ret; |
| 2610 | 2632 |
unsigned int idx; |
| 2611 | 2633 |
|
| 2612 |
idx = SUBPAGE_IDX(addr - mmio->base);
|
|
| 2634 |
idx = SUBPAGE_IDX(addr); |
|
| 2613 | 2635 |
#if defined(DEBUG_SUBPAGE) |
| 2614 | 2636 |
printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__,
|
| 2615 | 2637 |
mmio, len, addr, idx); |
| 2616 | 2638 |
#endif |
| 2617 |
ret = (**mmio->mem_read[idx][len])(mmio->opaque[idx][0][len], addr); |
|
| 2639 |
ret = (**mmio->mem_read[idx][len])(mmio->opaque[idx][0][len], |
|
| 2640 |
addr + mmio->region_offset[idx][0][len]); |
|
| 2618 | 2641 |
|
| 2619 | 2642 |
return ret; |
| 2620 | 2643 |
} |
| ... | ... | |
| 2624 | 2647 |
{
|
| 2625 | 2648 |
unsigned int idx; |
| 2626 | 2649 |
|
| 2627 |
idx = SUBPAGE_IDX(addr - mmio->base);
|
|
| 2650 |
idx = SUBPAGE_IDX(addr); |
|
| 2628 | 2651 |
#if defined(DEBUG_SUBPAGE) |
| 2629 | 2652 |
printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d value %08x\n", __func__,
|
| 2630 | 2653 |
mmio, len, addr, idx, value); |
| 2631 | 2654 |
#endif |
| 2632 |
(**mmio->mem_write[idx][len])(mmio->opaque[idx][1][len], addr, value); |
|
| 2655 |
(**mmio->mem_write[idx][len])(mmio->opaque[idx][1][len], |
|
| 2656 |
addr + mmio->region_offset[idx][1][len], |
|
| 2657 |
value); |
|
| 2633 | 2658 |
} |
| 2634 | 2659 |
|
| 2635 | 2660 |
static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr) |
| ... | ... | |
| 2699 | 2724 |
}; |
| 2700 | 2725 |
|
| 2701 | 2726 |
static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
| 2702 |
ram_addr_t memory) |
|
| 2727 |
ram_addr_t memory, ram_addr_t region_offset)
|
|
| 2703 | 2728 |
{
|
| 2704 | 2729 |
int idx, eidx; |
| 2705 | 2730 |
unsigned int i; |
| ... | ... | |
| 2718 | 2743 |
if (io_mem_read[memory][i]) {
|
| 2719 | 2744 |
mmio->mem_read[idx][i] = &io_mem_read[memory][i]; |
| 2720 | 2745 |
mmio->opaque[idx][0][i] = io_mem_opaque[memory]; |
| 2746 |
mmio->region_offset[idx][0][i] = region_offset; |
|
| 2721 | 2747 |
} |
| 2722 | 2748 |
if (io_mem_write[memory][i]) {
|
| 2723 | 2749 |
mmio->mem_write[idx][i] = &io_mem_write[memory][i]; |
| 2724 | 2750 |
mmio->opaque[idx][1][i] = io_mem_opaque[memory]; |
| 2751 |
mmio->region_offset[idx][1][i] = region_offset; |
|
| 2725 | 2752 |
} |
| 2726 | 2753 |
} |
| 2727 | 2754 |
} |
| ... | ... | |
| 2730 | 2757 |
} |
| 2731 | 2758 |
|
| 2732 | 2759 |
static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys, |
| 2733 |
ram_addr_t orig_memory) |
|
| 2760 |
ram_addr_t orig_memory, ram_addr_t region_offset)
|
|
| 2734 | 2761 |
{
|
| 2735 | 2762 |
subpage_t *mmio; |
| 2736 | 2763 |
int subpage_memory; |
| ... | ... | |
| 2744 | 2771 |
mmio, base, TARGET_PAGE_SIZE, subpage_memory); |
| 2745 | 2772 |
#endif |
| 2746 | 2773 |
*phys = subpage_memory | IO_MEM_SUBPAGE; |
| 2747 |
subpage_register(mmio, 0, TARGET_PAGE_SIZE - 1, orig_memory); |
|
| 2774 |
subpage_register(mmio, 0, TARGET_PAGE_SIZE - 1, orig_memory, |
|
| 2775 |
region_offset); |
|
| 2748 | 2776 |
} |
| 2749 | 2777 |
|
| 2750 | 2778 |
return mmio; |
| ... | ... | |
| 2878 | 2906 |
if (is_write) {
|
| 2879 | 2907 |
if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
|
| 2880 | 2908 |
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
| 2909 |
if (p) |
|
| 2910 |
addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
|
| 2881 | 2911 |
/* XXX: could force cpu_single_env to NULL to avoid |
| 2882 | 2912 |
potential bugs */ |
| 2883 | 2913 |
if (l >= 4 && ((addr & 3) == 0)) {
|
| ... | ... | |
| 2915 | 2945 |
!(pd & IO_MEM_ROMD)) {
|
| 2916 | 2946 |
/* I/O case */ |
| 2917 | 2947 |
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
| 2948 |
if (p) |
|
| 2949 |
addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
|
| 2918 | 2950 |
if (l >= 4 && ((addr & 3) == 0)) {
|
| 2919 | 2951 |
/* 32 bit read access */ |
| 2920 | 2952 |
val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr); |
| ... | ... | |
| 3004 | 3036 |
!(pd & IO_MEM_ROMD)) {
|
| 3005 | 3037 |
/* I/O case */ |
| 3006 | 3038 |
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
| 3039 |
if (p) |
|
| 3040 |
addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
|
| 3007 | 3041 |
val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr); |
| 3008 | 3042 |
} else {
|
| 3009 | 3043 |
/* RAM case */ |
| ... | ... | |
| 3034 | 3068 |
!(pd & IO_MEM_ROMD)) {
|
| 3035 | 3069 |
/* I/O case */ |
| 3036 | 3070 |
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
| 3071 |
if (p) |
|
| 3072 |
addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
|
| 3037 | 3073 |
#ifdef TARGET_WORDS_BIGENDIAN |
| 3038 | 3074 |
val = (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr) << 32; |
| 3039 | 3075 |
val |= io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4); |
| ... | ... | |
| 3085 | 3121 |
|
| 3086 | 3122 |
if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
|
| 3087 | 3123 |
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
| 3124 |
if (p) |
|
| 3125 |
addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
|
| 3088 | 3126 |
io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); |
| 3089 | 3127 |
} else {
|
| 3090 | 3128 |
unsigned long addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
| ... | ... | |
| 3119 | 3157 |
|
| 3120 | 3158 |
if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
|
| 3121 | 3159 |
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
| 3160 |
if (p) |
|
| 3161 |
addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
|
| 3122 | 3162 |
#ifdef TARGET_WORDS_BIGENDIAN |
| 3123 | 3163 |
io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val >> 32); |
| 3124 | 3164 |
io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val); |
| ... | ... | |
| 3150 | 3190 |
|
| 3151 | 3191 |
if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
|
| 3152 | 3192 |
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
| 3193 |
if (p) |
|
| 3194 |
addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
|
| 3153 | 3195 |
io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); |
| 3154 | 3196 |
} else {
|
| 3155 | 3197 |
unsigned long addr1; |
| b/hw/arm_gic.c | ||
|---|---|---|
| 23 | 23 |
#ifdef NVIC |
| 24 | 24 |
static const uint8_t gic_id[] = |
| 25 | 25 |
{ 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1 };
|
| 26 |
#define GIC_DIST_OFFSET 0 |
|
| 27 | 26 |
/* The NVIC has 16 internal vectors. However these are not exposed |
| 28 | 27 |
through the normal GIC interface. */ |
| 29 | 28 |
#define GIC_BASE_IRQ 32 |
| 30 | 29 |
#else |
| 31 | 30 |
static const uint8_t gic_id[] = |
| 32 | 31 |
{ 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
|
| 33 |
#define GIC_DIST_OFFSET 0x1000 |
|
| 34 | 32 |
#define GIC_BASE_IRQ 0 |
| 35 | 33 |
#endif |
| 36 | 34 |
|
| ... | ... | |
| 76 | 74 |
|
| 77 | 75 |
typedef struct gic_state |
| 78 | 76 |
{
|
| 79 |
uint32_t base; |
|
| 80 | 77 |
qemu_irq parent_irq[NCPU]; |
| 81 | 78 |
int enabled; |
| 82 | 79 |
int cpu_enabled[NCPU]; |
| ... | ... | |
| 252 | 249 |
|
| 253 | 250 |
cpu = gic_get_current_cpu(); |
| 254 | 251 |
cm = 1 << cpu; |
| 255 |
offset -= s->base + GIC_DIST_OFFSET; |
|
| 256 | 252 |
if (offset < 0x100) {
|
| 257 | 253 |
#ifndef NVIC |
| 258 | 254 |
if (offset == 0) |
| ... | ... | |
| 365 | 361 |
#ifdef NVIC |
| 366 | 362 |
gic_state *s = (gic_state *)opaque; |
| 367 | 363 |
uint32_t addr; |
| 368 |
addr = offset - s->base;
|
|
| 364 |
addr = offset; |
|
| 369 | 365 |
if (addr < 0x100 || addr > 0xd00) |
| 370 | 366 |
return nvic_readl(s->nvic, addr); |
| 371 | 367 |
#endif |
| ... | ... | |
| 383 | 379 |
int cpu; |
| 384 | 380 |
|
| 385 | 381 |
cpu = gic_get_current_cpu(); |
| 386 |
offset -= s->base + GIC_DIST_OFFSET; |
|
| 387 | 382 |
if (offset < 0x100) {
|
| 388 | 383 |
#ifdef NVIC |
| 389 | 384 |
goto bad_reg; |
| ... | ... | |
| 526 | 521 |
gic_state *s = (gic_state *)opaque; |
| 527 | 522 |
#ifdef NVIC |
| 528 | 523 |
uint32_t addr; |
| 529 |
addr = offset - s->base;
|
|
| 524 |
addr = offset; |
|
| 530 | 525 |
if (addr < 0x100 || (addr > 0xd00 && addr != 0xf00)) {
|
| 531 | 526 |
nvic_writel(s->nvic, addr, value); |
| 532 | 527 |
return; |
| 533 | 528 |
} |
| 534 | 529 |
#endif |
| 535 |
if (offset - s->base == GIC_DIST_OFFSET + 0xf00) {
|
|
| 530 |
if (offset == 0xf00) {
|
|
| 536 | 531 |
int cpu; |
| 537 | 532 |
int irq; |
| 538 | 533 |
int mask; |
| ... | ... | |
| 723 | 718 |
return 0; |
| 724 | 719 |
} |
| 725 | 720 |
|
| 726 |
static gic_state *gic_init(uint32_t base, qemu_irq *parent_irq) |
|
| 721 |
static gic_state *gic_init(uint32_t dist_base, qemu_irq *parent_irq)
|
|
| 727 | 722 |
{
|
| 728 | 723 |
gic_state *s; |
| 729 | 724 |
int iomemtype; |
| ... | ... | |
| 738 | 733 |
} |
| 739 | 734 |
iomemtype = cpu_register_io_memory(0, gic_dist_readfn, |
| 740 | 735 |
gic_dist_writefn, s); |
| 741 |
cpu_register_physical_memory(base + GIC_DIST_OFFSET, 0x00001000,
|
|
| 736 |
cpu_register_physical_memory(dist_base, 0x00001000,
|
|
| 742 | 737 |
iomemtype); |
| 743 |
s->base = base; |
|
| 744 | 738 |
gic_reset(s); |
| 745 | 739 |
register_savevm("arm_gic", -1, 1, gic_save, gic_load, s);
|
| 746 | 740 |
return s; |
| b/hw/arm_sysctl.c | ||
|---|---|---|
| 14 | 14 |
#define LOCK_VALUE 0xa05f |
| 15 | 15 |
|
| 16 | 16 |
typedef struct {
|
| 17 |
uint32_t base; |
|
| 18 | 17 |
uint32_t sys_id; |
| 19 | 18 |
uint32_t leds; |
| 20 | 19 |
uint16_t lockval; |
| ... | ... | |
| 29 | 28 |
{
|
| 30 | 29 |
arm_sysctl_state *s = (arm_sysctl_state *)opaque; |
| 31 | 30 |
|
| 32 |
offset -= s->base; |
|
| 33 | 31 |
switch (offset) {
|
| 34 | 32 |
case 0x00: /* ID */ |
| 35 | 33 |
return s->sys_id; |
| ... | ... | |
| 108 | 106 |
uint32_t val) |
| 109 | 107 |
{
|
| 110 | 108 |
arm_sysctl_state *s = (arm_sysctl_state *)opaque; |
| 111 |
offset -= s->base; |
|
| 112 | 109 |
|
| 113 | 110 |
switch (offset) {
|
| 114 | 111 |
case 0x08: /* LED */ |
| ... | ... | |
| 199 | 196 |
s = (arm_sysctl_state *)qemu_mallocz(sizeof(arm_sysctl_state)); |
| 200 | 197 |
if (!s) |
| 201 | 198 |
return; |
| 202 |
s->base = base; |
|
| 203 | 199 |
s->sys_id = sys_id; |
| 204 | 200 |
/* The MPcore bootloader uses these flags to start secondary CPUs. |
| 205 | 201 |
We don't use a bootloader, so do this here. */ |
| b/hw/arm_timer.c | ||
|---|---|---|
| 190 | 190 |
typedef struct {
|
| 191 | 191 |
void *timer[2]; |
| 192 | 192 |
int level[2]; |
| 193 |
uint32_t base; |
|
| 194 | 193 |
qemu_irq irq; |
| 195 | 194 |
} sp804_state; |
| 196 | 195 |
|
| ... | ... | |
| 208 | 207 |
sp804_state *s = (sp804_state *)opaque; |
| 209 | 208 |
|
| 210 | 209 |
/* ??? Don't know the PrimeCell ID for this device. */ |
| 211 |
offset -= s->base; |
|
| 212 | 210 |
if (offset < 0x20) {
|
| 213 | 211 |
return arm_timer_read(s->timer[0], offset); |
| 214 | 212 |
} else {
|
| ... | ... | |
| 221 | 219 |
{
|
| 222 | 220 |
sp804_state *s = (sp804_state *)opaque; |
| 223 | 221 |
|
| 224 |
offset -= s->base; |
|
| 225 | 222 |
if (offset < 0x20) {
|
| 226 | 223 |
arm_timer_write(s->timer[0], offset, value); |
| 227 | 224 |
} else {
|
| ... | ... | |
| 268 | 265 |
|
| 269 | 266 |
s = (sp804_state *)qemu_mallocz(sizeof(sp804_state)); |
| 270 | 267 |
qi = qemu_allocate_irqs(sp804_set_irq, s, 2); |
| 271 |
s->base = base; |
|
| 272 | 268 |
s->irq = irq; |
| 273 | 269 |
/* ??? The timers are actually configurable between 32kHz and 1MHz, but |
| 274 | 270 |
we don't implement that. */ |
| ... | ... | |
| 285 | 281 |
|
| 286 | 282 |
typedef struct {
|
| 287 | 283 |
void *timer[3]; |
| 288 |
uint32_t base; |
|
| 289 | 284 |
} icp_pit_state; |
| 290 | 285 |
|
| 291 | 286 |
static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset) |
| ... | ... | |
| 294 | 289 |
int n; |
| 295 | 290 |
|
| 296 | 291 |
/* ??? Don't know the PrimeCell ID for this device. */ |
| 297 |
offset -= s->base; |
|
| 298 | 292 |
n = offset >> 8; |
| 299 | 293 |
if (n > 3) |
| 300 | 294 |
cpu_abort(cpu_single_env, "sp804_read: Bad timer %d\n", n); |
| ... | ... | |
| 308 | 302 |
icp_pit_state *s = (icp_pit_state *)opaque; |
| 309 | 303 |
int n; |
| 310 | 304 |
|
| 311 |
offset -= s->base; |
|
| 312 | 305 |
n = offset >> 8; |
| 313 | 306 |
if (n > 3) |
| 314 | 307 |
cpu_abort(cpu_single_env, "sp804_write: Bad timer %d\n", n); |
| ... | ... | |
| 335 | 328 |
icp_pit_state *s; |
| 336 | 329 |
|
| 337 | 330 |
s = (icp_pit_state *)qemu_mallocz(sizeof(icp_pit_state)); |
| 338 |
s->base = base; |
|
| 339 | 331 |
/* Timer 0 runs at the system clock speed (40MHz). */ |
| 340 | 332 |
s->timer[0] = arm_timer_init(40000000, pic[irq]); |
| 341 | 333 |
/* The other two timers run at 1MHz. */ |
| b/hw/armv7m.c | ||
|---|---|---|
| 14 | 14 |
/* Bitbanded IO. Each word corresponds to a single bit. */ |
| 15 | 15 |
|
| 16 | 16 |
/* Get the byte address of the real memory for a bitband acess. */ |
| 17 |
static inline uint32_t bitband_addr(uint32_t addr) |
|
| 17 |
static inline uint32_t bitband_addr(void * opaque, uint32_t addr)
|
|
| 18 | 18 |
{
|
| 19 | 19 |
uint32_t res; |
| 20 | 20 |
|
| 21 |
res = addr & 0xe0000000;
|
|
| 21 |
res = *(uint32_t *)opaque;
|
|
| 22 | 22 |
res |= (addr & 0x1ffffff) >> 5; |
| 23 | 23 |
return res; |
| 24 | 24 |
|
| ... | ... | |
| 27 | 27 |
static uint32_t bitband_readb(void *opaque, target_phys_addr_t offset) |
| 28 | 28 |
{
|
| 29 | 29 |
uint8_t v; |
| 30 |
cpu_physical_memory_read(bitband_addr(offset), &v, 1); |
|
| 30 |
cpu_physical_memory_read(bitband_addr(opaque, offset), &v, 1);
|
|
| 31 | 31 |
return (v & (1 << ((offset >> 2) & 7))) != 0; |
| 32 | 32 |
} |
| 33 | 33 |
|
| ... | ... | |
| 37 | 37 |
uint32_t addr; |
| 38 | 38 |
uint8_t mask; |
| 39 | 39 |
uint8_t v; |
| 40 |
addr = bitband_addr(offset); |
|
| 40 |
addr = bitband_addr(opaque, offset);
|
|
| 41 | 41 |
mask = (1 << ((offset >> 2) & 7)); |
| 42 | 42 |
cpu_physical_memory_read(addr, &v, 1); |
| 43 | 43 |
if (value & 1) |
| ... | ... | |
| 52 | 52 |
uint32_t addr; |
| 53 | 53 |
uint16_t mask; |
| 54 | 54 |
uint16_t v; |
| 55 |
addr = bitband_addr(offset) & ~1; |
|
| 55 |
addr = bitband_addr(opaque, offset) & ~1;
|
|
| 56 | 56 |
mask = (1 << ((offset >> 2) & 15)); |
| 57 | 57 |
mask = tswap16(mask); |
| 58 | 58 |
cpu_physical_memory_read(addr, (uint8_t *)&v, 2); |
| ... | ... | |
| 65 | 65 |
uint32_t addr; |
| 66 | 66 |
uint16_t mask; |
| 67 | 67 |
uint16_t v; |
| 68 |
addr = bitband_addr(offset) & ~1; |
|
| 68 |
addr = bitband_addr(opaque, offset) & ~1;
|
|
| 69 | 69 |
mask = (1 << ((offset >> 2) & 15)); |
| 70 | 70 |
mask = tswap16(mask); |
| 71 | 71 |
cpu_physical_memory_read(addr, (uint8_t *)&v, 2); |
| ... | ... | |
| 81 | 81 |
uint32_t addr; |
| 82 | 82 |
uint32_t mask; |
| 83 | 83 |
uint32_t v; |
| 84 |
addr = bitband_addr(offset) & ~3; |
|
| 84 |
addr = bitband_addr(opaque, offset) & ~3;
|
|
| 85 | 85 |
mask = (1 << ((offset >> 2) & 31)); |
| 86 | 86 |
mask = tswap32(mask); |
| 87 | 87 |
cpu_physical_memory_read(addr, (uint8_t *)&v, 4); |
| ... | ... | |
| 94 | 94 |
uint32_t addr; |
| 95 | 95 |
uint32_t mask; |
| 96 | 96 |
uint32_t v; |
| 97 |
addr = bitband_addr(offset) & ~3; |
|
| 97 |
addr = bitband_addr(opaque, offset) & ~3;
|
|
| 98 | 98 |
mask = (1 << ((offset >> 2) & 31)); |
| 99 | 99 |
mask = tswap32(mask); |
| 100 | 100 |
cpu_physical_memory_read(addr, (uint8_t *)&v, 4); |
| ... | ... | |
| 120 | 120 |
static void armv7m_bitband_init(void) |
| 121 | 121 |
{
|
| 122 | 122 |
int iomemtype; |
| 123 |
static uint32_t bitband1_offset = 0x20000000; |
|
| 124 |
static uint32_t bitband2_offset = 0x40000000; |
|
| 123 | 125 |
|
| 124 | 126 |
iomemtype = cpu_register_io_memory(0, bitband_readfn, bitband_writefn, |
| 125 |
NULL);
|
|
| 127 |
&bitband1_offset);
|
|
| 126 | 128 |
cpu_register_physical_memory(0x22000000, 0x02000000, iomemtype); |
| 129 |
iomemtype = cpu_register_io_memory(0, bitband_readfn, bitband_writefn, |
|
| 130 |
&bitband2_offset); |
|
| 127 | 131 |
cpu_register_physical_memory(0x42000000, 0x02000000, iomemtype); |
| 128 | 132 |
} |
| 129 | 133 |
|
| b/hw/ds1225y.c | ||
|---|---|---|
| 30 | 30 |
|
| 31 | 31 |
typedef struct ds1225y_t |
| 32 | 32 |
{
|
| 33 |
target_phys_addr_t mem_base; |
|
| 34 | 33 |
uint32_t chip_size; |
| 35 | 34 |
QEMUFile *file; |
| 36 | 35 |
uint8_t *contents; |
| ... | ... | |
| 41 | 40 |
static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr) |
| 42 | 41 |
{
|
| 43 | 42 |
ds1225y_t *s = opaque; |
| 44 |
int64_t pos; |
|
| 45 | 43 |
uint32_t val; |
| 46 | 44 |
|
| 47 |
pos = addr - s->mem_base; |
|
| 48 |
if (pos >= s->chip_size) |
|
| 49 |
pos -= s->chip_size; |
|
| 50 |
|
|
| 51 |
val = s->contents[pos]; |
|
| 45 |
val = s->contents[addr]; |
|
| 52 | 46 |
|
| 53 | 47 |
#ifdef DEBUG_NVRAM |
| 54 | 48 |
printf("nvram: read 0x%x at " TARGET_FMT_lx "\n", val, addr);
|
| ... | ... | |
| 77 | 71 |
static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t val) |
| 78 | 72 |
{
|
| 79 | 73 |
ds1225y_t *s = opaque; |
| 80 |
int64_t pos; |
|
| 81 | 74 |
|
| 82 | 75 |
#ifdef DEBUG_NVRAM |
| 83 | 76 |
printf("nvram: write 0x%x at " TARGET_FMT_lx "\n", val, addr);
|
| 84 | 77 |
#endif |
| 85 | 78 |
|
| 86 |
pos = addr - s->mem_base; |
|
| 87 |
s->contents[pos] = val & 0xff; |
|
| 79 |
s->contents[addr] = val & 0xff; |
|
| 88 | 80 |
if (s->file) {
|
| 89 |
qemu_fseek(s->file, pos, SEEK_SET);
|
|
| 81 |
qemu_fseek(s->file, addr, SEEK_SET);
|
|
| 90 | 82 |
qemu_put_byte(s->file, (int)val); |
| 91 | 83 |
qemu_fflush(s->file); |
| 92 | 84 |
} |
| ... | ... | |
| 117 | 109 |
return; |
| 118 | 110 |
} |
| 119 | 111 |
|
| 120 |
nvram_writeb(opaque, addr - s->chip_size, val);
|
|
| 112 |
nvram_writeb(opaque, addr, val); |
|
| 121 | 113 |
} |
| 122 | 114 |
|
| 123 | 115 |
static void nvram_writew_protected (void *opaque, target_phys_addr_t addr, uint32_t val) |
| ... | ... | |
| 167 | 159 |
if (!s->contents) {
|
| 168 | 160 |
return NULL; |
| 169 | 161 |
} |
| 170 |
s->mem_base = mem_base; |
|
| 171 | 162 |
s->protection = 7; |
| 172 | 163 |
|
| 173 | 164 |
/* Read current file */ |
| b/hw/e1000.c | ||
|---|---|---|
| 76 | 76 |
PCIDevice dev; |
| 77 | 77 |
VLANClientState *vc; |
| 78 | 78 |
NICInfo *nd; |
| 79 |
uint32_t mmio_base; |
|
| 80 | 79 |
int mmio_index; |
| 81 | 80 |
|
| 82 | 81 |
uint32_t mac_reg[0x8000]; |
| ... | ... | |
| 786 | 785 |
e1000_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 787 | 786 |
{
|
| 788 | 787 |
E1000State *s = opaque; |
| 789 |
unsigned int index = ((addr - s->mmio_base) & 0x1ffff) >> 2;
|
|
| 788 |
unsigned int index = (addr & 0x1ffff) >> 2;
|
|
| 790 | 789 |
|
| 791 | 790 |
#ifdef TARGET_WORDS_BIGENDIAN |
| 792 | 791 |
val = bswap32(val); |
| ... | ... | |
| 820 | 819 |
e1000_mmio_readl(void *opaque, target_phys_addr_t addr) |
| 821 | 820 |
{
|
| 822 | 821 |
E1000State *s = opaque; |
| 823 |
unsigned int index = ((addr - s->mmio_base) & 0x1ffff) >> 2;
|
|
| 822 |
unsigned int index = (addr & 0x1ffff) >> 2;
|
|
| 824 | 823 |
|
| 825 | 824 |
if (index < NREADOPS && macreg_readops[index]) |
| 826 | 825 |
{
|
| ... | ... | |
| 870 | 869 |
int i, j; |
| 871 | 870 |
|
| 872 | 871 |
pci_device_save(&s->dev, f); |
| 873 |
qemu_put_be32s(f, &s->mmio_base);
|
|
| 872 |
qemu_put_be32(f, 0);
|
|
| 874 | 873 |
qemu_put_be32s(f, &s->rxbuf_size); |
| 875 | 874 |
qemu_put_be32s(f, &s->rxbuf_min_shift); |
| 876 | 875 |
qemu_put_be32s(f, &s->eecd_state.val_in); |
| ... | ... | |
| 916 | 915 |
return ret; |
| 917 | 916 |
if (version_id == 1) |
| 918 | 917 |
qemu_get_sbe32s(f, &i); /* once some unused instance id */ |
| 919 |
qemu_get_be32s(f, &s->mmio_base);
|
|
| 918 |
qemu_get_be32(f); /* Ignored. Was mmio_base. */
|
|
| 920 | 919 |
qemu_get_be32s(f, &s->rxbuf_size); |
| 921 | 920 |
qemu_get_be32s(f, &s->rxbuf_min_shift); |
| 922 | 921 |
qemu_get_be32s(f, &s->eecd_state.val_in); |
| ... | ... | |
| 1005 | 1004 |
|
| 1006 | 1005 |
DBGOUT(MMIO, "e1000_mmio_map addr=0x%08x 0x%08x\n", addr, size); |
| 1007 | 1006 |
|
| 1008 |
d->mmio_base = addr; |
|
| 1009 | 1007 |
cpu_register_physical_memory(addr, PNPMMIO_SIZE, d->mmio_index); |
| 1010 | 1008 |
} |
| 1011 | 1009 |
|
| b/hw/eepro100.c | ||
|---|---|---|
| 1392 | 1392 |
static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 1393 | 1393 |
{
|
| 1394 | 1394 |
EEPRO100State *s = opaque; |
| 1395 |
addr -= s->region[0]; |
|
| 1396 | 1395 |
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
|
| 1397 | 1396 |
eepro100_write1(s, addr, val); |
| 1398 | 1397 |
} |
| ... | ... | |
| 1400 | 1399 |
static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 1401 | 1400 |
{
|
| 1402 | 1401 |
EEPRO100State *s = opaque; |
| 1403 |
addr -= s->region[0]; |
|
| 1404 | 1402 |
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
|
| 1405 | 1403 |
eepro100_write2(s, addr, val); |
| 1406 | 1404 |
} |
| ... | ... | |
| 1408 | 1406 |
static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 1409 | 1407 |
{
|
| 1410 | 1408 |
EEPRO100State *s = opaque; |
| 1411 |
addr -= s->region[0]; |
|
| 1412 | 1409 |
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
|
| 1413 | 1410 |
eepro100_write4(s, addr, val); |
| 1414 | 1411 |
} |
| ... | ... | |
| 1416 | 1413 |
static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr) |
| 1417 | 1414 |
{
|
| 1418 | 1415 |
EEPRO100State *s = opaque; |
| 1419 |
addr -= s->region[0]; |
|
| 1420 | 1416 |
//~ logout("addr=%s\n", regname(addr));
|
| 1421 | 1417 |
return eepro100_read1(s, addr); |
| 1422 | 1418 |
} |
| ... | ... | |
| 1424 | 1420 |
static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr) |
| 1425 | 1421 |
{
|
| 1426 | 1422 |
EEPRO100State *s = opaque; |
| 1427 |
addr -= s->region[0]; |
|
| 1428 | 1423 |
//~ logout("addr=%s\n", regname(addr));
|
| 1429 | 1424 |
return eepro100_read2(s, addr); |
| 1430 | 1425 |
} |
| ... | ... | |
| 1432 | 1427 |
static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr) |
| 1433 | 1428 |
{
|
| 1434 | 1429 |
EEPRO100State *s = opaque; |
| 1435 |
addr -= s->region[0]; |
|
| 1436 | 1430 |
//~ logout("addr=%s\n", regname(addr));
|
| 1437 | 1431 |
return eepro100_read4(s, addr); |
| 1438 | 1432 |
} |
| b/hw/etraxfs_dma.c | ||
|---|---|---|
| 188 | 188 |
struct fs_dma_ctrl |
| 189 | 189 |
{
|
| 190 | 190 |
CPUState *env; |
| 191 |
target_phys_addr_t base; |
|
| 192 | 191 |
|
| 193 | 192 |
int nr_channels; |
| 194 | 193 |
struct fs_dma_channel *channels; |
| ... | ... | |
| 212 | 211 |
&& ctrl->channels[c].client; |
| 213 | 212 |
} |
| 214 | 213 |
|
| 215 |
static inline int fs_channel(target_phys_addr_t base, target_phys_addr_t addr)
|
|
| 214 |
static inline int fs_channel(target_phys_addr_t addr) |
|
| 216 | 215 |
{
|
| 217 | 216 |
/* Every channel has a 0x2000 ctrl register map. */ |
| 218 |
return (addr - base) >> 13;
|
|
| 217 |
return addr >> 13;
|
|
| 219 | 218 |
} |
| 220 | 219 |
|
| 221 | 220 |
#ifdef USE_THIS_DEAD_CODE |
| ... | ... | |
| 572 | 571 |
uint32_t r = 0; |
| 573 | 572 |
|
| 574 | 573 |
/* Make addr relative to this instances base. */ |
| 575 |
c = fs_channel(ctrl->base, addr);
|
|
| 574 |
c = fs_channel(addr); |
|
| 576 | 575 |
addr &= 0x1fff; |
| 577 | 576 |
switch (addr) |
| 578 | 577 |
{
|
| ... | ... | |
| 618 | 617 |
int c; |
| 619 | 618 |
|
| 620 | 619 |
/* Make addr relative to this instances base. */ |
| 621 |
c = fs_channel(ctrl->base, addr);
|
|
| 620 |
c = fs_channel(addr); |
|
| 622 | 621 |
addr &= 0x1fff; |
| 623 | 622 |
switch (addr) |
| 624 | 623 |
{
|
| ... | ... | |
| 753 | 752 |
|
| 754 | 753 |
ctrl->bh = qemu_bh_new(DMA_run, ctrl); |
| 755 | 754 |
|
| 756 |
ctrl->base = base; |
|
| 757 | 755 |
ctrl->env = env; |
| 758 | 756 |
ctrl->nr_channels = nr_channels; |
| 759 | 757 |
ctrl->channels = qemu_mallocz(sizeof ctrl->channels[0] * nr_channels); |
| ... | ... | |
| 766 | 764 |
dma_read, |
| 767 | 765 |
dma_write, |
| 768 | 766 |
ctrl); |
| 769 |
cpu_register_physical_memory (base + i * 0x2000, |
|
| 770 |
sizeof ctrl->channels[i].regs,
|
|
| 771 |
ctrl->channels[i].regmap);
|
|
| 767 |
cpu_register_physical_memory_offset (base + i * 0x2000,
|
|
| 768 |
sizeof ctrl->channels[i].regs, ctrl->channels[i].regmap,
|
|
| 769 |
i * 0x2000);
|
|
| 772 | 770 |
} |
| 773 | 771 |
|
| 774 | 772 |
return ctrl; |
| b/hw/etraxfs_eth.c | ||
|---|---|---|
| 314 | 314 |
{
|
| 315 | 315 |
CPUState *env; |
| 316 | 316 |
qemu_irq *irq; |
| 317 |
target_phys_addr_t base; |
|
| 318 | 317 |
VLANClientState *vc; |
| 319 | 318 |
int ethregs; |
| 320 | 319 |
|
| ... | ... | |
| 375 | 374 |
struct fs_eth *eth = opaque; |
| 376 | 375 |
uint32_t r = 0; |
| 377 | 376 |
|
| 378 |
/* Make addr relative to this instances base. */ |
|
| 379 |
addr -= eth->base; |
|
| 380 | 377 |
switch (addr) {
|
| 381 | 378 |
case R_STAT: |
| 382 | 379 |
/* Attach an MDIO/PHY abstraction. */ |
| ... | ... | |
| 428 | 425 |
{
|
| 429 | 426 |
struct fs_eth *eth = opaque; |
| 430 | 427 |
|
| 431 |
/* Make addr relative to this instances base. */ |
|
| 432 |
addr -= eth->base; |
|
| 433 | 428 |
switch (addr) |
| 434 | 429 |
{
|
| 435 | 430 |
case RW_MA0_LO: |
| ... | ... | |
| 589 | 584 |
dma[1].client.pull = NULL; |
| 590 | 585 |
|
| 591 | 586 |
eth->env = env; |
| 592 |
eth->base = base; |
|
| 593 | 587 |
eth->irq = irq; |
| 594 | 588 |
eth->dma_out = dma; |
| 595 | 589 |
eth->dma_in = dma + 1; |
| b/hw/etraxfs_pic.c | ||
|---|---|---|
| 31 | 31 |
struct fs_pic_state_t |
| 32 | 32 |
{
|
| 33 | 33 |
CPUState *env; |
| 34 |
target_phys_addr_t base; |
|
| 35 | 34 |
|
| 36 | 35 |
uint32_t rw_mask; |
| 37 | 36 |
/* Active interrupt lines. */ |
| ... | ... | |
| 56 | 55 |
struct fs_pic_state_t *fs = opaque; |
| 57 | 56 |
uint32_t rval; |
| 58 | 57 |
|
| 59 |
/* Transform this to a relative addr. */ |
|
| 60 |
addr -= fs->base; |
|
| 61 | 58 |
switch (addr) |
| 62 | 59 |
{
|
| 63 | 60 |
case 0x0: |
| ... | ... | |
| 99 | 96 |
{
|
| 100 | 97 |
struct fs_pic_state_t *fs = opaque; |
| 101 | 98 |
D(printf("%s addr=%x val=%x\n", __func__, addr, value));
|
| 102 |
/* Transform this to a relative addr. */ |
|
| 103 |
addr -= fs->base; |
|
| 104 | 99 |
switch (addr) |
| 105 | 100 |
{
|
| 106 | 101 |
case 0x0: |
| ... | ... | |
| 233 | 228 |
|
| 234 | 229 |
intr_vect_regs = cpu_register_io_memory(0, pic_read, pic_write, fs); |
| 235 | 230 |
cpu_register_physical_memory(base, 0x14, intr_vect_regs); |
| 236 |
fs->base = base; |
|
| 237 | 231 |
|
| 238 | 232 |
return pic; |
| 239 | 233 |
err: |
| b/hw/etraxfs_ser.c | ||
|---|---|---|
| 50 | 50 |
CharDriverState *chr; |
| 51 | 51 |
qemu_irq *irq; |
| 52 | 52 |
|
| 53 |
target_phys_addr_t base; |
|
| 54 |
|
|
| 55 | 53 |
int pending_tx; |
| 56 | 54 |
|
| 57 | 55 |
/* Control registers. */ |
| ... | ... | |
| 240 | 238 |
|
| 241 | 239 |
s->env = env; |
| 242 | 240 |
s->irq = irq; |
| 243 |
s->base = base; |
|
| 244 |
|
|
| 245 | 241 |
s->chr = chr; |
| 246 | 242 |
|
| 247 | 243 |
/* transmitter begins ready and idle. */ |
| b/hw/etraxfs_timer.c | ||
|---|---|---|
| 47 | 47 |
CPUState *env; |
| 48 | 48 |
qemu_irq *irq; |
| 49 | 49 |
qemu_irq *nmi; |
| 50 |
target_phys_addr_t base; |
|
| 51 | 50 |
|
| 52 | 51 |
QEMUBH *bh_t0; |
| 53 | 52 |
QEMUBH *bh_t1; |
| ... | ... | |
| 90 | 89 |
struct fs_timer_t *t = opaque; |
| 91 | 90 |
uint32_t r = 0; |
| 92 | 91 |
|
| 93 |
/* Make addr relative to this instances base. */ |
|
| 94 |
addr -= t->base; |
|
| 95 | 92 |
switch (addr) {
|
| 96 | 93 |
case R_TMR0_DATA: |
| 97 | 94 |
break; |
| ... | ... | |
| 273 | 270 |
{
|
| 274 | 271 |
struct fs_timer_t *t = opaque; |
| 275 | 272 |
|
| 276 |
/* Make addr relative to this instances base. */ |
|
| 277 |
addr -= t->base; |
|
| 278 | 273 |
switch (addr) |
| 279 | 274 |
{
|
| 280 | 275 |
case RW_TMR0_DIV: |
| ... | ... | |
| 357 | 352 |
t->irq = irqs; |
| 358 | 353 |
t->nmi = nmi; |
| 359 | 354 |
t->env = env; |
| 360 |
t->base = base; |
|
| 361 | 355 |
|
| 362 | 356 |
timer_regs = cpu_register_io_memory(0, timer_read, timer_write, t); |
| 363 | 357 |
cpu_register_physical_memory (base, 0x5c, timer_regs); |
| b/hw/g364fb.c | ||
|---|---|---|
| 26 | 26 |
//#define DEBUG_G364 |
| 27 | 27 |
|
| 28 | 28 |
typedef struct G364State {
|
| 29 |
target_phys_addr_t vram_base; |
|
| 30 | 29 |
unsigned int vram_size; |
| 31 | 30 |
uint8_t *vram_buffer; |
| 32 | 31 |
uint32_t ctla; |
| ... | ... | |
| 300 | 299 |
static uint32_t g364fb_mem_readb(void *opaque, target_phys_addr_t addr) |
| 301 | 300 |
{
|
| 302 | 301 |
G364State *s = opaque; |
| 303 |
target_phys_addr_t relative_addr = addr - s->vram_base; |
|
| 304 | 302 |
|
| 305 |
return s->vram_buffer[relative_addr];
|
|
| 303 |
return s->vram_buffer[addr]; |
|
| 306 | 304 |
} |
| 307 | 305 |
|
| 308 | 306 |
static uint32_t g364fb_mem_readw(void *opaque, target_phys_addr_t addr) |
| ... | ... | |
| 326 | 324 |
static void g364fb_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 327 | 325 |
{
|
| 328 | 326 |
G364State *s = opaque; |
| 329 |
target_phys_addr_t relative_addr = addr - s->vram_base; |
|
| 330 | 327 |
|
| 331 |
s->vram_buffer[relative_addr] = val;
|
|
| 328 |
s->vram_buffer[addr] = val; |
|
| 332 | 329 |
} |
| 333 | 330 |
|
| 334 | 331 |
static void g364fb_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
| ... | ... | |
| 375 | 372 |
g364fb_reset(s); |
| 376 | 373 |
|
| 377 | 374 |
s->ds = ds; |
| 378 |
s->vram_base = vram_base; |
|
| 379 | 375 |
|
| 380 | 376 |
s->console = graphic_console_init(ds, g364fb_update_display, |
| 381 | 377 |
g364fb_invalidate_display, |
| 382 | 378 |
g364fb_screen_dump, NULL, s); |
| 383 | 379 |
|
| 384 | 380 |
io_vram = cpu_register_io_memory(0, g364fb_mem_read, g364fb_mem_write, s); |
| 385 |
cpu_register_physical_memory(s->vram_base, vram_size, io_vram);
|
|
| 381 |
cpu_register_physical_memory(vram_base, vram_size, io_vram); |
|
| 386 | 382 |
|
| 387 | 383 |
io_ctrl = cpu_register_io_memory(0, g364fb_ctrl_read, g364fb_ctrl_write, s); |
| 388 | 384 |
cpu_register_physical_memory(ctrl_base, 0x10000, io_ctrl); |
| b/hw/integratorcp.c | ||
|---|---|---|
| 38 | 38 |
static uint32_t integratorcm_read(void *opaque, target_phys_addr_t offset) |
| 39 | 39 |
{
|
| 40 | 40 |
integratorcm_state *s = (integratorcm_state *)opaque; |
| 41 |
offset -= 0x10000000; |
|
| 42 | 41 |
if (offset >= 0x100 && offset < 0x200) {
|
| 43 | 42 |
/* CM_SPD */ |
| 44 | 43 |
if (offset >= 0x180) |
| ... | ... | |
| 141 | 140 |
uint32_t value) |
| 142 | 141 |
{
|
| 143 | 142 |
integratorcm_state *s = (integratorcm_state *)opaque; |
| 144 |
offset -= 0x10000000; |
|
| 145 | 143 |
switch (offset >> 2) {
|
| 146 | 144 |
case 2: /* CM_OSC */ |
| 147 | 145 |
if (s->cm_lock == 0xa05f) |
| ... | ... | |
| 268 | 266 |
|
| 269 | 267 |
typedef struct icp_pic_state |
| 270 | 268 |
{
|
| 271 |
uint32_t base; |
|
| 272 | 269 |
uint32_t level; |
| 273 | 270 |
uint32_t irq_enabled; |
| 274 | 271 |
uint32_t fiq_enabled; |
| ... | ... | |
| 300 | 297 |
{
|
| 301 | 298 |
icp_pic_state *s = (icp_pic_state *)opaque; |
| 302 | 299 |
|
| 303 |
offset -= s->base; |
|
| 304 | 300 |
switch (offset >> 2) {
|
| 305 | 301 |
case 0: /* IRQ_STATUS */ |
| 306 | 302 |
return s->level & s->irq_enabled; |
| ... | ... | |
| 329 | 325 |
uint32_t value) |
| 330 | 326 |
{
|
| 331 | 327 |
icp_pic_state *s = (icp_pic_state *)opaque; |
| 332 |
offset -= s->base; |
|
| 333 | 328 |
|
| 334 | 329 |
switch (offset >> 2) {
|
| 335 | 330 |
case 2: /* IRQ_ENABLESET */ |
| ... | ... | |
| 386 | 381 |
if (!s) |
| 387 | 382 |
return NULL; |
| 388 | 383 |
qi = qemu_allocate_irqs(icp_pic_set_irq, s, 32); |
| 389 |
s->base = base; |
|
| 390 | 384 |
s->parent_irq = parent_irq; |
| 391 | 385 |
s->parent_fiq = parent_fiq; |
| 392 | 386 |
iomemtype = cpu_register_io_memory(0, icp_pic_readfn, |
| ... | ... | |
| 397 | 391 |
} |
| 398 | 392 |
|
| 399 | 393 |
/* CP control registers. */ |
| 400 |
typedef struct {
|
|
| 401 |
uint32_t base; |
|
| 402 |
} icp_control_state; |
|
| 403 |
|
|
| 404 | 394 |
static uint32_t icp_control_read(void *opaque, target_phys_addr_t offset) |
| 405 | 395 |
{
|
| 406 |
icp_control_state *s = (icp_control_state *)opaque; |
|
| 407 |
offset -= s->base; |
|
| 408 | 396 |
switch (offset >> 2) {
|
| 409 | 397 |
case 0: /* CP_IDFIELD */ |
| 410 | 398 |
return 0x41034003; |
| ... | ... | |
| 424 | 412 |
static void icp_control_write(void *opaque, target_phys_addr_t offset, |
| 425 | 413 |
uint32_t value) |
| 426 | 414 |
{
|
| 427 |
icp_control_state *s = (icp_control_state *)opaque; |
|
| 428 |
offset -= s->base; |
|
| 429 | 415 |
switch (offset >> 2) {
|
| 430 | 416 |
case 1: /* CP_FLASHPROG */ |
| 431 | 417 |
case 2: /* CP_INTREG */ |
| ... | ... | |
| 452 | 438 |
static void icp_control_init(uint32_t base) |
| 453 | 439 |
{
|
| 454 | 440 |
int iomemtype; |
| 455 |
icp_control_state *s; |
|
| 456 | 441 |
|
| 457 |
s = (icp_control_state *)qemu_mallocz(sizeof(icp_control_state)); |
|
| 458 | 442 |
iomemtype = cpu_register_io_memory(0, icp_control_readfn, |
| 459 |
icp_control_writefn, s);
|
|
| 443 |
icp_control_writefn, NULL);
|
|
| 460 | 444 |
cpu_register_physical_memory(base, 0x00800000, iomemtype); |
| 461 |
s->base = base; |
|
| 462 | 445 |
/* ??? Save/restore. */ |
| 463 | 446 |
} |
| 464 | 447 |
|
| b/hw/iommu.c | ||
|---|---|---|
| 114 | 114 |
#define PAGE_MASK (PAGE_SIZE - 1) |
| 115 | 115 |
|
| 116 | 116 |
typedef struct IOMMUState {
|
| 117 |
target_phys_addr_t addr; |
|
| 118 | 117 |
uint32_t regs[IOMMU_NREGS]; |
| 119 | 118 |
target_phys_addr_t iostart; |
| 120 | 119 |
uint32_t version; |
| ... | ... | |
| 127 | 126 |
target_phys_addr_t saddr; |
| 128 | 127 |
uint32_t ret; |
| 129 | 128 |
|
| 130 |
saddr = (addr - s->addr) >> 2;
|
|
| 129 |
saddr = addr >> 2;
|
|
| 131 | 130 |
switch (saddr) {
|
| 132 | 131 |
default: |
| 133 | 132 |
ret = s->regs[saddr]; |
| ... | ... | |
| 148 | 147 |
IOMMUState *s = opaque; |
| 149 | 148 |
target_phys_addr_t saddr; |
| 150 | 149 |
|
| 151 |
saddr = (addr - s->addr) >> 2;
|
|
| 150 |
saddr = addr >> 2;
|
|
| 152 | 151 |
DPRINTF("write reg[%d] = %x\n", (int)saddr, val);
|
| 153 | 152 |
switch (saddr) {
|
| 154 | 153 |
case IOMMU_CTRL: |
| ... | ... | |
| 358 | 357 |
if (!s) |
| 359 | 358 |
return NULL; |
| 360 | 359 |
|
| 361 |
s->addr = addr; |
|
| 362 | 360 |
s->version = version; |
| 363 | 361 |
s->irq = irq; |
| 364 | 362 |
|
| b/hw/jazz_led.c | ||
|---|---|---|
| 34 | 34 |
} screen_state_t; |
| 35 | 35 |
|
| 36 | 36 |
typedef struct LedState {
|
| 37 |
target_phys_addr_t base; |
|
| 38 | 37 |
uint8_t segments; |
| 39 | 38 |
DisplayState *ds; |
| 40 | 39 |
QEMUConsole *console; |
| ... | ... | |
| 44 | 43 |
static uint32_t led_readb(void *opaque, target_phys_addr_t addr) |
| 45 | 44 |
{
|
| 46 | 45 |
LedState *s = opaque; |
| 47 |
int relative_addr = addr - s->base; |
|
| 48 | 46 |
uint32_t val; |
| 49 | 47 |
|
| 50 |
switch (relative_addr) {
|
|
| 48 |
switch (addr) {
|
|
| 51 | 49 |
case 0: |
| 52 | 50 |
val = s->segments; |
| 53 | 51 |
break; |
| ... | ... | |
| 94 | 92 |
static void led_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 95 | 93 |
{
|
| 96 | 94 |
LedState *s = opaque; |
| 97 |
int relative_addr = addr - s->base; |
|
| 98 | 95 |
|
| 99 |
switch (relative_addr) {
|
|
| 96 |
switch (addr) {
|
|
| 100 | 97 |
case 0: |
| 101 | 98 |
s->segments = val; |
| 102 | 99 |
s->state |= REDRAW_SEGMENTS; |
| ... | ... | |
| 311 | 308 |
if (!s) |
| 312 | 309 |
return; |
| 313 | 310 |
|
| 314 |
s->base = base; |
|
| 315 | 311 |
s->ds = ds; |
| 316 | 312 |
s->state = REDRAW_SEGMENTS | REDRAW_BACKGROUND; |
| 317 | 313 |
|
| 318 | 314 |
io = cpu_register_io_memory(0, led_read, led_write, s); |
| 319 |
cpu_register_physical_memory(s->base, 1, io);
|
|
| 315 |
cpu_register_physical_memory(base, 1, io); |
|
| 320 | 316 |
|
| 321 | 317 |
s->console = graphic_console_init(ds, jazz_led_update_display, |
| 322 | 318 |
jazz_led_invalidate_display, |
| b/hw/m48t59.c | ||
|---|---|---|
| 46 | 46 |
/* Hardware parameters */ |
| 47 | 47 |
qemu_irq IRQ; |
| 48 | 48 |
int mem_index; |
| 49 |
target_phys_addr_t mem_base; |
|
| 50 | 49 |
uint32_t io_base; |
| 51 | 50 |
uint16_t size; |
| 52 | 51 |
/* RTC management */ |
| ... | ... | |
| 514 | 513 |
{
|
| 515 | 514 |
m48t59_t *NVRAM = opaque; |
| 516 | 515 |
|
| 517 |
addr -= NVRAM->mem_base; |
|
| 518 | 516 |
m48t59_write(NVRAM, addr, value & 0xff); |
| 519 | 517 |
} |
| 520 | 518 |
|
| ... | ... | |
| 522 | 520 |
{
|
| 523 | 521 |
m48t59_t *NVRAM = opaque; |
| 524 | 522 |
|
| 525 |
addr -= NVRAM->mem_base; |
|
| 526 | 523 |
m48t59_write(NVRAM, addr, (value >> 8) & 0xff); |
| 527 | 524 |
m48t59_write(NVRAM, addr + 1, value & 0xff); |
| 528 | 525 |
} |
| ... | ... | |
| 531 | 528 |
{
|
| 532 | 529 |
m48t59_t *NVRAM = opaque; |
| 533 | 530 |
|
| 534 |
addr -= NVRAM->mem_base; |
|
| 535 | 531 |
m48t59_write(NVRAM, addr, (value >> 24) & 0xff); |
| 536 | 532 |
m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff); |
| 537 | 533 |
m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff); |
| ... | ... | |
| 543 | 539 |
m48t59_t *NVRAM = opaque; |
| 544 | 540 |
uint32_t retval; |
| 545 | 541 |
|
| 546 |
addr -= NVRAM->mem_base; |
|
| 547 | 542 |
retval = m48t59_read(NVRAM, addr); |
| 548 | 543 |
return retval; |
| 549 | 544 |
} |
| ... | ... | |
| 553 | 548 |
m48t59_t *NVRAM = opaque; |
| 554 | 549 |
uint32_t retval; |
| 555 | 550 |
|
| 556 |
addr -= NVRAM->mem_base; |
|
| 557 | 551 |
retval = m48t59_read(NVRAM, addr) << 8; |
| 558 | 552 |
retval |= m48t59_read(NVRAM, addr + 1); |
| 559 | 553 |
return retval; |
| ... | ... | |
| 564 | 558 |
m48t59_t *NVRAM = opaque; |
| 565 | 559 |
uint32_t retval; |
| 566 | 560 |
|
| 567 |
addr -= NVRAM->mem_base; |
|
| 568 | 561 |
retval = m48t59_read(NVRAM, addr) << 24; |
| 569 | 562 |
retval |= m48t59_read(NVRAM, addr + 1) << 16; |
| 570 | 563 |
retval |= m48t59_read(NVRAM, addr + 2) << 8; |
| ... | ... | |
| 636 | 629 |
} |
| 637 | 630 |
s->IRQ = IRQ; |
| 638 | 631 |
s->size = size; |
| 639 |
s->mem_base = mem_base; |
|
| 640 | 632 |
s->io_base = io_base; |
| 641 | 633 |
s->addr = 0; |
| 642 | 634 |
s->type = type; |
| b/hw/mac_nvram.c | ||
|---|---|---|
| 26 | 26 |
#include "ppc_mac.h" |
| 27 | 27 |
|
| 28 | 28 |
struct MacIONVRAMState {
|
| 29 |
target_phys_addr_t mem_base; |
|
| 30 | 29 |
target_phys_addr_t size; |
| 31 | 30 |
int mem_index; |
| 32 | 31 |
uint8_t data[0x2000]; |
| ... | ... | |
| 62 | 61 |
{
|
| 63 | 62 |
MacIONVRAMState *s = opaque; |
| 64 | 63 |
|
| 65 |
addr -= s->mem_base; |
|
| 66 | 64 |
addr = (addr >> 4) & 0x1fff; |
| 67 | 65 |
s->data[addr] = value; |
| 68 | 66 |
// printf("macio_nvram_writeb %04x = %02x\n", addr, value);
|
| ... | ... | |
| 73 | 71 |
MacIONVRAMState *s = opaque; |
| 74 | 72 |
uint32_t value; |
| 75 | 73 |
|
| 76 |
addr -= s->mem_base; |
|
| 77 | 74 |
addr = (addr >> 4) & 0x1fff; |
| 78 | 75 |
value = s->data[addr]; |
| 79 | 76 |
// printf("macio_nvram_readb %04x = %02x\n", addr, value);
|
| ... | ... | |
| 112 | 109 |
MacIONVRAMState *s; |
| 113 | 110 |
|
| 114 | 111 |
s = opaque; |
| 115 |
s->mem_base = mem_base; |
|
| 116 | 112 |
cpu_register_physical_memory(mem_base, s->size, s->mem_index); |
| 117 | 113 |
} |
| 118 | 114 |
|
| b/hw/mc146818rtc.c | ||
|---|---|---|
| 59 | 59 |
uint8_t cmos_index; |
| 60 | 60 |
struct tm current_tm; |
| 61 | 61 |
qemu_irq irq; |
| 62 |
target_phys_addr_t base; |
|
| 63 | 62 |
int it_shift; |
| 64 | 63 |
/* periodic timer */ |
| 65 | 64 |
QEMUTimer *periodic_timer; |
| ... | ... | |
| 492 | 491 |
{
|
| 493 | 492 |
RTCState *s = opaque; |
| 494 | 493 |
|
| 495 |
return cmos_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF;
|
|
| 494 |
return cmos_ioport_read(s, addr >> s->it_shift) & 0xFF;
|
|
| 496 | 495 |
} |
| 497 | 496 |
|
| 498 | 497 |
static void cmos_mm_writeb (void *opaque, |
| ... | ... | |
| 500 | 499 |
{
|
| 501 | 500 |
RTCState *s = opaque; |
| 502 | 501 |
|
| 503 |
cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
|
|
| 502 |
cmos_ioport_write(s, addr >> s->it_shift, value & 0xFF);
|
|
| 504 | 503 |
} |
| 505 | 504 |
|
| 506 | 505 |
static uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr) |
| ... | ... | |
| 508 | 507 |
RTCState *s = opaque; |
| 509 | 508 |
uint32_t val; |
| 510 | 509 |
|
| 511 |
val = cmos_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
|
|
| 510 |
val = cmos_ioport_read(s, addr >> s->it_shift) & 0xFFFF;
|
|
| 512 | 511 |
#ifdef TARGET_WORDS_BIGENDIAN |
| 513 | 512 |
val = bswap16(val); |
| 514 | 513 |
#endif |
| ... | ... | |
| 522 | 521 |
#ifdef TARGET_WORDS_BIGENDIAN |
| 523 | 522 |
value = bswap16(value); |
| 524 | 523 |
#endif |
| 525 |
cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
|
|
| 524 |
cmos_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
|
|
| 526 | 525 |
} |
| 527 | 526 |
|
| 528 | 527 |
static uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr) |
| ... | ... | |
| 530 | 529 |
RTCState *s = opaque; |
| 531 | 530 |
uint32_t val; |
| 532 | 531 |
|
| 533 |
val = cmos_ioport_read(s, (addr - s->base) >> s->it_shift);
|
|
| 532 |
val = cmos_ioport_read(s, addr >> s->it_shift);
|
|
| 534 | 533 |
#ifdef TARGET_WORDS_BIGENDIAN |
| 535 | 534 |
val = bswap32(val); |
| 536 | 535 |
#endif |
| ... | ... | |
| 544 | 543 |
#ifdef TARGET_WORDS_BIGENDIAN |
| 545 | 544 |
value = bswap32(value); |
| 546 | 545 |
#endif |
| 547 |
cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value);
|
|
| 546 |
cmos_ioport_write(s, addr >> s->it_shift, value);
|
|
| 548 | 547 |
} |
| 549 | 548 |
|
| 550 | 549 |
static CPUReadMemoryFunc *rtc_mm_read[] = {
|
| ... | ... | |
| 573 | 572 |
s->cmos_data[RTC_REG_B] = 0x02; |
| 574 | 573 |
s->cmos_data[RTC_REG_C] = 0x00; |
| 575 | 574 |
s->cmos_data[RTC_REG_D] = 0x80; |
| 576 |
s->base = base; |
|
| 577 | 575 |
|
| 578 | 576 |
rtc_set_date_from_host(s); |
| 579 | 577 |
|
| b/hw/mcf5208.c | ||
|---|---|---|
| 40 | 40 |
qemu_irq_lower(s->irq); |
| 41 | 41 |
} |
| 42 | 42 |
|
| 43 |
static void m5208_timer_write(m5208_timer_state *s, int offset,
|
|
| 43 |
static void m5208_timer_write(void *opaque, target_phys_addr_t offset,
|
|
| 44 | 44 |
uint32_t value) |
| 45 | 45 |
{
|
| 46 |
m5208_timer_state *s = (m5208_timer_state *)opaque; |
|
| 46 | 47 |
int prescale; |
| 47 | 48 |
int limit; |
| 48 | 49 |
switch (offset) {
|
| ... | ... | |
| 88 | 89 |
case 4: |
| 89 | 90 |
break; |
| 90 | 91 |
default: |
| 91 |
/* Should never happen. */ |
|
| 92 |
abort(); |
|
| 92 |
cpu_abort(cpu_single_env, "m5208_timer_write: Bad offset 0x%x\n", |
|
| 93 |
(int)offset); |
|
| 94 |
break; |
|
| 93 | 95 |
} |
| 94 | 96 |
m5208_timer_update(s); |
| 95 | 97 |
} |
| ... | ... | |
| 101 | 103 |
m5208_timer_update(s); |
| 102 | 104 |
} |
| 103 | 105 |
|
| 104 |
typedef struct {
|
|
| 105 |
m5208_timer_state timer[2]; |
|
| 106 |
} m5208_sys_state; |
|
| 106 |
static uint32_t m5208_timer_read(void *opaque, target_phys_addr_t addr) |
|
| 107 |
{
|
|
| 108 |
m5208_timer_state *s = (m5208_timer_state *)opaque; |
|
| 109 |
switch (addr) {
|
|
| 110 |
case 0: |
|
| 111 |
return s->pcsr; |
|
| 112 |
case 2: |
|
| 113 |
return s->pmr; |
|
| 114 |
case 4: |
|
| 115 |
return ptimer_get_count(s->timer); |
|
| 116 |
default: |
|
| 117 |
cpu_abort(cpu_single_env, "m5208_timer_read: Bad offset 0x%x\n", |
|
| 118 |
(int)addr); |
|
| 119 |
return 0; |
|
| 120 |
} |
|
| 121 |
} |
|
| 122 |
|
|
| 123 |
static CPUReadMemoryFunc *m5208_timer_readfn[] = {
|
|
| 124 |
m5208_timer_read, |
|
| 125 |
m5208_timer_read, |
|
| 126 |
m5208_timer_read |
|
| 127 |
}; |
|
| 128 |
|
|
| 129 |
static CPUWriteMemoryFunc *m5208_timer_writefn[] = {
|
|
| 130 |
m5208_timer_write, |
|
| 131 |
m5208_timer_write, |
|
| 132 |
m5208_timer_write |
|
| 133 |
}; |
|
| 107 | 134 |
|
| 108 | 135 |
static uint32_t m5208_sys_read(void *opaque, target_phys_addr_t addr) |
| 109 | 136 |
{
|
| 110 |
m5208_sys_state *s = (m5208_sys_state *)opaque; |
|
| 111 | 137 |
switch (addr) {
|
| 112 |
/* PIT0 */ |
|
| 113 |
case 0xfc080000: |
|
| 114 |
return s->timer[0].pcsr; |
|
| 115 |
case 0xfc080002: |
|
| 116 |
return s->timer[0].pmr; |
|
| 117 |
case 0xfc080004: |
|
| 118 |
return ptimer_get_count(s->timer[0].timer); |
|
| 119 |
/* PIT1 */ |
|
| 120 |
case 0xfc084000: |
|
| 121 |
return s->timer[1].pcsr; |
|
| 122 |
case 0xfc084002: |
|
| 123 |
return s->timer[1].pmr; |
|
| 124 |
case 0xfc084004: |
|
| 125 |
return ptimer_get_count(s->timer[1].timer); |
|
| 126 |
|
|
| 127 |
/* SDRAM Controller. */ |
|
| 128 |
case 0xfc0a8110: /* SDCS0 */ |
|
| 138 |
case 0x110: /* SDCS0 */ |
|
| 129 | 139 |
{
|
| 130 | 140 |
int n; |
| 131 | 141 |
for (n = 0; n < 32; n++) {
|
| ... | ... | |
| 134 | 144 |
} |
| 135 | 145 |
return (n - 1) | 0x40000000; |
| 136 | 146 |
} |
| 137 |
case 0xfc0a8114: /* SDCS1 */
|
|
| 147 |
case 0x114: /* SDCS1 */ |
|
| 138 | 148 |
return 0; |
| 139 | 149 |
|
| 140 | 150 |
default: |
| ... | ... | |
| 147 | 157 |
static void m5208_sys_write(void *opaque, target_phys_addr_t addr, |
| 148 | 158 |
uint32_t value) |
| 149 | 159 |
{
|
| 150 |
m5208_sys_state *s = (m5208_sys_state *)opaque; |
|
| 151 |
switch (addr) {
|
|
| 152 |
/* PIT0 */ |
|
| 153 |
case 0xfc080000: |
|
| 154 |
case 0xfc080002: |
|
| 155 |
case 0xfc080004: |
|
| 156 |
m5208_timer_write(&s->timer[0], addr & 0xf, value); |
|
| 157 |
return; |
|
| 158 |
/* PIT1 */ |
|
| 159 |
case 0xfc084000: |
|
| 160 |
case 0xfc084002: |
|
| 161 |
case 0xfc084004: |
|
| 162 |
m5208_timer_write(&s->timer[1], addr & 0xf, value); |
|
| 163 |
return; |
|
| 164 |
default: |
|
| 165 |
cpu_abort(cpu_single_env, "m5208_sys_write: Bad offset 0x%x\n", |
|
| 166 |
(int)addr); |
|
| 167 |
break; |
|
| 168 |
} |
|
| 160 |
cpu_abort(cpu_single_env, "m5208_sys_write: Bad offset 0x%x\n", |
|
| 161 |
(int)addr); |
|
| 169 | 162 |
} |
| 170 | 163 |
|
| 171 | 164 |
static CPUReadMemoryFunc *m5208_sys_readfn[] = {
|
| ... | ... | |
| 183 | 176 |
static void mcf5208_sys_init(qemu_irq *pic) |
| 184 | 177 |
{
|
| 185 | 178 |
int iomemtype; |
| 186 |
m5208_sys_state *s;
|
|
| 179 |
m5208_timer_state *s;
|
|
| 187 | 180 |
QEMUBH *bh; |
| 188 | 181 |
int i; |
| 189 | 182 |
|
| 190 |
s = (m5208_sys_state *)qemu_mallocz(sizeof(m5208_sys_state)); |
|
| 191 | 183 |
iomemtype = cpu_register_io_memory(0, m5208_sys_readfn, |
| 192 |
m5208_sys_writefn, s);
|
|
| 184 |
m5208_sys_writefn, NULL);
|
|
| 193 | 185 |
/* SDRAMC. */ |
| 194 | 186 |
cpu_register_physical_memory(0xfc0a8000, 0x00004000, iomemtype); |
| 195 | 187 |
/* Timers. */ |
| 196 | 188 |
for (i = 0; i < 2; i++) {
|
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