Revision 8da3ff18 hw/arm_gic.c
| b/hw/arm_gic.c | ||
|---|---|---|
| 23 | 23 |
#ifdef NVIC |
| 24 | 24 |
static const uint8_t gic_id[] = |
| 25 | 25 |
{ 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1 };
|
| 26 |
#define GIC_DIST_OFFSET 0 |
|
| 27 | 26 |
/* The NVIC has 16 internal vectors. However these are not exposed |
| 28 | 27 |
through the normal GIC interface. */ |
| 29 | 28 |
#define GIC_BASE_IRQ 32 |
| 30 | 29 |
#else |
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static const uint8_t gic_id[] = |
| 32 | 31 |
{ 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
|
| 33 |
#define GIC_DIST_OFFSET 0x1000 |
|
| 34 | 32 |
#define GIC_BASE_IRQ 0 |
| 35 | 33 |
#endif |
| 36 | 34 |
|
| ... | ... | |
| 76 | 74 |
|
| 77 | 75 |
typedef struct gic_state |
| 78 | 76 |
{
|
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uint32_t base; |
|
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qemu_irq parent_irq[NCPU]; |
| 81 | 78 |
int enabled; |
| 82 | 79 |
int cpu_enabled[NCPU]; |
| ... | ... | |
| 252 | 249 |
|
| 253 | 250 |
cpu = gic_get_current_cpu(); |
| 254 | 251 |
cm = 1 << cpu; |
| 255 |
offset -= s->base + GIC_DIST_OFFSET; |
|
| 256 | 252 |
if (offset < 0x100) {
|
| 257 | 253 |
#ifndef NVIC |
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if (offset == 0) |
| ... | ... | |
| 365 | 361 |
#ifdef NVIC |
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gic_state *s = (gic_state *)opaque; |
| 367 | 363 |
uint32_t addr; |
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addr = offset - s->base;
|
|
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addr = offset; |
|
| 369 | 365 |
if (addr < 0x100 || addr > 0xd00) |
| 370 | 366 |
return nvic_readl(s->nvic, addr); |
| 371 | 367 |
#endif |
| ... | ... | |
| 383 | 379 |
int cpu; |
| 384 | 380 |
|
| 385 | 381 |
cpu = gic_get_current_cpu(); |
| 386 |
offset -= s->base + GIC_DIST_OFFSET; |
|
| 387 | 382 |
if (offset < 0x100) {
|
| 388 | 383 |
#ifdef NVIC |
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goto bad_reg; |
| ... | ... | |
| 526 | 521 |
gic_state *s = (gic_state *)opaque; |
| 527 | 522 |
#ifdef NVIC |
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uint32_t addr; |
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addr = offset - s->base;
|
|
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addr = offset; |
|
| 530 | 525 |
if (addr < 0x100 || (addr > 0xd00 && addr != 0xf00)) {
|
| 531 | 526 |
nvic_writel(s->nvic, addr, value); |
| 532 | 527 |
return; |
| 533 | 528 |
} |
| 534 | 529 |
#endif |
| 535 |
if (offset - s->base == GIC_DIST_OFFSET + 0xf00) {
|
|
| 530 |
if (offset == 0xf00) {
|
|
| 536 | 531 |
int cpu; |
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int irq; |
| 538 | 533 |
int mask; |
| ... | ... | |
| 723 | 718 |
return 0; |
| 724 | 719 |
} |
| 725 | 720 |
|
| 726 |
static gic_state *gic_init(uint32_t base, qemu_irq *parent_irq) |
|
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static gic_state *gic_init(uint32_t dist_base, qemu_irq *parent_irq)
|
|
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{
|
| 728 | 723 |
gic_state *s; |
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int iomemtype; |
| ... | ... | |
| 738 | 733 |
} |
| 739 | 734 |
iomemtype = cpu_register_io_memory(0, gic_dist_readfn, |
| 740 | 735 |
gic_dist_writefn, s); |
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cpu_register_physical_memory(base + GIC_DIST_OFFSET, 0x00001000,
|
|
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cpu_register_physical_memory(dist_base, 0x00001000,
|
|
| 742 | 737 |
iomemtype); |
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s->base = base; |
|
| 744 | 738 |
gic_reset(s); |
| 745 | 739 |
register_savevm("arm_gic", -1, 1, gic_save, gic_load, s);
|
| 746 | 740 |
return s; |
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