Revision 8da3ff18 hw/e1000.c
b/hw/e1000.c | ||
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76 | 76 |
PCIDevice dev; |
77 | 77 |
VLANClientState *vc; |
78 | 78 |
NICInfo *nd; |
79 |
uint32_t mmio_base; |
|
80 | 79 |
int mmio_index; |
81 | 80 |
|
82 | 81 |
uint32_t mac_reg[0x8000]; |
... | ... | |
786 | 785 |
e1000_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
787 | 786 |
{ |
788 | 787 |
E1000State *s = opaque; |
789 |
unsigned int index = ((addr - s->mmio_base) & 0x1ffff) >> 2;
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|
788 |
unsigned int index = (addr & 0x1ffff) >> 2;
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|
790 | 789 |
|
791 | 790 |
#ifdef TARGET_WORDS_BIGENDIAN |
792 | 791 |
val = bswap32(val); |
... | ... | |
820 | 819 |
e1000_mmio_readl(void *opaque, target_phys_addr_t addr) |
821 | 820 |
{ |
822 | 821 |
E1000State *s = opaque; |
823 |
unsigned int index = ((addr - s->mmio_base) & 0x1ffff) >> 2;
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|
822 |
unsigned int index = (addr & 0x1ffff) >> 2;
|
|
824 | 823 |
|
825 | 824 |
if (index < NREADOPS && macreg_readops[index]) |
826 | 825 |
{ |
... | ... | |
870 | 869 |
int i, j; |
871 | 870 |
|
872 | 871 |
pci_device_save(&s->dev, f); |
873 |
qemu_put_be32s(f, &s->mmio_base);
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|
872 |
qemu_put_be32(f, 0);
|
|
874 | 873 |
qemu_put_be32s(f, &s->rxbuf_size); |
875 | 874 |
qemu_put_be32s(f, &s->rxbuf_min_shift); |
876 | 875 |
qemu_put_be32s(f, &s->eecd_state.val_in); |
... | ... | |
916 | 915 |
return ret; |
917 | 916 |
if (version_id == 1) |
918 | 917 |
qemu_get_sbe32s(f, &i); /* once some unused instance id */ |
919 |
qemu_get_be32s(f, &s->mmio_base);
|
|
918 |
qemu_get_be32(f); /* Ignored. Was mmio_base. */
|
|
920 | 919 |
qemu_get_be32s(f, &s->rxbuf_size); |
921 | 920 |
qemu_get_be32s(f, &s->rxbuf_min_shift); |
922 | 921 |
qemu_get_be32s(f, &s->eecd_state.val_in); |
... | ... | |
1005 | 1004 |
|
1006 | 1005 |
DBGOUT(MMIO, "e1000_mmio_map addr=0x%08x 0x%08x\n", addr, size); |
1007 | 1006 |
|
1008 |
d->mmio_base = addr; |
|
1009 | 1007 |
cpu_register_physical_memory(addr, PNPMMIO_SIZE, d->mmio_index); |
1010 | 1008 |
} |
1011 | 1009 |
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