Revision 8da3ff18 hw/etraxfs_timer.c
| b/hw/etraxfs_timer.c | ||
|---|---|---|
| 47 | 47 |
CPUState *env; |
| 48 | 48 |
qemu_irq *irq; |
| 49 | 49 |
qemu_irq *nmi; |
| 50 |
target_phys_addr_t base; |
|
| 51 | 50 |
|
| 52 | 51 |
QEMUBH *bh_t0; |
| 53 | 52 |
QEMUBH *bh_t1; |
| ... | ... | |
| 90 | 89 |
struct fs_timer_t *t = opaque; |
| 91 | 90 |
uint32_t r = 0; |
| 92 | 91 |
|
| 93 |
/* Make addr relative to this instances base. */ |
|
| 94 |
addr -= t->base; |
|
| 95 | 92 |
switch (addr) {
|
| 96 | 93 |
case R_TMR0_DATA: |
| 97 | 94 |
break; |
| ... | ... | |
| 273 | 270 |
{
|
| 274 | 271 |
struct fs_timer_t *t = opaque; |
| 275 | 272 |
|
| 276 |
/* Make addr relative to this instances base. */ |
|
| 277 |
addr -= t->base; |
|
| 278 | 273 |
switch (addr) |
| 279 | 274 |
{
|
| 280 | 275 |
case RW_TMR0_DIV: |
| ... | ... | |
| 357 | 352 |
t->irq = irqs; |
| 358 | 353 |
t->nmi = nmi; |
| 359 | 354 |
t->env = env; |
| 360 |
t->base = base; |
|
| 361 | 355 |
|
| 362 | 356 |
timer_regs = cpu_register_io_memory(0, timer_read, timer_write, t); |
| 363 | 357 |
cpu_register_physical_memory (base, 0x5c, timer_regs); |
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