Archipelago » qemu

    /* Hardware parameters */

    qemu_irq IRQ;

    int mem_index;

    uint32_t io_base;

    uint16_t size;

    /* RTC management */

{

    m48t59_t *NVRAM = opaque;

    m48t59_write(NVRAM, addr, value & 0xff);

}

{

    m48t59_t *NVRAM = opaque;

    m48t59_write(NVRAM, addr, (value >> 8) & 0xff);

    m48t59_write(NVRAM, addr + 1, value & 0xff);

}

{

    m48t59_t *NVRAM = opaque;

    m48t59_write(NVRAM, addr, (value >> 24) & 0xff);

    m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);

    m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff);

    m48t59_t *NVRAM = opaque;

    uint32_t retval;

    retval = m48t59_read(NVRAM, addr);

    return retval;

}

    m48t59_t *NVRAM = opaque;

    uint32_t retval;

    retval = m48t59_read(NVRAM, addr) << 8;

    retval |= m48t59_read(NVRAM, addr + 1);

    return retval;

    m48t59_t *NVRAM = opaque;

    uint32_t retval;

    retval = m48t59_read(NVRAM, addr) << 24;

    retval |= m48t59_read(NVRAM, addr + 1) << 16;

    retval |= m48t59_read(NVRAM, addr + 2) << 8;

    }

    s->IRQ = IRQ;

    s->size = size;

    s->io_base = io_base;

    s->addr = 0;

    s->type = type;