Revision 8da3ff18 hw/mcf5208.c
| b/hw/mcf5208.c | ||
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| 40 | 40 |
qemu_irq_lower(s->irq); |
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} |
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static void m5208_timer_write(m5208_timer_state *s, int offset,
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static void m5208_timer_write(void *opaque, target_phys_addr_t offset,
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uint32_t value) |
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{
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m5208_timer_state *s = (m5208_timer_state *)opaque; |
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int prescale; |
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int limit; |
| 48 | 49 |
switch (offset) {
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| ... | ... | |
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case 4: |
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break; |
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default: |
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/* Should never happen. */ |
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abort(); |
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cpu_abort(cpu_single_env, "m5208_timer_write: Bad offset 0x%x\n", |
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(int)offset); |
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break; |
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} |
| 94 | 96 |
m5208_timer_update(s); |
| 95 | 97 |
} |
| ... | ... | |
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m5208_timer_update(s); |
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} |
| 103 | 105 |
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typedef struct {
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m5208_timer_state timer[2]; |
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} m5208_sys_state; |
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static uint32_t m5208_timer_read(void *opaque, target_phys_addr_t addr) |
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{
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m5208_timer_state *s = (m5208_timer_state *)opaque; |
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switch (addr) {
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case 0: |
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return s->pcsr; |
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case 2: |
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return s->pmr; |
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case 4: |
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return ptimer_get_count(s->timer); |
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default: |
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cpu_abort(cpu_single_env, "m5208_timer_read: Bad offset 0x%x\n", |
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(int)addr); |
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return 0; |
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} |
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} |
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static CPUReadMemoryFunc *m5208_timer_readfn[] = {
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m5208_timer_read, |
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m5208_timer_read, |
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m5208_timer_read |
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}; |
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static CPUWriteMemoryFunc *m5208_timer_writefn[] = {
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m5208_timer_write, |
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m5208_timer_write, |
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m5208_timer_write |
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}; |
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static uint32_t m5208_sys_read(void *opaque, target_phys_addr_t addr) |
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{
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m5208_sys_state *s = (m5208_sys_state *)opaque; |
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switch (addr) {
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/* PIT0 */ |
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case 0xfc080000: |
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return s->timer[0].pcsr; |
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case 0xfc080002: |
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return s->timer[0].pmr; |
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case 0xfc080004: |
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return ptimer_get_count(s->timer[0].timer); |
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/* PIT1 */ |
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case 0xfc084000: |
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return s->timer[1].pcsr; |
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case 0xfc084002: |
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return s->timer[1].pmr; |
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case 0xfc084004: |
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return ptimer_get_count(s->timer[1].timer); |
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/* SDRAM Controller. */ |
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case 0xfc0a8110: /* SDCS0 */ |
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case 0x110: /* SDCS0 */ |
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{
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int n; |
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for (n = 0; n < 32; n++) {
|
| ... | ... | |
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} |
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return (n - 1) | 0x40000000; |
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} |
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case 0xfc0a8114: /* SDCS1 */
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case 0x114: /* SDCS1 */ |
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return 0; |
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default: |
| ... | ... | |
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static void m5208_sys_write(void *opaque, target_phys_addr_t addr, |
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uint32_t value) |
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{
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m5208_sys_state *s = (m5208_sys_state *)opaque; |
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switch (addr) {
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/* PIT0 */ |
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case 0xfc080000: |
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case 0xfc080002: |
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case 0xfc080004: |
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m5208_timer_write(&s->timer[0], addr & 0xf, value); |
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return; |
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/* PIT1 */ |
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case 0xfc084000: |
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case 0xfc084002: |
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case 0xfc084004: |
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m5208_timer_write(&s->timer[1], addr & 0xf, value); |
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return; |
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default: |
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cpu_abort(cpu_single_env, "m5208_sys_write: Bad offset 0x%x\n", |
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(int)addr); |
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break; |
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} |
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cpu_abort(cpu_single_env, "m5208_sys_write: Bad offset 0x%x\n", |
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(int)addr); |
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} |
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static CPUReadMemoryFunc *m5208_sys_readfn[] = {
|
| ... | ... | |
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static void mcf5208_sys_init(qemu_irq *pic) |
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{
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int iomemtype; |
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m5208_sys_state *s;
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m5208_timer_state *s;
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QEMUBH *bh; |
| 188 | 181 |
int i; |
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s = (m5208_sys_state *)qemu_mallocz(sizeof(m5208_sys_state)); |
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iomemtype = cpu_register_io_memory(0, m5208_sys_readfn, |
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m5208_sys_writefn, s);
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m5208_sys_writefn, NULL);
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/* SDRAMC. */ |
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cpu_register_physical_memory(0xfc0a8000, 0x00004000, iomemtype); |
| 195 | 187 |
/* Timers. */ |
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for (i = 0; i < 2; i++) {
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bh = qemu_bh_new(m5208_timer_trigger, &s->timer[i]); |
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s->timer[i].timer = ptimer_init(bh); |
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s = (m5208_timer_state *)qemu_mallocz(sizeof(m5208_timer_state)); |
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bh = qemu_bh_new(m5208_timer_trigger, s); |
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s->timer = ptimer_init(bh); |
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iomemtype = cpu_register_io_memory(0, m5208_timer_readfn, |
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m5208_timer_writefn, s); |
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cpu_register_physical_memory(0xfc080000 + 0x4000 * i, 0x00004000, |
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iomemtype); |
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s->timer[i].irq = pic[4 + i];
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s->irq = pic[4 + i]; |
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} |
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} |
| 204 | 199 |
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