Revision 8da3ff18 hw/omap1.c
| b/hw/omap1.c | ||
|---|---|---|
| 95 | 95 |
struct omap_intr_handler_s {
|
| 96 | 96 |
qemu_irq *pins; |
| 97 | 97 |
qemu_irq parent_intr[2]; |
| 98 |
target_phys_addr_t base; |
|
| 99 | 98 |
unsigned char nbanks; |
| 100 | 99 |
int level_only; |
| 101 | 100 |
|
| ... | ... | |
| 202 | 201 |
static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr) |
| 203 | 202 |
{
|
| 204 | 203 |
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
| 205 |
int i, offset = addr - s->base;
|
|
| 204 |
int i, offset = addr; |
|
| 206 | 205 |
int bank_no = offset >> 8; |
| 207 | 206 |
int line_no; |
| 208 | 207 |
struct omap_intr_handler_bank_s *bank = &s->bank[bank_no]; |
| ... | ... | |
| 280 | 279 |
uint32_t value) |
| 281 | 280 |
{
|
| 282 | 281 |
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
| 283 |
int i, offset = addr - s->base;
|
|
| 282 |
int i, offset = addr; |
|
| 284 | 283 |
int bank_no = offset >> 8; |
| 285 | 284 |
struct omap_intr_handler_bank_s *bank = &s->bank[bank_no]; |
| 286 | 285 |
offset &= 0xff; |
| ... | ... | |
| 420 | 419 |
|
| 421 | 420 |
s->parent_intr[0] = parent_irq; |
| 422 | 421 |
s->parent_intr[1] = parent_fiq; |
| 423 |
s->base = base; |
|
| 424 | 422 |
s->nbanks = nbanks; |
| 425 | 423 |
s->pins = qemu_allocate_irqs(omap_set_intr, s, nbanks * 32); |
| 426 | 424 |
if (pins) |
| ... | ... | |
| 430 | 428 |
|
| 431 | 429 |
iomemtype = cpu_register_io_memory(0, omap_inth_readfn, |
| 432 | 430 |
omap_inth_writefn, s); |
| 433 |
cpu_register_physical_memory(s->base, size, iomemtype);
|
|
| 431 |
cpu_register_physical_memory(base, size, iomemtype); |
|
| 434 | 432 |
|
| 435 | 433 |
return s; |
| 436 | 434 |
} |
| ... | ... | |
| 438 | 436 |
static uint32_t omap2_inth_read(void *opaque, target_phys_addr_t addr) |
| 439 | 437 |
{
|
| 440 | 438 |
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
| 441 |
int offset = addr - s->base;
|
|
| 439 |
int offset = addr; |
|
| 442 | 440 |
int bank_no, line_no; |
| 443 | 441 |
struct omap_intr_handler_bank_s *bank = 0; |
| 444 | 442 |
|
| ... | ... | |
| 516 | 514 |
uint32_t value) |
| 517 | 515 |
{
|
| 518 | 516 |
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
| 519 |
int offset = addr - s->base;
|
|
| 517 |
int offset = addr; |
|
| 520 | 518 |
int bank_no, line_no; |
| 521 | 519 |
struct omap_intr_handler_bank_s *bank = 0; |
| 522 | 520 |
|
| ... | ... | |
| 640 | 638 |
|
| 641 | 639 |
s->parent_intr[0] = parent_irq; |
| 642 | 640 |
s->parent_intr[1] = parent_fiq; |
| 643 |
s->base = base; |
|
| 644 | 641 |
s->nbanks = nbanks; |
| 645 | 642 |
s->level_only = 1; |
| 646 | 643 |
s->pins = qemu_allocate_irqs(omap_set_intr_noedge, s, nbanks * 32); |
| ... | ... | |
| 651 | 648 |
|
| 652 | 649 |
iomemtype = cpu_register_io_memory(0, omap2_inth_readfn, |
| 653 | 650 |
omap2_inth_writefn, s); |
| 654 |
cpu_register_physical_memory(s->base, size, iomemtype);
|
|
| 651 |
cpu_register_physical_memory(base, size, iomemtype); |
|
| 655 | 652 |
|
| 656 | 653 |
return s; |
| 657 | 654 |
} |
| ... | ... | |
| 660 | 657 |
struct omap_mpu_timer_s {
|
| 661 | 658 |
qemu_irq irq; |
| 662 | 659 |
omap_clk clk; |
| 663 |
target_phys_addr_t base; |
|
| 664 | 660 |
uint32_t val; |
| 665 | 661 |
int64_t time; |
| 666 | 662 |
QEMUTimer *timer; |
| ... | ... | |
| 757 | 753 |
static uint32_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr) |
| 758 | 754 |
{
|
| 759 | 755 |
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; |
| 760 |
int offset = addr - s->base; |
|
| 761 | 756 |
|
| 762 |
switch (offset) {
|
|
| 757 |
switch (addr) {
|
|
| 763 | 758 |
case 0x00: /* CNTL_TIMER */ |
| 764 | 759 |
return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st; |
| 765 | 760 |
|
| ... | ... | |
| 778 | 773 |
uint32_t value) |
| 779 | 774 |
{
|
| 780 | 775 |
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; |
| 781 |
int offset = addr - s->base; |
|
| 782 | 776 |
|
| 783 |
switch (offset) {
|
|
| 777 |
switch (addr) {
|
|
| 784 | 778 |
case 0x00: /* CNTL_TIMER */ |
| 785 | 779 |
omap_timer_sync(s); |
| 786 | 780 |
s->enable = (value >> 5) & 1; |
| ... | ... | |
| 836 | 830 |
|
| 837 | 831 |
s->irq = irq; |
| 838 | 832 |
s->clk = clk; |
| 839 |
s->base = base; |
|
| 840 | 833 |
s->timer = qemu_new_timer(vm_clock, omap_timer_tick, s); |
| 841 | 834 |
s->tick = qemu_bh_new(omap_timer_fire, s); |
| 842 | 835 |
omap_mpu_timer_reset(s); |
| ... | ... | |
| 844 | 837 |
|
| 845 | 838 |
iomemtype = cpu_register_io_memory(0, omap_mpu_timer_readfn, |
| 846 | 839 |
omap_mpu_timer_writefn, s); |
| 847 |
cpu_register_physical_memory(s->base, 0x100, iomemtype);
|
|
| 840 |
cpu_register_physical_memory(base, 0x100, iomemtype); |
|
| 848 | 841 |
|
| 849 | 842 |
return s; |
| 850 | 843 |
} |
| ... | ... | |
| 861 | 854 |
static uint32_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr) |
| 862 | 855 |
{
|
| 863 | 856 |
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; |
| 864 |
int offset = addr - s->timer.base; |
|
| 865 | 857 |
|
| 866 |
switch (offset) {
|
|
| 858 |
switch (addr) {
|
|
| 867 | 859 |
case 0x00: /* CNTL_TIMER */ |
| 868 | 860 |
return (s->timer.ptv << 9) | (s->timer.ar << 8) | |
| 869 | 861 |
(s->timer.st << 7) | (s->free << 1); |
| ... | ... | |
| 883 | 875 |
uint32_t value) |
| 884 | 876 |
{
|
| 885 | 877 |
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; |
| 886 |
int offset = addr - s->timer.base; |
|
| 887 | 878 |
|
| 888 |
switch (offset) {
|
|
| 879 |
switch (addr) {
|
|
| 889 | 880 |
case 0x00: /* CNTL_TIMER */ |
| 890 | 881 |
omap_timer_sync(&s->timer); |
| 891 | 882 |
s->timer.ptv = (value >> 9) & 7; |
| ... | ... | |
| 963 | 954 |
|
| 964 | 955 |
s->timer.irq = irq; |
| 965 | 956 |
s->timer.clk = clk; |
| 966 |
s->timer.base = base; |
|
| 967 | 957 |
s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer); |
| 968 | 958 |
omap_wd_timer_reset(s); |
| 969 | 959 |
omap_timer_clk_setup(&s->timer); |
| 970 | 960 |
|
| 971 | 961 |
iomemtype = cpu_register_io_memory(0, omap_wd_timer_readfn, |
| 972 | 962 |
omap_wd_timer_writefn, s); |
| 973 |
cpu_register_physical_memory(s->timer.base, 0x100, iomemtype);
|
|
| 963 |
cpu_register_physical_memory(base, 0x100, iomemtype); |
|
| 974 | 964 |
|
| 975 | 965 |
return s; |
| 976 | 966 |
} |
| ... | ... | |
| 1066 | 1056 |
|
| 1067 | 1057 |
s->timer.irq = irq; |
| 1068 | 1058 |
s->timer.clk = clk; |
| 1069 |
s->timer.base = base; |
|
| 1070 | 1059 |
s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer); |
| 1071 | 1060 |
omap_os_timer_reset(s); |
| 1072 | 1061 |
omap_timer_clk_setup(&s->timer); |
| 1073 | 1062 |
|
| 1074 | 1063 |
iomemtype = cpu_register_io_memory(0, omap_os_timer_readfn, |
| 1075 | 1064 |
omap_os_timer_writefn, s); |
| 1076 |
cpu_register_physical_memory(s->timer.base, 0x800, iomemtype);
|
|
| 1065 |
cpu_register_physical_memory(base, 0x800, iomemtype); |
|
| 1077 | 1066 |
|
| 1078 | 1067 |
return s; |
| 1079 | 1068 |
} |
| ... | ... | |
| 1082 | 1071 |
static uint32_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr) |
| 1083 | 1072 |
{
|
| 1084 | 1073 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
| 1085 |
int offset = addr - s->ulpd_pm_base; |
|
| 1086 | 1074 |
uint16_t ret; |
| 1087 | 1075 |
|
| 1088 |
switch (offset) {
|
|
| 1076 |
switch (addr) {
|
|
| 1089 | 1077 |
case 0x14: /* IT_STATUS */ |
| 1090 |
ret = s->ulpd_pm_regs[offset >> 2];
|
|
| 1091 |
s->ulpd_pm_regs[offset >> 2] = 0;
|
|
| 1078 |
ret = s->ulpd_pm_regs[addr >> 2];
|
|
| 1079 |
s->ulpd_pm_regs[addr >> 2] = 0;
|
|
| 1092 | 1080 |
qemu_irq_lower(s->irq[1][OMAP_INT_GAUGE_32K]); |
| 1093 | 1081 |
return ret; |
| 1094 | 1082 |
|
| ... | ... | |
| 1113 | 1101 |
case 0x48: /* LOCL_TIME */ |
| 1114 | 1102 |
case 0x4c: /* APLL_CTRL */ |
| 1115 | 1103 |
case 0x50: /* POWER_CTRL */ |
| 1116 |
return s->ulpd_pm_regs[offset >> 2];
|
|
| 1104 |
return s->ulpd_pm_regs[addr >> 2];
|
|
| 1117 | 1105 |
} |
| 1118 | 1106 |
|
| 1119 | 1107 |
OMAP_BAD_REG(addr); |
| ... | ... | |
| 1146 | 1134 |
uint32_t value) |
| 1147 | 1135 |
{
|
| 1148 | 1136 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
| 1149 |
int offset = addr - s->ulpd_pm_base; |
|
| 1150 | 1137 |
int64_t now, ticks; |
| 1151 | 1138 |
int div, mult; |
| 1152 | 1139 |
static const int bypass_div[4] = { 1, 2, 4, 4 };
|
| 1153 | 1140 |
uint16_t diff; |
| 1154 | 1141 |
|
| 1155 |
switch (offset) {
|
|
| 1142 |
switch (addr) {
|
|
| 1156 | 1143 |
case 0x00: /* COUNTER_32_LSB */ |
| 1157 | 1144 |
case 0x04: /* COUNTER_32_MSB */ |
| 1158 | 1145 |
case 0x08: /* COUNTER_HIGH_FREQ_LSB */ |
| ... | ... | |
| 1164 | 1151 |
|
| 1165 | 1152 |
case 0x10: /* GAUGING_CTRL */ |
| 1166 | 1153 |
/* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */ |
| 1167 |
if ((s->ulpd_pm_regs[offset >> 2] ^ value) & 1) {
|
|
| 1154 |
if ((s->ulpd_pm_regs[addr >> 2] ^ value) & 1) {
|
|
| 1168 | 1155 |
now = qemu_get_clock(vm_clock); |
| 1169 | 1156 |
|
| 1170 | 1157 |
if (value & 1) |
| ... | ... | |
| 1190 | 1177 |
qemu_irq_raise(s->irq[1][OMAP_INT_GAUGE_32K]); |
| 1191 | 1178 |
} |
| 1192 | 1179 |
} |
| 1193 |
s->ulpd_pm_regs[offset >> 2] = value;
|
|
| 1180 |
s->ulpd_pm_regs[addr >> 2] = value;
|
|
| 1194 | 1181 |
break; |
| 1195 | 1182 |
|
| 1196 | 1183 |
case 0x18: /* Reserved */ |
| ... | ... | |
| 1203 | 1190 |
case 0x38: /* COUNTER_32_FIQ */ |
| 1204 | 1191 |
case 0x48: /* LOCL_TIME */ |
| 1205 | 1192 |
case 0x50: /* POWER_CTRL */ |
| 1206 |
s->ulpd_pm_regs[offset >> 2] = value;
|
|
| 1193 |
s->ulpd_pm_regs[addr >> 2] = value;
|
|
| 1207 | 1194 |
break; |
| 1208 | 1195 |
|
| 1209 | 1196 |
case 0x30: /* CLOCK_CTRL */ |
| 1210 |
diff = s->ulpd_pm_regs[offset >> 2] ^ value;
|
|
| 1211 |
s->ulpd_pm_regs[offset >> 2] = value & 0x3f;
|
|
| 1197 |
diff = s->ulpd_pm_regs[addr >> 2] ^ value;
|
|
| 1198 |
s->ulpd_pm_regs[addr >> 2] = value & 0x3f;
|
|
| 1212 | 1199 |
omap_ulpd_clk_update(s, diff, value); |
| 1213 | 1200 |
break; |
| 1214 | 1201 |
|
| 1215 | 1202 |
case 0x34: /* SOFT_REQ */ |
| 1216 |
diff = s->ulpd_pm_regs[offset >> 2] ^ value;
|
|
| 1217 |
s->ulpd_pm_regs[offset >> 2] = value & 0x1f;
|
|
| 1203 |
diff = s->ulpd_pm_regs[addr >> 2] ^ value;
|
|
| 1204 |
s->ulpd_pm_regs[addr >> 2] = value & 0x1f;
|
|
| 1218 | 1205 |
omap_ulpd_req_update(s, diff, value); |
| 1219 | 1206 |
break; |
| 1220 | 1207 |
|
| ... | ... | |
| 1223 | 1210 |
* omitted altogether, probably a typo. */ |
| 1224 | 1211 |
/* This register has identical semantics with DPLL(1:3) control |
| 1225 | 1212 |
* registers, see omap_dpll_write() */ |
| 1226 |
diff = s->ulpd_pm_regs[offset >> 2] & value;
|
|
| 1227 |
s->ulpd_pm_regs[offset >> 2] = value & 0x2fff;
|
|
| 1213 |
diff = s->ulpd_pm_regs[addr >> 2] & value;
|
|
| 1214 |
s->ulpd_pm_regs[addr >> 2] = value & 0x2fff;
|
|
| 1228 | 1215 |
if (diff & (0x3ff << 2)) {
|
| 1229 | 1216 |
if (value & (1 << 4)) { /* PLL_ENABLE */
|
| 1230 | 1217 |
div = ((value >> 5) & 3) + 1; /* PLL_DIV */ |
| ... | ... | |
| 1237 | 1224 |
} |
| 1238 | 1225 |
|
| 1239 | 1226 |
/* Enter the desired mode. */ |
| 1240 |
s->ulpd_pm_regs[offset >> 2] =
|
|
| 1241 |
(s->ulpd_pm_regs[offset >> 2] & 0xfffe) |
|
|
| 1242 |
((s->ulpd_pm_regs[offset >> 2] >> 4) & 1);
|
|
| 1227 |
s->ulpd_pm_regs[addr >> 2] =
|
|
| 1228 |
(s->ulpd_pm_regs[addr >> 2] & 0xfffe) |
|
|
| 1229 |
((s->ulpd_pm_regs[addr >> 2] >> 4) & 1);
|
|
| 1243 | 1230 |
|
| 1244 | 1231 |
/* Act as if the lock is restored. */ |
| 1245 |
s->ulpd_pm_regs[offset >> 2] |= 2;
|
|
| 1232 |
s->ulpd_pm_regs[addr >> 2] |= 2;
|
|
| 1246 | 1233 |
break; |
| 1247 | 1234 |
|
| 1248 | 1235 |
case 0x4c: /* APLL_CTRL */ |
| 1249 |
diff = s->ulpd_pm_regs[offset >> 2] & value;
|
|
| 1250 |
s->ulpd_pm_regs[offset >> 2] = value & 0xf;
|
|
| 1236 |
diff = s->ulpd_pm_regs[addr >> 2] & value;
|
|
| 1237 |
s->ulpd_pm_regs[addr >> 2] = value & 0xf;
|
|
| 1251 | 1238 |
if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */ |
| 1252 | 1239 |
omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s, |
| 1253 | 1240 |
(value & (1 << 0)) ? "apll" : "dpll4")); |
| ... | ... | |
| 1303 | 1290 |
int iomemtype = cpu_register_io_memory(0, omap_ulpd_pm_readfn, |
| 1304 | 1291 |
omap_ulpd_pm_writefn, mpu); |
| 1305 | 1292 |
|
| 1306 |
mpu->ulpd_pm_base = base; |
|
| 1307 |
cpu_register_physical_memory(mpu->ulpd_pm_base, 0x800, iomemtype); |
|
| 1293 |
cpu_register_physical_memory(base, 0x800, iomemtype); |
|
| 1308 | 1294 |
omap_ulpd_pm_reset(mpu); |
| 1309 | 1295 |
} |
| 1310 | 1296 |
|
| ... | ... | |
| 1312 | 1298 |
static uint32_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr) |
| 1313 | 1299 |
{
|
| 1314 | 1300 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
| 1315 |
int offset = addr - s->pin_cfg_base; |
|
| 1316 | 1301 |
|
| 1317 |
switch (offset) {
|
|
| 1302 |
switch (addr) {
|
|
| 1318 | 1303 |
case 0x00: /* FUNC_MUX_CTRL_0 */ |
| 1319 | 1304 |
case 0x04: /* FUNC_MUX_CTRL_1 */ |
| 1320 | 1305 |
case 0x08: /* FUNC_MUX_CTRL_2 */ |
| 1321 |
return s->func_mux_ctrl[offset >> 2];
|
|
| 1306 |
return s->func_mux_ctrl[addr >> 2];
|
|
| 1322 | 1307 |
|
| 1323 | 1308 |
case 0x0c: /* COMP_MODE_CTRL_0 */ |
| 1324 | 1309 |
return s->comp_mode_ctrl[0]; |
| ... | ... | |
| 1334 | 1319 |
case 0x30: /* FUNC_MUX_CTRL_B */ |
| 1335 | 1320 |
case 0x34: /* FUNC_MUX_CTRL_C */ |
| 1336 | 1321 |
case 0x38: /* FUNC_MUX_CTRL_D */ |
| 1337 |
return s->func_mux_ctrl[(offset >> 2) - 1];
|
|
| 1322 |
return s->func_mux_ctrl[(addr >> 2) - 1];
|
|
| 1338 | 1323 |
|
| 1339 | 1324 |
case 0x40: /* PULL_DWN_CTRL_0 */ |
| 1340 | 1325 |
case 0x44: /* PULL_DWN_CTRL_1 */ |
| 1341 | 1326 |
case 0x48: /* PULL_DWN_CTRL_2 */ |
| 1342 | 1327 |
case 0x4c: /* PULL_DWN_CTRL_3 */ |
| 1343 |
return s->pull_dwn_ctrl[(offset & 0xf) >> 2];
|
|
| 1328 |
return s->pull_dwn_ctrl[(addr & 0xf) >> 2];
|
|
| 1344 | 1329 |
|
| 1345 | 1330 |
case 0x50: /* GATE_INH_CTRL_0 */ |
| 1346 | 1331 |
return s->gate_inh_ctrl[0]; |
| ... | ... | |
| 1416 | 1401 |
uint32_t value) |
| 1417 | 1402 |
{
|
| 1418 | 1403 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
| 1419 |
int offset = addr - s->pin_cfg_base; |
|
| 1420 | 1404 |
uint32_t diff; |
| 1421 | 1405 |
|
| 1422 |
switch (offset) {
|
|
| 1406 |
switch (addr) {
|
|
| 1423 | 1407 |
case 0x00: /* FUNC_MUX_CTRL_0 */ |
| 1424 |
diff = s->func_mux_ctrl[offset >> 2] ^ value;
|
|
| 1425 |
s->func_mux_ctrl[offset >> 2] = value;
|
|
| 1408 |
diff = s->func_mux_ctrl[addr >> 2] ^ value;
|
|
| 1409 |
s->func_mux_ctrl[addr >> 2] = value;
|
|
| 1426 | 1410 |
omap_pin_funcmux0_update(s, diff, value); |
| 1427 | 1411 |
return; |
| 1428 | 1412 |
|
| 1429 | 1413 |
case 0x04: /* FUNC_MUX_CTRL_1 */ |
| 1430 |
diff = s->func_mux_ctrl[offset >> 2] ^ value;
|
|
| 1431 |
s->func_mux_ctrl[offset >> 2] = value;
|
|
| 1414 |
diff = s->func_mux_ctrl[addr >> 2] ^ value;
|
|
| 1415 |
s->func_mux_ctrl[addr >> 2] = value;
|
|
| 1432 | 1416 |
omap_pin_funcmux1_update(s, diff, value); |
| 1433 | 1417 |
return; |
| 1434 | 1418 |
|
| 1435 | 1419 |
case 0x08: /* FUNC_MUX_CTRL_2 */ |
| 1436 |
s->func_mux_ctrl[offset >> 2] = value;
|
|
| 1420 |
s->func_mux_ctrl[addr >> 2] = value;
|
|
| 1437 | 1421 |
return; |
| 1438 | 1422 |
|
| 1439 | 1423 |
case 0x0c: /* COMP_MODE_CTRL_0 */ |
| ... | ... | |
| 1454 | 1438 |
case 0x30: /* FUNC_MUX_CTRL_B */ |
| 1455 | 1439 |
case 0x34: /* FUNC_MUX_CTRL_C */ |
| 1456 | 1440 |
case 0x38: /* FUNC_MUX_CTRL_D */ |
| 1457 |
s->func_mux_ctrl[(offset >> 2) - 1] = value;
|
|
| 1441 |
s->func_mux_ctrl[(addr >> 2) - 1] = value;
|
|
| 1458 | 1442 |
return; |
| 1459 | 1443 |
|
| 1460 | 1444 |
case 0x40: /* PULL_DWN_CTRL_0 */ |
| 1461 | 1445 |
case 0x44: /* PULL_DWN_CTRL_1 */ |
| 1462 | 1446 |
case 0x48: /* PULL_DWN_CTRL_2 */ |
| 1463 | 1447 |
case 0x4c: /* PULL_DWN_CTRL_3 */ |
| 1464 |
s->pull_dwn_ctrl[(offset & 0xf) >> 2] = value;
|
|
| 1448 |
s->pull_dwn_ctrl[(addr & 0xf) >> 2] = value;
|
|
| 1465 | 1449 |
return; |
| 1466 | 1450 |
|
| 1467 | 1451 |
case 0x50: /* GATE_INH_CTRL_0 */ |
| ... | ... | |
| 1521 | 1505 |
int iomemtype = cpu_register_io_memory(0, omap_pin_cfg_readfn, |
| 1522 | 1506 |
omap_pin_cfg_writefn, mpu); |
| 1523 | 1507 |
|
| 1524 |
mpu->pin_cfg_base = base; |
|
| 1525 |
cpu_register_physical_memory(mpu->pin_cfg_base, 0x800, iomemtype); |
|
| 1508 |
cpu_register_physical_memory(base, 0x800, iomemtype); |
|
| 1526 | 1509 |
omap_pin_cfg_reset(mpu); |
| 1527 | 1510 |
} |
| 1528 | 1511 |
|
| ... | ... | |
| 1591 | 1574 |
{
|
| 1592 | 1575 |
int iomemtype = cpu_register_io_memory(0, omap_id_readfn, |
| 1593 | 1576 |
omap_id_writefn, mpu); |
| 1594 |
cpu_register_physical_memory(0xfffe1800, 0x800, iomemtype);
|
|
| 1595 |
cpu_register_physical_memory(0xfffed400, 0x100, iomemtype);
|
|
| 1577 |
cpu_register_physical_memory_offset(0xfffe1800, 0x800, iomemtype, 0xfffe1800);
|
|
| 1578 |
cpu_register_physical_memory_offset(0xfffed400, 0x100, iomemtype, 0xfffed400);
|
|
| 1596 | 1579 |
if (!cpu_is_omap15xx(mpu)) |
| 1597 |
cpu_register_physical_memory(0xfffe2000, 0x800, iomemtype);
|
|
| 1580 |
cpu_register_physical_memory_offset(0xfffe2000, 0x800, iomemtype, 0xfffe2000);
|
|
| 1598 | 1581 |
} |
| 1599 | 1582 |
|
| 1600 | 1583 |
/* MPUI Control (Dummy) */ |
| 1601 | 1584 |
static uint32_t omap_mpui_read(void *opaque, target_phys_addr_t addr) |
| 1602 | 1585 |
{
|
| 1603 | 1586 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
| 1604 |
int offset = addr - s->mpui_base; |
|
| 1605 | 1587 |
|
| 1606 |
switch (offset) {
|
|
| 1588 |
switch (addr) {
|
|
| 1607 | 1589 |
case 0x00: /* CTRL */ |
| 1608 | 1590 |
return s->mpui_ctrl; |
| 1609 | 1591 |
case 0x04: /* DEBUG_ADDR */ |
| ... | ... | |
| 1631 | 1613 |
uint32_t value) |
| 1632 | 1614 |
{
|
| 1633 | 1615 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
| 1634 |
int offset = addr - s->mpui_base; |
|
| 1635 | 1616 |
|
| 1636 |
switch (offset) {
|
|
| 1617 |
switch (addr) {
|
|
| 1637 | 1618 |
case 0x00: /* CTRL */ |
| 1638 | 1619 |
s->mpui_ctrl = value & 0x007fffff; |
| 1639 | 1620 |
break; |
| ... | ... | |
| 1677 | 1658 |
int iomemtype = cpu_register_io_memory(0, omap_mpui_readfn, |
| 1678 | 1659 |
omap_mpui_writefn, mpu); |
| 1679 | 1660 |
|
| 1680 |
mpu->mpui_base = base; |
|
| 1681 |
cpu_register_physical_memory(mpu->mpui_base, 0x100, iomemtype); |
|
| 1661 |
cpu_register_physical_memory(base, 0x100, iomemtype); |
|
| 1682 | 1662 |
|
| 1683 | 1663 |
omap_mpui_reset(mpu); |
| 1684 | 1664 |
} |
| 1685 | 1665 |
|
| 1686 | 1666 |
/* TIPB Bridges */ |
| 1687 | 1667 |
struct omap_tipb_bridge_s {
|
| 1688 |
target_phys_addr_t base; |
|
| 1689 | 1668 |
qemu_irq abort; |
| 1690 | 1669 |
|
| 1691 | 1670 |
int width_intr; |
| ... | ... | |
| 1698 | 1677 |
static uint32_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr) |
| 1699 | 1678 |
{
|
| 1700 | 1679 |
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; |
| 1701 |
int offset = addr - s->base; |
|
| 1702 | 1680 |
|
| 1703 |
switch (offset) {
|
|
| 1681 |
switch (addr) {
|
|
| 1704 | 1682 |
case 0x00: /* TIPB_CNTL */ |
| 1705 | 1683 |
return s->control; |
| 1706 | 1684 |
case 0x04: /* TIPB_BUS_ALLOC */ |
| ... | ... | |
| 1725 | 1703 |
uint32_t value) |
| 1726 | 1704 |
{
|
| 1727 | 1705 |
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; |
| 1728 |
int offset = addr - s->base; |
|
| 1729 | 1706 |
|
| 1730 |
switch (offset) {
|
|
| 1707 |
switch (addr) {
|
|
| 1731 | 1708 |
case 0x00: /* TIPB_CNTL */ |
| 1732 | 1709 |
s->control = value & 0xffff; |
| 1733 | 1710 |
break; |
| ... | ... | |
| 1785 | 1762 |
qemu_mallocz(sizeof(struct omap_tipb_bridge_s)); |
| 1786 | 1763 |
|
| 1787 | 1764 |
s->abort = abort_irq; |
| 1788 |
s->base = base; |
|
| 1789 | 1765 |
omap_tipb_bridge_reset(s); |
| 1790 | 1766 |
|
| 1791 | 1767 |
iomemtype = cpu_register_io_memory(0, omap_tipb_bridge_readfn, |
| 1792 | 1768 |
omap_tipb_bridge_writefn, s); |
| 1793 |
cpu_register_physical_memory(s->base, 0x100, iomemtype);
|
|
| 1769 |
cpu_register_physical_memory(base, 0x100, iomemtype); |
|
| 1794 | 1770 |
|
| 1795 | 1771 |
return s; |
| 1796 | 1772 |
} |
| ... | ... | |
| 1799 | 1775 |
static uint32_t omap_tcmi_read(void *opaque, target_phys_addr_t addr) |
| 1800 | 1776 |
{
|
| 1801 | 1777 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
| 1802 |
int offset = addr - s->tcmi_base; |
|
| 1803 | 1778 |
uint32_t ret; |
| 1804 | 1779 |
|
| 1805 |
switch (offset) {
|
|
| 1780 |
switch (addr) {
|
|
| 1806 | 1781 |
case 0x00: /* IMIF_PRIO */ |
| 1807 | 1782 |
case 0x04: /* EMIFS_PRIO */ |
| 1808 | 1783 |
case 0x08: /* EMIFF_PRIO */ |
| ... | ... | |
| 1817 | 1792 |
case 0x30: /* TIMEOUT3 */ |
| 1818 | 1793 |
case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ |
| 1819 | 1794 |
case 0x40: /* EMIFS_CFG_DYN_WAIT */ |
| 1820 |
return s->tcmi_regs[offset >> 2];
|
|
| 1795 |
return s->tcmi_regs[addr >> 2];
|
|
| 1821 | 1796 |
|
| 1822 | 1797 |
case 0x20: /* EMIFF_SDRAM_CONFIG */ |
| 1823 |
ret = s->tcmi_regs[offset >> 2];
|
|
| 1824 |
s->tcmi_regs[offset >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */
|
|
| 1798 |
ret = s->tcmi_regs[addr >> 2];
|
|
| 1799 |
s->tcmi_regs[addr >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */
|
|
| 1825 | 1800 |
/* XXX: We can try using the VGA_DIRTY flag for this */ |
| 1826 | 1801 |
return ret; |
| 1827 | 1802 |
} |
| ... | ... | |
| 1834 | 1809 |
uint32_t value) |
| 1835 | 1810 |
{
|
| 1836 | 1811 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
| 1837 |
int offset = addr - s->tcmi_base; |
|
| 1838 | 1812 |
|
| 1839 |
switch (offset) {
|
|
| 1813 |
switch (addr) {
|
|
| 1840 | 1814 |
case 0x00: /* IMIF_PRIO */ |
| 1841 | 1815 |
case 0x04: /* EMIFS_PRIO */ |
| 1842 | 1816 |
case 0x08: /* EMIFF_PRIO */ |
| ... | ... | |
| 1851 | 1825 |
case 0x30: /* TIMEOUT3 */ |
| 1852 | 1826 |
case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ |
| 1853 | 1827 |
case 0x40: /* EMIFS_CFG_DYN_WAIT */ |
| 1854 |
s->tcmi_regs[offset >> 2] = value;
|
|
| 1828 |
s->tcmi_regs[addr >> 2] = value;
|
|
| 1855 | 1829 |
break; |
| 1856 | 1830 |
case 0x0c: /* EMIFS_CONFIG */ |
| 1857 |
s->tcmi_regs[offset >> 2] = (value & 0xf) | (1 << 4);
|
|
| 1831 |
s->tcmi_regs[addr >> 2] = (value & 0xf) | (1 << 4);
|
|
| 1858 | 1832 |
break; |
| 1859 | 1833 |
|
| 1860 | 1834 |
default: |
| ... | ... | |
| 1899 | 1873 |
int iomemtype = cpu_register_io_memory(0, omap_tcmi_readfn, |
| 1900 | 1874 |
omap_tcmi_writefn, mpu); |
| 1901 | 1875 |
|
| 1902 |
mpu->tcmi_base = base; |
|
| 1903 |
cpu_register_physical_memory(mpu->tcmi_base, 0x100, iomemtype); |
|
| 1876 |
cpu_register_physical_memory(base, 0x100, iomemtype); |
|
| 1904 | 1877 |
omap_tcmi_reset(mpu); |
| 1905 | 1878 |
} |
| 1906 | 1879 |
|
| ... | ... | |
| 1908 | 1881 |
static uint32_t omap_dpll_read(void *opaque, target_phys_addr_t addr) |
| 1909 | 1882 |
{
|
| 1910 | 1883 |
struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; |
| 1911 |
int offset = addr - s->base; |
|
| 1912 | 1884 |
|
| 1913 |
if (offset == 0x00) /* CTL_REG */
|
|
| 1885 |
if (addr == 0x00) /* CTL_REG */
|
|
| 1914 | 1886 |
return s->mode; |
| 1915 | 1887 |
|
| 1916 | 1888 |
OMAP_BAD_REG(addr); |
| ... | ... | |
| 1922 | 1894 |
{
|
| 1923 | 1895 |
struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; |
| 1924 | 1896 |
uint16_t diff; |
| 1925 |
int offset = addr - s->base; |
|
| 1926 | 1897 |
static const int bypass_div[4] = { 1, 2, 4, 4 };
|
| 1927 | 1898 |
int div, mult; |
| 1928 | 1899 |
|
| 1929 |
if (offset == 0x00) { /* CTL_REG */
|
|
| 1900 |
if (addr == 0x00) { /* CTL_REG */
|
|
| 1930 | 1901 |
/* See omap_ulpd_pm_write() too */ |
| 1931 | 1902 |
diff = s->mode & value; |
| 1932 | 1903 |
s->mode = value & 0x2fff; |
| ... | ... | |
| 1975 | 1946 |
int iomemtype = cpu_register_io_memory(0, omap_dpll_readfn, |
| 1976 | 1947 |
omap_dpll_writefn, s); |
| 1977 | 1948 |
|
| 1978 |
s->base = base; |
|
| 1979 | 1949 |
s->dpll = clk; |
| 1980 | 1950 |
omap_dpll_reset(s); |
| 1981 | 1951 |
|
| 1982 |
cpu_register_physical_memory(s->base, 0x100, iomemtype);
|
|
| 1952 |
cpu_register_physical_memory(base, 0x100, iomemtype); |
|
| 1983 | 1953 |
} |
| 1984 | 1954 |
|
| 1985 | 1955 |
/* UARTs */ |
| 1986 | 1956 |
struct omap_uart_s {
|
| 1957 |
target_phys_addr_t base; |
|
| 1987 | 1958 |
SerialState *serial; /* TODO */ |
| 1988 | 1959 |
struct omap_target_agent_s *ta; |
| 1989 |
target_phys_addr_t base; |
|
| 1990 | 1960 |
omap_clk fclk; |
| 1991 | 1961 |
qemu_irq irq; |
| 1992 | 1962 |
|
| ... | ... | |
| 2025 | 1995 |
static uint32_t omap_uart_read(void *opaque, target_phys_addr_t addr) |
| 2026 | 1996 |
{
|
| 2027 | 1997 |
struct omap_uart_s *s = (struct omap_uart_s *) opaque; |
| 2028 |
int offset = addr - s->base; |
|
| 2029 | 1998 |
|
| 2030 |
switch (offset) {
|
|
| 1999 |
addr &= 0xff; |
|
| 2000 |
switch (addr) {
|
|
| 2031 | 2001 |
case 0x20: /* MDR1 */ |
| 2032 | 2002 |
return s->mdr[0]; |
| 2033 | 2003 |
case 0x24: /* MDR2 */ |
| ... | ... | |
| 2058 | 2028 |
uint32_t value) |
| 2059 | 2029 |
{
|
| 2060 | 2030 |
struct omap_uart_s *s = (struct omap_uart_s *) opaque; |
| 2061 |
int offset = addr - s->base; |
|
| 2062 | 2031 |
|
| 2063 |
switch (offset) {
|
|
| 2032 |
addr &= 0xff; |
|
| 2033 |
switch (addr) {
|
|
| 2064 | 2034 |
case 0x20: /* MDR1 */ |
| 2065 | 2035 |
s->mdr[0] = value & 0x7f; |
| 2066 | 2036 |
break; |
| ... | ... | |
| 2118 | 2088 |
|
| 2119 | 2089 |
s->ta = ta; |
| 2120 | 2090 |
|
| 2121 |
cpu_register_physical_memory(s->base + 0x20, 0x100, iomemtype);
|
|
| 2091 |
cpu_register_physical_memory(base + 0x20, 0x100, iomemtype); |
|
| 2122 | 2092 |
|
| 2123 | 2093 |
return s; |
| 2124 | 2094 |
} |
| ... | ... | |
| 2135 | 2105 |
static uint32_t omap_clkm_read(void *opaque, target_phys_addr_t addr) |
| 2136 | 2106 |
{
|
| 2137 | 2107 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
| 2138 |
int offset = addr - s->clkm.mpu_base; |
|
| 2139 | 2108 |
|
| 2140 |
switch (offset) {
|
|
| 2109 |
switch (addr) {
|
|
| 2141 | 2110 |
case 0x00: /* ARM_CKCTL */ |
| 2142 | 2111 |
return s->clkm.arm_ckctl; |
| 2143 | 2112 |
|
| ... | ... | |
| 2333 | 2302 |
uint32_t value) |
| 2334 | 2303 |
{
|
| 2335 | 2304 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
| 2336 |
int offset = addr - s->clkm.mpu_base; |
|
| 2337 | 2305 |
uint16_t diff; |
| 2338 | 2306 |
omap_clk clk; |
| 2339 | 2307 |
static const char *clkschemename[8] = {
|
| ... | ... | |
| 2341 | 2309 |
"mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4", |
| 2342 | 2310 |
}; |
| 2343 | 2311 |
|
| 2344 |
switch (offset) {
|
|
| 2312 |
switch (addr) {
|
|
| 2345 | 2313 |
case 0x00: /* ARM_CKCTL */ |
| 2346 | 2314 |
diff = s->clkm.arm_ckctl ^ value; |
| 2347 | 2315 |
s->clkm.arm_ckctl = value & 0x7fff; |
| ... | ... | |
| 2423 | 2391 |
static uint32_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr) |
| 2424 | 2392 |
{
|
| 2425 | 2393 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
| 2426 |
int offset = addr - s->clkm.dsp_base; |
|
| 2427 | 2394 |
|
| 2428 |
switch (offset) {
|
|
| 2395 |
switch (addr) {
|
|
| 2429 | 2396 |
case 0x04: /* DSP_IDLECT1 */ |
| 2430 | 2397 |
return s->clkm.dsp_idlect1; |
| 2431 | 2398 |
|
| ... | ... | |
| 2464 | 2431 |
uint32_t value) |
| 2465 | 2432 |
{
|
| 2466 | 2433 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
| 2467 |
int offset = addr - s->clkm.dsp_base; |
|
| 2468 | 2434 |
uint16_t diff; |
| 2469 | 2435 |
|
| 2470 |
switch (offset) {
|
|
| 2436 |
switch (addr) {
|
|
| 2471 | 2437 |
case 0x04: /* DSP_IDLECT1 */ |
| 2472 | 2438 |
diff = s->clkm.dsp_idlect1 ^ value; |
| 2473 | 2439 |
s->clkm.dsp_idlect1 = value & 0x01f7; |
| ... | ... | |
| 2536 | 2502 |
cpu_register_io_memory(0, omap_clkdsp_readfn, omap_clkdsp_writefn, s), |
| 2537 | 2503 |
}; |
| 2538 | 2504 |
|
| 2539 |
s->clkm.mpu_base = mpu_base; |
|
| 2540 |
s->clkm.dsp_base = dsp_base; |
|
| 2541 | 2505 |
s->clkm.arm_idlect1 = 0x03ff; |
| 2542 | 2506 |
s->clkm.arm_idlect2 = 0x0100; |
| 2543 | 2507 |
s->clkm.dsp_idlect1 = 0x0002; |
| 2544 | 2508 |
omap_clkm_reset(s); |
| 2545 | 2509 |
s->clkm.cold_start = 0x3a; |
| 2546 | 2510 |
|
| 2547 |
cpu_register_physical_memory(s->clkm.mpu_base, 0x100, iomemtype[0]);
|
|
| 2548 |
cpu_register_physical_memory(s->clkm.dsp_base, 0x1000, iomemtype[1]);
|
|
| 2511 |
cpu_register_physical_memory(mpu_base, 0x100, iomemtype[0]); |
|
| 2512 |
cpu_register_physical_memory(dsp_base, 0x1000, iomemtype[1]); |
|
| 2549 | 2513 |
} |
| 2550 | 2514 |
|
| 2551 | 2515 |
/* MPU I/O */ |
| 2552 | 2516 |
struct omap_mpuio_s {
|
| 2553 |
target_phys_addr_t base; |
|
| 2554 | 2517 |
qemu_irq irq; |
| 2555 | 2518 |
qemu_irq kbd_irq; |
| 2556 | 2519 |
qemu_irq *in; |
| ... | ... | |
| 2783 | 2746 |
struct omap_mpuio_s *s = (struct omap_mpuio_s *) |
| 2784 | 2747 |
qemu_mallocz(sizeof(struct omap_mpuio_s)); |
| 2785 | 2748 |
|
| 2786 |
s->base = base; |
|
| 2787 | 2749 |
s->irq = gpio_int; |
| 2788 | 2750 |
s->kbd_irq = kbd_int; |
| 2789 | 2751 |
s->wakeup = wakeup; |
| ... | ... | |
| 2792 | 2754 |
|
| 2793 | 2755 |
iomemtype = cpu_register_io_memory(0, omap_mpuio_readfn, |
| 2794 | 2756 |
omap_mpuio_writefn, s); |
| 2795 |
cpu_register_physical_memory(s->base, 0x800, iomemtype);
|
|
| 2757 |
cpu_register_physical_memory(base, 0x800, iomemtype); |
|
| 2796 | 2758 |
|
| 2797 | 2759 |
omap_clk_adduser(clk, qemu_allocate_irqs(omap_mpuio_onoff, s, 1)[0]); |
| 2798 | 2760 |
|
| ... | ... | |
| 2827 | 2789 |
|
| 2828 | 2790 |
/* General-Purpose I/O */ |
| 2829 | 2791 |
struct omap_gpio_s {
|
| 2830 |
target_phys_addr_t base; |
|
| 2831 | 2792 |
qemu_irq irq; |
| 2832 | 2793 |
qemu_irq *in; |
| 2833 | 2794 |
qemu_irq handler[16]; |
| ... | ... | |
| 2984 | 2945 |
struct omap_gpio_s *s = (struct omap_gpio_s *) |
| 2985 | 2946 |
qemu_mallocz(sizeof(struct omap_gpio_s)); |
| 2986 | 2947 |
|
| 2987 |
s->base = base; |
|
| 2988 | 2948 |
s->irq = irq; |
| 2989 | 2949 |
s->in = qemu_allocate_irqs(omap_gpio_set, s, 16); |
| 2990 | 2950 |
omap_gpio_reset(s); |
| 2991 | 2951 |
|
| 2992 | 2952 |
iomemtype = cpu_register_io_memory(0, omap_gpio_readfn, |
| 2993 | 2953 |
omap_gpio_writefn, s); |
| 2994 |
cpu_register_physical_memory(s->base, 0x1000, iomemtype);
|
|
| 2954 |
cpu_register_physical_memory(base, 0x1000, iomemtype); |
|
| 2995 | 2955 |
|
| 2996 | 2956 |
return s; |
| 2997 | 2957 |
} |
| ... | ... | |
| 3010 | 2970 |
|
| 3011 | 2971 |
/* MicroWire Interface */ |
| 3012 | 2972 |
struct omap_uwire_s {
|
| 3013 |
target_phys_addr_t base; |
|
| 3014 | 2973 |
qemu_irq txirq; |
| 3015 | 2974 |
qemu_irq rxirq; |
| 3016 | 2975 |
qemu_irq txdrq; |
| ... | ... | |
| 3155 | 3114 |
struct omap_uwire_s *s = (struct omap_uwire_s *) |
| 3156 | 3115 |
qemu_mallocz(sizeof(struct omap_uwire_s)); |
| 3157 | 3116 |
|
| 3158 |
s->base = base; |
|
| 3159 | 3117 |
s->txirq = irq[0]; |
| 3160 | 3118 |
s->rxirq = irq[1]; |
| 3161 | 3119 |
s->txdrq = dma; |
| ... | ... | |
| 3163 | 3121 |
|
| 3164 | 3122 |
iomemtype = cpu_register_io_memory(0, omap_uwire_readfn, |
| 3165 | 3123 |
omap_uwire_writefn, s); |
| 3166 |
cpu_register_physical_memory(s->base, 0x800, iomemtype);
|
|
| 3124 |
cpu_register_physical_memory(base, 0x800, iomemtype); |
|
| 3167 | 3125 |
|
| 3168 | 3126 |
return s; |
| 3169 | 3127 |
} |
| ... | ... | |
| 3364 | 3322 |
|
| 3365 | 3323 |
/* Real-time Clock module */ |
| 3366 | 3324 |
struct omap_rtc_s {
|
| 3367 |
target_phys_addr_t base; |
|
| 3368 | 3325 |
qemu_irq irq; |
| 3369 | 3326 |
qemu_irq alarm; |
| 3370 | 3327 |
QEMUTimer *clk; |
| ... | ... | |
| 3775 | 3732 |
struct omap_rtc_s *s = (struct omap_rtc_s *) |
| 3776 | 3733 |
qemu_mallocz(sizeof(struct omap_rtc_s)); |
| 3777 | 3734 |
|
| 3778 |
s->base = base; |
|
| 3779 | 3735 |
s->irq = irq[0]; |
| 3780 | 3736 |
s->alarm = irq[1]; |
| 3781 | 3737 |
s->clk = qemu_new_timer(rt_clock, omap_rtc_tick, s); |
| ... | ... | |
| 3784 | 3740 |
|
| 3785 | 3741 |
iomemtype = cpu_register_io_memory(0, omap_rtc_readfn, |
| 3786 | 3742 |
omap_rtc_writefn, s); |
| 3787 |
cpu_register_physical_memory(s->base, 0x800, iomemtype);
|
|
| 3743 |
cpu_register_physical_memory(base, 0x800, iomemtype); |
|
| 3788 | 3744 |
|
| 3789 | 3745 |
return s; |
| 3790 | 3746 |
} |
| 3791 | 3747 |
|
| 3792 | 3748 |
/* Multi-channel Buffered Serial Port interfaces */ |
| 3793 | 3749 |
struct omap_mcbsp_s {
|
| 3794 |
target_phys_addr_t base; |
|
| 3795 | 3750 |
qemu_irq txirq; |
| 3796 | 3751 |
qemu_irq rxirq; |
| 3797 | 3752 |
qemu_irq txdrq; |
| ... | ... | |
| 4295 | 4250 |
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) |
| 4296 | 4251 |
qemu_mallocz(sizeof(struct omap_mcbsp_s)); |
| 4297 | 4252 |
|
| 4298 |
s->base = base; |
|
| 4299 | 4253 |
s->txirq = irq[0]; |
| 4300 | 4254 |
s->rxirq = irq[1]; |
| 4301 | 4255 |
s->txdrq = dma[0]; |
| ... | ... | |
| 4306 | 4260 |
|
| 4307 | 4261 |
iomemtype = cpu_register_io_memory(0, omap_mcbsp_readfn, |
| 4308 | 4262 |
omap_mcbsp_writefn, s); |
| 4309 |
cpu_register_physical_memory(s->base, 0x800, iomemtype);
|
|
| 4263 |
cpu_register_physical_memory(base, 0x800, iomemtype); |
|
| 4310 | 4264 |
|
| 4311 | 4265 |
return s; |
| 4312 | 4266 |
} |
| ... | ... | |
| 4340 | 4294 |
|
| 4341 | 4295 |
/* LED Pulse Generators */ |
| 4342 | 4296 |
struct omap_lpg_s {
|
| 4343 |
target_phys_addr_t base; |
|
| 4344 | 4297 |
QEMUTimer *tm; |
| 4345 | 4298 |
|
| 4346 | 4299 |
uint8_t control; |
| ... | ... | |
| 4473 | 4426 |
struct omap_lpg_s *s = (struct omap_lpg_s *) |
| 4474 | 4427 |
qemu_mallocz(sizeof(struct omap_lpg_s)); |
| 4475 | 4428 |
|
| 4476 |
s->base = base; |
|
| 4477 | 4429 |
s->tm = qemu_new_timer(rt_clock, omap_lpg_tick, s); |
| 4478 | 4430 |
|
| 4479 | 4431 |
omap_lpg_reset(s); |
| 4480 | 4432 |
|
| 4481 | 4433 |
iomemtype = cpu_register_io_memory(0, omap_lpg_readfn, |
| 4482 | 4434 |
omap_lpg_writefn, s); |
| 4483 |
cpu_register_physical_memory(s->base, 0x800, iomemtype);
|
|
| 4435 |
cpu_register_physical_memory(base, 0x800, iomemtype); |
|
| 4484 | 4436 |
|
| 4485 | 4437 |
omap_clk_adduser(clk, qemu_allocate_irqs(omap_lpg_clk_update, s, 1)[0]); |
| 4486 | 4438 |
|
Also available in: Unified diff