Revision 8da3ff18 hw/omap_dma.c
| b/hw/omap_dma.c | ||
|---|---|---|
| 106 | 106 |
struct soc_dma_s *dma; |
| 107 | 107 |
|
| 108 | 108 |
struct omap_mpu_state_s *mpu; |
| 109 |
target_phys_addr_t base; |
|
| 110 | 109 |
omap_clk clk; |
| 111 | 110 |
qemu_irq irq[4]; |
| 112 | 111 |
void (*intr_update)(struct omap_dma_s *s); |
| ... | ... | |
| 1447 | 1446 |
static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr) |
| 1448 | 1447 |
{
|
| 1449 | 1448 |
struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
| 1450 |
int reg, ch, offset = addr - s->base;
|
|
| 1449 |
int reg, ch; |
|
| 1451 | 1450 |
uint16_t ret; |
| 1452 | 1451 |
|
| 1453 |
switch (offset) {
|
|
| 1452 |
switch (addr) {
|
|
| 1454 | 1453 |
case 0x300 ... 0x3fe: |
| 1455 | 1454 |
if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
|
| 1456 |
if (omap_dma_3_1_lcd_read(&s->lcd_ch, offset, &ret))
|
|
| 1455 |
if (omap_dma_3_1_lcd_read(&s->lcd_ch, addr, &ret))
|
|
| 1457 | 1456 |
break; |
| 1458 | 1457 |
return ret; |
| 1459 | 1458 |
} |
| 1460 | 1459 |
/* Fall through. */ |
| 1461 | 1460 |
case 0x000 ... 0x2fe: |
| 1462 |
reg = offset & 0x3f;
|
|
| 1463 |
ch = (offset >> 6) & 0x0f;
|
|
| 1461 |
reg = addr & 0x3f;
|
|
| 1462 |
ch = (addr >> 6) & 0x0f;
|
|
| 1464 | 1463 |
if (omap_dma_ch_reg_read(s, &s->ch[ch], reg, &ret)) |
| 1465 | 1464 |
break; |
| 1466 | 1465 |
return ret; |
| ... | ... | |
| 1470 | 1469 |
break; |
| 1471 | 1470 |
/* Fall through. */ |
| 1472 | 1471 |
case 0x400: |
| 1473 |
if (omap_dma_sys_read(s, offset, &ret))
|
|
| 1472 |
if (omap_dma_sys_read(s, addr, &ret))
|
|
| 1474 | 1473 |
break; |
| 1475 | 1474 |
return ret; |
| 1476 | 1475 |
|
| 1477 | 1476 |
case 0xb00 ... 0xbfe: |
| 1478 | 1477 |
if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
|
| 1479 |
if (omap_dma_3_2_lcd_read(&s->lcd_ch, offset, &ret))
|
|
| 1478 |
if (omap_dma_3_2_lcd_read(&s->lcd_ch, addr, &ret))
|
|
| 1480 | 1479 |
break; |
| 1481 | 1480 |
return ret; |
| 1482 | 1481 |
} |
| ... | ... | |
| 1491 | 1490 |
uint32_t value) |
| 1492 | 1491 |
{
|
| 1493 | 1492 |
struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
| 1494 |
int reg, ch, offset = addr - s->base;
|
|
| 1493 |
int reg, ch; |
|
| 1495 | 1494 |
|
| 1496 |
switch (offset) {
|
|
| 1495 |
switch (addr) {
|
|
| 1497 | 1496 |
case 0x300 ... 0x3fe: |
| 1498 | 1497 |
if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
|
| 1499 |
if (omap_dma_3_1_lcd_write(&s->lcd_ch, offset, value))
|
|
| 1498 |
if (omap_dma_3_1_lcd_write(&s->lcd_ch, addr, value))
|
|
| 1500 | 1499 |
break; |
| 1501 | 1500 |
return; |
| 1502 | 1501 |
} |
| 1503 | 1502 |
/* Fall through. */ |
| 1504 | 1503 |
case 0x000 ... 0x2fe: |
| 1505 |
reg = offset & 0x3f;
|
|
| 1506 |
ch = (offset >> 6) & 0x0f;
|
|
| 1504 |
reg = addr & 0x3f;
|
|
| 1505 |
ch = (addr >> 6) & 0x0f;
|
|
| 1507 | 1506 |
if (omap_dma_ch_reg_write(s, &s->ch[ch], reg, value)) |
| 1508 | 1507 |
break; |
| 1509 | 1508 |
return; |
| ... | ... | |
| 1513 | 1512 |
break; |
| 1514 | 1513 |
case 0x400: |
| 1515 | 1514 |
/* Fall through. */ |
| 1516 |
if (omap_dma_sys_write(s, offset, value))
|
|
| 1515 |
if (omap_dma_sys_write(s, addr, value))
|
|
| 1517 | 1516 |
break; |
| 1518 | 1517 |
return; |
| 1519 | 1518 |
|
| 1520 | 1519 |
case 0xb00 ... 0xbfe: |
| 1521 | 1520 |
if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
|
| 1522 |
if (omap_dma_3_2_lcd_write(&s->lcd_ch, offset, value))
|
|
| 1521 |
if (omap_dma_3_2_lcd_write(&s->lcd_ch, addr, value))
|
|
| 1523 | 1522 |
break; |
| 1524 | 1523 |
return; |
| 1525 | 1524 |
} |
| ... | ... | |
| 1628 | 1627 |
num_irqs = 16; |
| 1629 | 1628 |
memsize = 0xc00; |
| 1630 | 1629 |
} |
| 1631 |
s->base = base; |
|
| 1632 | 1630 |
s->model = model; |
| 1633 | 1631 |
s->mpu = mpu; |
| 1634 | 1632 |
s->clk = clk; |
| ... | ... | |
| 1660 | 1658 |
|
| 1661 | 1659 |
iomemtype = cpu_register_io_memory(0, omap_dma_readfn, |
| 1662 | 1660 |
omap_dma_writefn, s); |
| 1663 |
cpu_register_physical_memory(s->base, memsize, iomemtype);
|
|
| 1661 |
cpu_register_physical_memory(base, memsize, iomemtype); |
|
| 1664 | 1662 |
|
| 1665 | 1663 |
mpu->drq = s->dma->drq; |
| 1666 | 1664 |
|
| ... | ... | |
| 1691 | 1689 |
static uint32_t omap_dma4_read(void *opaque, target_phys_addr_t addr) |
| 1692 | 1690 |
{
|
| 1693 | 1691 |
struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
| 1694 |
int irqn = 0, chnum, offset = addr - s->base;
|
|
| 1692 |
int irqn = 0, chnum; |
|
| 1695 | 1693 |
struct omap_dma_channel_s *ch; |
| 1696 | 1694 |
|
| 1697 |
switch (offset) {
|
|
| 1695 |
switch (addr) {
|
|
| 1698 | 1696 |
case 0x00: /* DMA4_REVISION */ |
| 1699 | 1697 |
return 0x40; |
| 1700 | 1698 |
|
| ... | ... | |
| 1735 | 1733 |
return s->gcr; |
| 1736 | 1734 |
|
| 1737 | 1735 |
case 0x80 ... 0xfff: |
| 1738 |
offset -= 0x80;
|
|
| 1739 |
chnum = offset / 0x60;
|
|
| 1736 |
addr -= 0x80;
|
|
| 1737 |
chnum = addr / 0x60;
|
|
| 1740 | 1738 |
ch = s->ch + chnum; |
| 1741 |
offset -= chnum * 0x60;
|
|
| 1739 |
addr -= chnum * 0x60;
|
|
| 1742 | 1740 |
break; |
| 1743 | 1741 |
|
| 1744 | 1742 |
default: |
| ... | ... | |
| 1747 | 1745 |
} |
| 1748 | 1746 |
|
| 1749 | 1747 |
/* Per-channel registers */ |
| 1750 |
switch (offset) {
|
|
| 1748 |
switch (addr) {
|
|
| 1751 | 1749 |
case 0x00: /* DMA4_CCR */ |
| 1752 | 1750 |
return (ch->buf_disable << 25) | |
| 1753 | 1751 |
(ch->src_sync << 24) | |
| ... | ... | |
| 1837 | 1835 |
uint32_t value) |
| 1838 | 1836 |
{
|
| 1839 | 1837 |
struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
| 1840 |
int chnum, irqn = 0, offset = addr - s->base;
|
|
| 1838 |
int chnum, irqn = 0; |
|
| 1841 | 1839 |
struct omap_dma_channel_s *ch; |
| 1842 | 1840 |
|
| 1843 |
switch (offset) {
|
|
| 1841 |
switch (addr) {
|
|
| 1844 | 1842 |
case 0x14: /* DMA4_IRQSTATUS_L3 */ |
| 1845 | 1843 |
irqn ++; |
| 1846 | 1844 |
case 0x10: /* DMA4_IRQSTATUS_L2 */ |
| ... | ... | |
| 1878 | 1876 |
return; |
| 1879 | 1877 |
|
| 1880 | 1878 |
case 0x80 ... 0xfff: |
| 1881 |
offset -= 0x80;
|
|
| 1882 |
chnum = offset / 0x60;
|
|
| 1879 |
addr -= 0x80;
|
|
| 1880 |
chnum = addr / 0x60;
|
|
| 1883 | 1881 |
ch = s->ch + chnum; |
| 1884 |
offset -= chnum * 0x60;
|
|
| 1882 |
addr -= chnum * 0x60;
|
|
| 1885 | 1883 |
break; |
| 1886 | 1884 |
|
| 1887 | 1885 |
case 0x00: /* DMA4_REVISION */ |
| ... | ... | |
| 1899 | 1897 |
} |
| 1900 | 1898 |
|
| 1901 | 1899 |
/* Per-channel registers */ |
| 1902 |
switch (offset) {
|
|
| 1900 |
switch (addr) {
|
|
| 1903 | 1901 |
case 0x00: /* DMA4_CCR */ |
| 1904 | 1902 |
ch->buf_disable = (value >> 25) & 1; |
| 1905 | 1903 |
ch->src_sync = (value >> 24) & 1; /* XXX For CamDMA must be 1 */ |
| ... | ... | |
| 2041 | 2039 |
struct omap_dma_s *s = (struct omap_dma_s *) |
| 2042 | 2040 |
qemu_mallocz(sizeof(struct omap_dma_s)); |
| 2043 | 2041 |
|
| 2044 |
s->base = base; |
|
| 2045 | 2042 |
s->model = omap_dma_4; |
| 2046 | 2043 |
s->chans = chans; |
| 2047 | 2044 |
s->mpu = mpu; |
| ... | ... | |
| 2068 | 2065 |
|
| 2069 | 2066 |
iomemtype = cpu_register_io_memory(0, omap_dma4_readfn, |
| 2070 | 2067 |
omap_dma4_writefn, s); |
| 2071 |
cpu_register_physical_memory(s->base, 0x1000, iomemtype);
|
|
| 2068 |
cpu_register_physical_memory(base, 0x1000, iomemtype); |
|
| 2072 | 2069 |
|
| 2073 | 2070 |
mpu->drq = s->dma->drq; |
| 2074 | 2071 |
|
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