Revision 8da3ff18 hw/ppc405_boards.c
b/hw/ppc405_boards.c | ||
---|---|---|
54 | 54 |
*/ |
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typedef struct ref405ep_fpga_t ref405ep_fpga_t; |
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struct ref405ep_fpga_t { |
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uint32_t base; |
|
58 | 57 |
uint8_t reg0; |
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uint8_t reg1; |
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}; |
... | ... | |
65 | 64 |
uint32_t ret; |
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|
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fpga = opaque; |
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addr -= fpga->base; |
|
69 | 67 |
switch (addr) { |
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case 0x0: |
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ret = fpga->reg0; |
... | ... | |
87 | 85 |
ref405ep_fpga_t *fpga; |
88 | 86 |
|
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fpga = opaque; |
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addr -= fpga->base; |
|
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switch (addr) { |
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case 0x0: |
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/* Read only */ |
... | ... | |
166 | 163 |
|
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fpga = qemu_mallocz(sizeof(ref405ep_fpga_t)); |
168 | 165 |
if (fpga != NULL) { |
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fpga->base = base; |
|
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fpga_memory = cpu_register_io_memory(0, ref405ep_fpga_read, |
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ref405ep_fpga_write, fpga); |
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cpu_register_physical_memory(base, 0x00000100, fpga_memory); |
... | ... | |
382 | 378 |
*/ |
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typedef struct taihu_cpld_t taihu_cpld_t; |
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struct taihu_cpld_t { |
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uint32_t base; |
|
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uint8_t reg0; |
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uint8_t reg1; |
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}; |
... | ... | |
393 | 388 |
uint32_t ret; |
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|
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cpld = opaque; |
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addr -= cpld->base; |
|
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switch (addr) { |
398 | 392 |
case 0x0: |
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ret = cpld->reg0; |
... | ... | |
415 | 409 |
taihu_cpld_t *cpld; |
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|
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cpld = opaque; |
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addr -= cpld->base; |
|
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switch (addr) { |
420 | 413 |
case 0x0: |
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/* Read only */ |
... | ... | |
494 | 487 |
|
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cpld = qemu_mallocz(sizeof(taihu_cpld_t)); |
496 | 489 |
if (cpld != NULL) { |
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cpld->base = base; |
|
498 | 490 |
cpld_memory = cpu_register_io_memory(0, taihu_cpld_read, |
499 | 491 |
taihu_cpld_write, cpld); |
500 | 492 |
cpu_register_physical_memory(base, 0x00000100, cpld_memory); |
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