Revision 8da3ff18 hw/pxa2xx.c
b/hw/pxa2xx.c | ||
---|---|---|
90 | 90 |
static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr) |
91 | 91 |
{ |
92 | 92 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
93 |
addr -= s->pm_base; |
|
94 | 93 |
|
95 | 94 |
switch (addr) { |
96 | 95 |
case PMCR ... PCMD31: |
... | ... | |
110 | 109 |
uint32_t value) |
111 | 110 |
{ |
112 | 111 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
113 |
addr -= s->pm_base; |
|
114 | 112 |
|
115 | 113 |
switch (addr) { |
116 | 114 |
case PMCR: |
... | ... | |
175 | 173 |
static uint32_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr) |
176 | 174 |
{ |
177 | 175 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
178 |
addr -= s->cm_base; |
|
179 | 176 |
|
180 | 177 |
switch (addr) { |
181 | 178 |
case CCCR: |
... | ... | |
197 | 194 |
uint32_t value) |
198 | 195 |
{ |
199 | 196 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
200 |
addr -= s->cm_base; |
|
201 | 197 |
|
202 | 198 |
switch (addr) { |
203 | 199 |
case CCCR: |
... | ... | |
487 | 483 |
static uint32_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr) |
488 | 484 |
{ |
489 | 485 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
490 |
addr -= s->mm_base; |
|
491 | 486 |
|
492 | 487 |
switch (addr) { |
493 | 488 |
case MDCNFG ... SA1110: |
... | ... | |
505 | 500 |
uint32_t value) |
506 | 501 |
{ |
507 | 502 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
508 |
addr -= s->mm_base; |
|
509 | 503 |
|
510 | 504 |
switch (addr) { |
511 | 505 |
case MDCNFG ... SA1110: |
... | ... | |
554 | 548 |
|
555 | 549 |
/* Synchronous Serial Ports */ |
556 | 550 |
struct pxa2xx_ssp_s { |
557 |
target_phys_addr_t base; |
|
558 | 551 |
qemu_irq irq; |
559 | 552 |
int enable; |
560 | 553 |
|
... | ... | |
668 | 661 |
{ |
669 | 662 |
struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque; |
670 | 663 |
uint32_t retval; |
671 |
addr -= s->base; |
|
672 | 664 |
|
673 | 665 |
switch (addr) { |
674 | 666 |
case SSCR0: |
... | ... | |
714 | 706 |
uint32_t value) |
715 | 707 |
{ |
716 | 708 |
struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque; |
717 |
addr -= s->base; |
|
718 | 709 |
|
719 | 710 |
switch (addr) { |
720 | 711 |
case SSCR0: |
... | ... | |
1022 | 1013 |
static uint32_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr) |
1023 | 1014 |
{ |
1024 | 1015 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
1025 |
addr -= s->rtc_base; |
|
1026 | 1016 |
|
1027 | 1017 |
switch (addr) { |
1028 | 1018 |
case RTTR: |
... | ... | |
1069 | 1059 |
uint32_t value) |
1070 | 1060 |
{ |
1071 | 1061 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
1072 |
addr -= s->rtc_base; |
|
1073 | 1062 |
|
1074 | 1063 |
switch (addr) { |
1075 | 1064 |
case RTTR: |
... | ... | |
1270 | 1259 |
struct pxa2xx_i2c_s { |
1271 | 1260 |
i2c_slave slave; |
1272 | 1261 |
i2c_bus *bus; |
1273 |
target_phys_addr_t base; |
|
1274 | 1262 |
qemu_irq irq; |
1275 | 1263 |
|
1276 | 1264 |
uint16_t control; |
... | ... | |
1351 | 1339 |
static uint32_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr) |
1352 | 1340 |
{ |
1353 | 1341 |
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque; |
1354 |
addr -= s->base; |
|
1355 | 1342 |
|
1343 |
addr &= 0xff; |
|
1356 | 1344 |
switch (addr) { |
1357 | 1345 |
case ICR: |
1358 | 1346 |
return s->control; |
... | ... | |
1380 | 1368 |
{ |
1381 | 1369 |
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque; |
1382 | 1370 |
int ack; |
1383 |
addr -= s->base; |
|
1384 | 1371 |
|
1372 |
addr &= 0xff; |
|
1385 | 1373 |
switch (addr) { |
1386 | 1374 |
case ICR: |
1387 | 1375 |
s->control = value & 0xfff7; |
... | ... | |
1493 | 1481 |
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) |
1494 | 1482 |
i2c_slave_init(i2c_init_bus(), 0, sizeof(struct pxa2xx_i2c_s)); |
1495 | 1483 |
|
1496 |
s->base = base; |
|
1497 | 1484 |
s->irq = irq; |
1498 | 1485 |
s->slave.event = pxa2xx_i2c_event; |
1499 | 1486 |
s->slave.recv = pxa2xx_i2c_rx; |
... | ... | |
1502 | 1489 |
|
1503 | 1490 |
iomemtype = cpu_register_io_memory(0, pxa2xx_i2c_readfn, |
1504 | 1491 |
pxa2xx_i2c_writefn, s); |
1505 |
cpu_register_physical_memory(s->base & ~page_size, page_size, iomemtype);
|
|
1492 |
cpu_register_physical_memory(base & ~page_size, page_size + 1, iomemtype);
|
|
1506 | 1493 |
|
1507 | 1494 |
register_savevm("pxa2xx_i2c", base, 1, |
1508 | 1495 |
pxa2xx_i2c_save, pxa2xx_i2c_load, s); |
... | ... | |
1573 | 1560 |
static uint32_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr) |
1574 | 1561 |
{ |
1575 | 1562 |
struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque; |
1576 |
addr -= s->base; |
|
1577 | 1563 |
|
1578 | 1564 |
switch (addr) { |
1579 | 1565 |
case SACR0: |
... | ... | |
1607 | 1593 |
{ |
1608 | 1594 |
struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque; |
1609 | 1595 |
uint32_t *sample; |
1610 |
addr -= s->base; |
|
1611 | 1596 |
|
1612 | 1597 |
switch (addr) { |
1613 | 1598 |
case SACR0: |
... | ... | |
1733 | 1718 |
struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) |
1734 | 1719 |
qemu_mallocz(sizeof(struct pxa2xx_i2s_s)); |
1735 | 1720 |
|
1736 |
s->base = base; |
|
1737 | 1721 |
s->irq = irq; |
1738 | 1722 |
s->dma = dma; |
1739 | 1723 |
s->data_req = pxa2xx_i2s_data_req; |
... | ... | |
1742 | 1726 |
|
1743 | 1727 |
iomemtype = cpu_register_io_memory(0, pxa2xx_i2s_readfn, |
1744 | 1728 |
pxa2xx_i2s_writefn, s); |
1745 |
cpu_register_physical_memory(s->base & 0xfff00000, 0x100000, iomemtype);
|
|
1729 |
cpu_register_physical_memory(base, 0x100000, iomemtype);
|
|
1746 | 1730 |
|
1747 | 1731 |
register_savevm("pxa2xx_i2s", base, 0, |
1748 | 1732 |
pxa2xx_i2s_save, pxa2xx_i2s_load, s); |
... | ... | |
1752 | 1736 |
|
1753 | 1737 |
/* PXA Fast Infra-red Communications Port */ |
1754 | 1738 |
struct pxa2xx_fir_s { |
1755 |
target_phys_addr_t base; |
|
1756 | 1739 |
qemu_irq irq; |
1757 | 1740 |
struct pxa2xx_dma_state_s *dma; |
1758 | 1741 |
int enable; |
... | ... | |
1826 | 1809 |
{ |
1827 | 1810 |
struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque; |
1828 | 1811 |
uint8_t ret; |
1829 |
addr -= s->base; |
|
1830 | 1812 |
|
1831 | 1813 |
switch (addr) { |
1832 | 1814 |
case ICCR0: |
... | ... | |
1865 | 1847 |
{ |
1866 | 1848 |
struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque; |
1867 | 1849 |
uint8_t ch; |
1868 |
addr -= s->base; |
|
1869 | 1850 |
|
1870 | 1851 |
switch (addr) { |
1871 | 1852 |
case ICCR0: |
... | ... | |
1996 | 1977 |
struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) |
1997 | 1978 |
qemu_mallocz(sizeof(struct pxa2xx_fir_s)); |
1998 | 1979 |
|
1999 |
s->base = base; |
|
2000 | 1980 |
s->irq = irq; |
2001 | 1981 |
s->dma = dma; |
2002 | 1982 |
s->chr = chr; |
... | ... | |
2005 | 1985 |
|
2006 | 1986 |
iomemtype = cpu_register_io_memory(0, pxa2xx_fir_readfn, |
2007 | 1987 |
pxa2xx_fir_writefn, s); |
2008 |
cpu_register_physical_memory(s->base, 0x1000, iomemtype);
|
|
1988 |
cpu_register_physical_memory(base, 0x1000, iomemtype); |
|
2009 | 1989 |
|
2010 | 1990 |
if (chr) |
2011 | 1991 |
qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty, |
... | ... | |
2118 | 2098 |
ssp = (struct pxa2xx_ssp_s *) |
2119 | 2099 |
qemu_mallocz(sizeof(struct pxa2xx_ssp_s) * i); |
2120 | 2100 |
for (i = 0; pxa27x_ssp[i].io_base; i ++) { |
2101 |
target_phys_addr_t ssp_base; |
|
2121 | 2102 |
s->ssp[i] = &ssp[i]; |
2122 |
ssp[i].base = pxa27x_ssp[i].io_base;
|
|
2103 |
ssp_base = pxa27x_ssp[i].io_base;
|
|
2123 | 2104 |
ssp[i].irq = s->pic[pxa27x_ssp[i].irqn]; |
2124 | 2105 |
|
2125 | 2106 |
iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn, |
2126 | 2107 |
pxa2xx_ssp_writefn, &ssp[i]); |
2127 |
cpu_register_physical_memory(ssp[i].base, 0x1000, iomemtype);
|
|
2108 |
cpu_register_physical_memory(ssp_base, 0x1000, iomemtype);
|
|
2128 | 2109 |
register_savevm("pxa2xx_ssp", i, 0, |
2129 | 2110 |
pxa2xx_ssp_save, pxa2xx_ssp_load, s); |
2130 | 2111 |
} |
... | ... | |
2241 | 2222 |
ssp = (struct pxa2xx_ssp_s *) |
2242 | 2223 |
qemu_mallocz(sizeof(struct pxa2xx_ssp_s) * i); |
2243 | 2224 |
for (i = 0; pxa255_ssp[i].io_base; i ++) { |
2225 |
target_phys_addr_t ssp_base; |
|
2244 | 2226 |
s->ssp[i] = &ssp[i]; |
2245 |
ssp[i].base = pxa255_ssp[i].io_base;
|
|
2227 |
ssp_base = pxa255_ssp[i].io_base;
|
|
2246 | 2228 |
ssp[i].irq = s->pic[pxa255_ssp[i].irqn]; |
2247 | 2229 |
|
2248 | 2230 |
iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn, |
2249 | 2231 |
pxa2xx_ssp_writefn, &ssp[i]); |
2250 |
cpu_register_physical_memory(ssp[i].base, 0x1000, iomemtype);
|
|
2232 |
cpu_register_physical_memory(ssp_base, 0x1000, iomemtype);
|
|
2251 | 2233 |
register_savevm("pxa2xx_ssp", i, 0, |
2252 | 2234 |
pxa2xx_ssp_save, pxa2xx_ssp_load, s); |
2253 | 2235 |
} |
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