Revision 8da3ff18 hw/pxa2xx_dma.c
| b/hw/pxa2xx_dma.c | ||
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| 25 | 25 |
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struct pxa2xx_dma_state_s {
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pxa2xx_dma_handler_t handler; |
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target_phys_addr_t base; |
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qemu_irq irq; |
| 30 | 29 |
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uint32_t stopintr; |
| ... | ... | |
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{
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struct pxa2xx_dma_state_s *s = (struct pxa2xx_dma_state_s *) opaque; |
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unsigned int channel; |
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offset -= s->base; |
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switch (offset) {
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case DRCMR64 ... DRCMR74: |
| ... | ... | |
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{
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struct pxa2xx_dma_state_s *s = (struct pxa2xx_dma_state_s *) opaque; |
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unsigned int channel; |
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offset -= s->base; |
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switch (offset) {
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case DRCMR64 ... DRCMR74: |
| ... | ... | |
| 498 | 495 |
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s->channels = channels; |
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s->chan = qemu_mallocz(sizeof(struct pxa2xx_dma_channel_s) * s->channels); |
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s->base = base; |
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s->irq = irq; |
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s->handler = (pxa2xx_dma_handler_t) pxa2xx_dma_request; |
| 504 | 500 |
s->req = qemu_mallocz(sizeof(uint8_t) * PXA2XX_DMA_NUM_REQUESTS); |
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