Revision 8da3ff18 hw/pxa2xx_pcmcia.c
| b/hw/pxa2xx_pcmcia.c | ||
|---|---|---|
| 14 | 14 |
struct pxa2xx_pcmcia_s {
|
| 15 | 15 |
struct pcmcia_socket_s slot; |
| 16 | 16 |
struct pcmcia_card_s *card; |
| 17 |
target_phys_addr_t common_base; |
|
| 18 |
target_phys_addr_t attr_base; |
|
| 19 |
target_phys_addr_t io_base; |
|
| 20 | 17 |
|
| 21 | 18 |
qemu_irq irq; |
| 22 | 19 |
qemu_irq cd_irq; |
| ... | ... | |
| 28 | 25 |
struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque; |
| 29 | 26 |
|
| 30 | 27 |
if (s->slot.attached) {
|
| 31 |
offset -= s->common_base; |
|
| 32 | 28 |
return s->card->common_read(s->card->state, offset); |
| 33 | 29 |
} |
| 34 | 30 |
|
| ... | ... | |
| 41 | 37 |
struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque; |
| 42 | 38 |
|
| 43 | 39 |
if (s->slot.attached) {
|
| 44 |
offset -= s->common_base; |
|
| 45 | 40 |
s->card->common_write(s->card->state, offset, value); |
| 46 | 41 |
} |
| 47 | 42 |
} |
| ... | ... | |
| 52 | 47 |
struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque; |
| 53 | 48 |
|
| 54 | 49 |
if (s->slot.attached) {
|
| 55 |
offset -= s->attr_base; |
|
| 56 | 50 |
return s->card->attr_read(s->card->state, offset); |
| 57 | 51 |
} |
| 58 | 52 |
|
| ... | ... | |
| 65 | 59 |
struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque; |
| 66 | 60 |
|
| 67 | 61 |
if (s->slot.attached) {
|
| 68 |
offset -= s->attr_base; |
|
| 69 | 62 |
s->card->attr_write(s->card->state, offset, value); |
| 70 | 63 |
} |
| 71 | 64 |
} |
| ... | ... | |
| 76 | 69 |
struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque; |
| 77 | 70 |
|
| 78 | 71 |
if (s->slot.attached) {
|
| 79 |
offset -= s->io_base; |
|
| 80 | 72 |
return s->card->io_read(s->card->state, offset); |
| 81 | 73 |
} |
| 82 | 74 |
|
| ... | ... | |
| 89 | 81 |
struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque; |
| 90 | 82 |
|
| 91 | 83 |
if (s->slot.attached) {
|
| 92 |
offset -= s->io_base; |
|
| 93 | 84 |
s->card->io_write(s->card->state, offset, value); |
| 94 | 85 |
} |
| 95 | 86 |
} |
| ... | ... | |
| 148 | 139 |
qemu_mallocz(sizeof(struct pxa2xx_pcmcia_s)); |
| 149 | 140 |
|
| 150 | 141 |
/* Socket I/O Memory Space */ |
| 151 |
s->io_base = base | 0x00000000; |
|
| 152 | 142 |
iomemtype = cpu_register_io_memory(0, pxa2xx_pcmcia_io_readfn, |
| 153 | 143 |
pxa2xx_pcmcia_io_writefn, s); |
| 154 |
cpu_register_physical_memory(s->io_base, 0x04000000, iomemtype);
|
|
| 144 |
cpu_register_physical_memory(base | 0x00000000, 0x04000000, iomemtype);
|
|
| 155 | 145 |
|
| 156 | 146 |
/* Then next 64 MB is reserved */ |
| 157 | 147 |
|
| 158 | 148 |
/* Socket Attribute Memory Space */ |
| 159 |
s->attr_base = base | 0x08000000; |
|
| 160 | 149 |
iomemtype = cpu_register_io_memory(0, pxa2xx_pcmcia_attr_readfn, |
| 161 | 150 |
pxa2xx_pcmcia_attr_writefn, s); |
| 162 |
cpu_register_physical_memory(s->attr_base, 0x04000000, iomemtype);
|
|
| 151 |
cpu_register_physical_memory(base | 0x08000000, 0x04000000, iomemtype);
|
|
| 163 | 152 |
|
| 164 | 153 |
/* Socket Common Memory Space */ |
| 165 |
s->common_base = base | 0x0c000000; |
|
| 166 | 154 |
iomemtype = cpu_register_io_memory(0, pxa2xx_pcmcia_common_readfn, |
| 167 | 155 |
pxa2xx_pcmcia_common_writefn, s); |
| 168 |
cpu_register_physical_memory(s->common_base, 0x04000000, iomemtype);
|
|
| 156 |
cpu_register_physical_memory(base | 0x0c000000, 0x04000000, iomemtype);
|
|
| 169 | 157 |
|
| 170 | 158 |
if (base == 0x30000000) |
| 171 | 159 |
s->slot.slot_string = "PXA PC Card Socket 1"; |
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