Archipelago » qemu

#define PXA2XX_PIC_SRCS	40

struct pxa2xx_pic_state_s {

    CPUState *cpu_env;

    uint32_t int_enabled[2];

    uint32_t int_pending[2];

static uint32_t pxa2xx_pic_mem_read(void *opaque, target_phys_addr_t offset)

{

    struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque;

    switch (offset) {

    case ICIP:	/* IRQ Pending register */

                uint32_t value)

{

    struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque;

    switch (offset) {

    case ICMR:	/* Mask register */

static uint32_t pxa2xx_pic_cp_read(void *opaque, int op2, int reg, int crm)

{

    target_phys_addr_t offset;

    if (pxa2xx_cp_reg_map[reg] == -1) {

        return 0;

    }

    return pxa2xx_pic_mem_read(opaque, offset);

}

static void pxa2xx_pic_cp_write(void *opaque, int op2, int reg, int crm,

                uint32_t value)

{

    target_phys_addr_t offset;

    if (pxa2xx_cp_reg_map[reg] == -1) {

        return;

    }

    pxa2xx_pic_mem_write(opaque, offset, value);

}

        return NULL;

    s->cpu_env = env;

    s->int_pending[0] = 0;

    s->int_pending[1] = 0;