Revision 8da3ff18 hw/sh_timer.c

b/hw/sh_timer.c
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    int level[3];
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    uint32_t tocr;
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    uint32_t tstr;
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    target_phys_addr_t base;
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    int feat;
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} tmu012_state;
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......
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#ifdef DEBUG_TIMER
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    printf("tmu012_read 0x%lx\n", (unsigned long) offset);
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#endif
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    offset -= s->base;
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    if (offset >= 0x20) {
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        if (!(s->feat & TMU012_FEAT_3CHAN))
......
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#ifdef DEBUG_TIMER
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    printf("tmu012_write 0x%lx 0x%08x\n", (unsigned long) offset, value);
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#endif
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    offset -= s->base;
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    if (offset >= 0x20) {
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        if (!(s->feat & TMU012_FEAT_3CHAN))
......
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    int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0;
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    s = (tmu012_state *)qemu_mallocz(sizeof(tmu012_state));
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    s->base = base;
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    s->feat = feat;
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    s->timer[0] = sh_timer_init(freq, timer_feat, ch0_irq);
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    s->timer[1] = sh_timer_init(freq, timer_feat, ch1_irq);

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