Revision 8da3ff18 hw/tc6393xb.c
| b/hw/tc6393xb.c | ||
|---|---|---|
| 79 | 79 |
#define NAND_MODE_ECC_RST 0x60 |
| 80 | 80 |
|
| 81 | 81 |
struct tc6393xb_s {
|
| 82 |
target_phys_addr_t target_base; |
|
| 83 | 82 |
qemu_irq irq; |
| 84 | 83 |
qemu_irq *sub_irqs; |
| 85 | 84 |
struct {
|
| ... | ... | |
| 498 | 497 |
|
| 499 | 498 |
static uint32_t tc6393xb_readb(void *opaque, target_phys_addr_t addr) {
|
| 500 | 499 |
struct tc6393xb_s *s = opaque; |
| 501 |
addr -= s->target_base; |
|
| 502 | 500 |
|
| 503 | 501 |
switch (addr >> 8) {
|
| 504 | 502 |
case 0: |
| ... | ... | |
| 520 | 518 |
|
| 521 | 519 |
static void tc6393xb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) {
|
| 522 | 520 |
struct tc6393xb_s *s = opaque; |
| 523 |
addr -= s->target_base; |
|
| 524 | 521 |
|
| 525 | 522 |
switch (addr >> 8) {
|
| 526 | 523 |
case 0: |
| ... | ... | |
| 582 | 579 |
}; |
| 583 | 580 |
|
| 584 | 581 |
s = (struct tc6393xb_s *) qemu_mallocz(sizeof(struct tc6393xb_s)); |
| 585 |
s->target_base = base; |
|
| 586 | 582 |
s->irq = irq; |
| 587 | 583 |
s->gpio_in = qemu_allocate_irqs(tc6393xb_gpio_set, s, TC6393XB_GPIOS); |
| 588 | 584 |
|
| ... | ... | |
| 595 | 591 |
|
| 596 | 592 |
iomemtype = cpu_register_io_memory(0, tc6393xb_readfn, |
| 597 | 593 |
tc6393xb_writefn, s); |
| 598 |
cpu_register_physical_memory(s->target_base, 0x10000, iomemtype);
|
|
| 594 |
cpu_register_physical_memory(base, 0x10000, iomemtype); |
|
| 599 | 595 |
|
| 600 | 596 |
if (ds) {
|
| 601 | 597 |
s->ds = ds; |
| 602 | 598 |
s->vram_addr = qemu_ram_alloc(0x100000); |
| 603 |
cpu_register_physical_memory(s->target_base + 0x100000, 0x100000, s->vram_addr);
|
|
| 599 |
cpu_register_physical_memory(base + 0x100000, 0x100000, s->vram_addr); |
|
| 604 | 600 |
s->scr_width = 480; |
| 605 | 601 |
s->scr_height = 640; |
| 606 | 602 |
s->console = graphic_console_init(ds, |
Also available in: Unified diff