root / hw / mc146818rtc.c @ 8da3ff18
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/*
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* QEMU MC146818 RTC emulation
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "qemu-timer.h" |
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#include "sysemu.h" |
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#include "pc.h" |
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#include "isa.h" |
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|
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//#define DEBUG_CMOS
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|
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#define RTC_SECONDS 0 |
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#define RTC_SECONDS_ALARM 1 |
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#define RTC_MINUTES 2 |
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#define RTC_MINUTES_ALARM 3 |
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#define RTC_HOURS 4 |
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#define RTC_HOURS_ALARM 5 |
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#define RTC_ALARM_DONT_CARE 0xC0 |
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|
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#define RTC_DAY_OF_WEEK 6 |
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#define RTC_DAY_OF_MONTH 7 |
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#define RTC_MONTH 8 |
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#define RTC_YEAR 9 |
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|
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#define RTC_REG_A 10 |
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#define RTC_REG_B 11 |
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#define RTC_REG_C 12 |
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#define RTC_REG_D 13 |
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|
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#define REG_A_UIP 0x80 |
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|
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#define REG_B_SET 0x80 |
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#define REG_B_PIE 0x40 |
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#define REG_B_AIE 0x20 |
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#define REG_B_UIE 0x10 |
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struct RTCState {
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uint8_t cmos_data[128];
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uint8_t cmos_index; |
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struct tm current_tm;
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qemu_irq irq; |
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int it_shift;
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/* periodic timer */
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QEMUTimer *periodic_timer; |
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int64_t next_periodic_time; |
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/* second update */
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int64_t next_second_time; |
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QEMUTimer *second_timer; |
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QEMUTimer *second_timer2; |
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}; |
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static void rtc_set_time(RTCState *s); |
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static void rtc_copy_date(RTCState *s); |
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static void rtc_timer_update(RTCState *s, int64_t current_time) |
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{ |
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int period_code, period;
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int64_t cur_clock, next_irq_clock; |
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period_code = s->cmos_data[RTC_REG_A] & 0x0f;
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if (period_code != 0 && |
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(s->cmos_data[RTC_REG_B] & REG_B_PIE)) { |
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if (period_code <= 2) |
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period_code += 7;
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/* period in 32 Khz cycles */
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period = 1 << (period_code - 1); |
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/* compute 32 khz clock */
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cur_clock = muldiv64(current_time, 32768, ticks_per_sec);
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next_irq_clock = (cur_clock & ~(period - 1)) + period;
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s->next_periodic_time = muldiv64(next_irq_clock, ticks_per_sec, 32768) + 1; |
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qemu_mod_timer(s->periodic_timer, s->next_periodic_time); |
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} else {
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qemu_del_timer(s->periodic_timer); |
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} |
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} |
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static void rtc_periodic_timer(void *opaque) |
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{ |
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RTCState *s = opaque; |
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|
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rtc_timer_update(s, s->next_periodic_time); |
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s->cmos_data[RTC_REG_C] |= 0xc0;
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qemu_irq_raise(s->irq); |
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} |
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static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) |
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{ |
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RTCState *s = opaque; |
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if ((addr & 1) == 0) { |
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s->cmos_index = data & 0x7f;
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} else {
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#ifdef DEBUG_CMOS
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printf("cmos: write index=0x%02x val=0x%02x\n",
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s->cmos_index, data); |
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#endif
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switch(s->cmos_index) {
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case RTC_SECONDS_ALARM:
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case RTC_MINUTES_ALARM:
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case RTC_HOURS_ALARM:
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/* XXX: not supported */
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s->cmos_data[s->cmos_index] = data; |
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break;
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case RTC_SECONDS:
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case RTC_MINUTES:
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case RTC_HOURS:
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case RTC_DAY_OF_WEEK:
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case RTC_DAY_OF_MONTH:
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case RTC_MONTH:
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case RTC_YEAR:
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s->cmos_data[s->cmos_index] = data; |
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/* if in set mode, do not update the time */
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if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
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rtc_set_time(s); |
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} |
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break;
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case RTC_REG_A:
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/* UIP bit is read only */
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s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) | |
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(s->cmos_data[RTC_REG_A] & REG_A_UIP); |
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rtc_timer_update(s, qemu_get_clock(vm_clock)); |
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break;
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case RTC_REG_B:
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if (data & REG_B_SET) {
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/* set mode: reset UIP mode */
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s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; |
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data &= ~REG_B_UIE; |
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} else {
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/* if disabling set mode, update the time */
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if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
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rtc_set_time(s); |
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} |
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} |
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s->cmos_data[RTC_REG_B] = data; |
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rtc_timer_update(s, qemu_get_clock(vm_clock)); |
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break;
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case RTC_REG_C:
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case RTC_REG_D:
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/* cannot write to them */
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break;
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default:
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s->cmos_data[s->cmos_index] = data; |
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break;
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} |
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} |
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} |
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static inline int to_bcd(RTCState *s, int a) |
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{ |
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if (s->cmos_data[RTC_REG_B] & 0x04) { |
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return a;
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} else {
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return ((a / 10) << 4) | (a % 10); |
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} |
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} |
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static inline int from_bcd(RTCState *s, int a) |
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{ |
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if (s->cmos_data[RTC_REG_B] & 0x04) { |
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return a;
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} else {
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return ((a >> 4) * 10) + (a & 0x0f); |
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} |
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} |
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static void rtc_set_time(RTCState *s) |
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{ |
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struct tm *tm = &s->current_tm;
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tm->tm_sec = from_bcd(s, s->cmos_data[RTC_SECONDS]); |
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tm->tm_min = from_bcd(s, s->cmos_data[RTC_MINUTES]); |
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tm->tm_hour = from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
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if (!(s->cmos_data[RTC_REG_B] & 0x02) && |
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(s->cmos_data[RTC_HOURS] & 0x80)) {
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tm->tm_hour += 12;
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} |
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tm->tm_wday = from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]); |
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tm->tm_mday = from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]); |
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tm->tm_mon = from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
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tm->tm_year = from_bcd(s, s->cmos_data[RTC_YEAR]) + 100;
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} |
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static void rtc_copy_date(RTCState *s) |
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{ |
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const struct tm *tm = &s->current_tm; |
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s->cmos_data[RTC_SECONDS] = to_bcd(s, tm->tm_sec); |
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s->cmos_data[RTC_MINUTES] = to_bcd(s, tm->tm_min); |
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if (s->cmos_data[RTC_REG_B] & 0x02) { |
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/* 24 hour format */
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s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour); |
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} else {
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/* 12 hour format */
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s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour % 12);
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if (tm->tm_hour >= 12) |
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s->cmos_data[RTC_HOURS] |= 0x80;
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} |
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s->cmos_data[RTC_DAY_OF_WEEK] = to_bcd(s, tm->tm_wday); |
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s->cmos_data[RTC_DAY_OF_MONTH] = to_bcd(s, tm->tm_mday); |
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s->cmos_data[RTC_MONTH] = to_bcd(s, tm->tm_mon + 1);
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s->cmos_data[RTC_YEAR] = to_bcd(s, tm->tm_year % 100);
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} |
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/* month is between 0 and 11. */
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static int get_days_in_month(int month, int year) |
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{ |
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static const int days_tab[12] = { |
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31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 |
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}; |
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int d;
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if ((unsigned )month >= 12) |
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return 31; |
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d = days_tab[month]; |
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if (month == 1) { |
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if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0)) |
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d++; |
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} |
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return d;
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} |
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/* update 'tm' to the next second */
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static void rtc_next_second(struct tm *tm) |
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{ |
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int days_in_month;
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tm->tm_sec++; |
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if ((unsigned)tm->tm_sec >= 60) { |
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tm->tm_sec = 0;
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tm->tm_min++; |
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if ((unsigned)tm->tm_min >= 60) { |
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tm->tm_min = 0;
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tm->tm_hour++; |
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if ((unsigned)tm->tm_hour >= 24) { |
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tm->tm_hour = 0;
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/* next day */
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tm->tm_wday++; |
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if ((unsigned)tm->tm_wday >= 7) |
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tm->tm_wday = 0;
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days_in_month = get_days_in_month(tm->tm_mon, |
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tm->tm_year + 1900);
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tm->tm_mday++; |
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if (tm->tm_mday < 1) { |
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tm->tm_mday = 1;
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} else if (tm->tm_mday > days_in_month) { |
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tm->tm_mday = 1;
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tm->tm_mon++; |
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if (tm->tm_mon >= 12) { |
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tm->tm_mon = 0;
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tm->tm_year++; |
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} |
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} |
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} |
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} |
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} |
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} |
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|
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static void rtc_update_second(void *opaque) |
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{ |
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RTCState *s = opaque; |
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int64_t delay; |
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|
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/* if the oscillator is not in normal operation, we do not update */
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if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) { |
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s->next_second_time += ticks_per_sec; |
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qemu_mod_timer(s->second_timer, s->next_second_time); |
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} else {
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rtc_next_second(&s->current_tm); |
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if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
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/* update in progress bit */
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s->cmos_data[RTC_REG_A] |= REG_A_UIP; |
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} |
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/* should be 244 us = 8 / 32768 seconds, but currently the
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timers do not have the necessary resolution. */
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delay = (ticks_per_sec * 1) / 100; |
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if (delay < 1) |
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delay = 1;
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qemu_mod_timer(s->second_timer2, |
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s->next_second_time + delay); |
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} |
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} |
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static void rtc_update_second2(void *opaque) |
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{ |
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RTCState *s = opaque; |
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if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
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rtc_copy_date(s); |
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} |
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|
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/* check alarm */
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if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
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if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 || |
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s->cmos_data[RTC_SECONDS_ALARM] == s->current_tm.tm_sec) && |
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((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 || |
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s->cmos_data[RTC_MINUTES_ALARM] == s->current_tm.tm_mon) && |
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((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 || |
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s->cmos_data[RTC_HOURS_ALARM] == s->current_tm.tm_hour)) { |
320 |
|
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s->cmos_data[RTC_REG_C] |= 0xa0;
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qemu_irq_raise(s->irq); |
323 |
} |
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} |
325 |
|
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/* update ended interrupt */
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if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
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s->cmos_data[RTC_REG_C] |= 0x90;
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qemu_irq_raise(s->irq); |
330 |
} |
331 |
|
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/* clear update in progress bit */
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s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; |
334 |
|
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s->next_second_time += ticks_per_sec; |
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qemu_mod_timer(s->second_timer, s->next_second_time); |
337 |
} |
338 |
|
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static uint32_t cmos_ioport_read(void *opaque, uint32_t addr) |
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{ |
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RTCState *s = opaque; |
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int ret;
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if ((addr & 1) == 0) { |
344 |
return 0xff; |
345 |
} else {
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switch(s->cmos_index) {
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case RTC_SECONDS:
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case RTC_MINUTES:
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case RTC_HOURS:
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case RTC_DAY_OF_WEEK:
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case RTC_DAY_OF_MONTH:
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case RTC_MONTH:
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case RTC_YEAR:
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ret = s->cmos_data[s->cmos_index]; |
355 |
break;
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case RTC_REG_A:
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ret = s->cmos_data[s->cmos_index]; |
358 |
break;
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case RTC_REG_C:
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ret = s->cmos_data[s->cmos_index]; |
361 |
qemu_irq_lower(s->irq); |
362 |
s->cmos_data[RTC_REG_C] = 0x00;
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break;
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default:
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ret = s->cmos_data[s->cmos_index]; |
366 |
break;
|
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} |
368 |
#ifdef DEBUG_CMOS
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printf("cmos: read index=0x%02x val=0x%02x\n",
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s->cmos_index, ret); |
371 |
#endif
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return ret;
|
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} |
374 |
} |
375 |
|
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void rtc_set_memory(RTCState *s, int addr, int val) |
377 |
{ |
378 |
if (addr >= 0 && addr <= 127) |
379 |
s->cmos_data[addr] = val; |
380 |
} |
381 |
|
382 |
void rtc_set_date(RTCState *s, const struct tm *tm) |
383 |
{ |
384 |
s->current_tm = *tm; |
385 |
rtc_copy_date(s); |
386 |
} |
387 |
|
388 |
/* PC cmos mappings */
|
389 |
#define REG_IBM_CENTURY_BYTE 0x32 |
390 |
#define REG_IBM_PS2_CENTURY_BYTE 0x37 |
391 |
|
392 |
static void rtc_set_date_from_host(RTCState *s) |
393 |
{ |
394 |
struct tm tm;
|
395 |
int val;
|
396 |
|
397 |
/* set the CMOS date */
|
398 |
qemu_get_timedate(&tm, 0);
|
399 |
rtc_set_date(s, &tm); |
400 |
|
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val = to_bcd(s, (tm.tm_year / 100) + 19); |
402 |
rtc_set_memory(s, REG_IBM_CENTURY_BYTE, val); |
403 |
rtc_set_memory(s, REG_IBM_PS2_CENTURY_BYTE, val); |
404 |
} |
405 |
|
406 |
static void rtc_save(QEMUFile *f, void *opaque) |
407 |
{ |
408 |
RTCState *s = opaque; |
409 |
|
410 |
qemu_put_buffer(f, s->cmos_data, 128);
|
411 |
qemu_put_8s(f, &s->cmos_index); |
412 |
|
413 |
qemu_put_be32(f, s->current_tm.tm_sec); |
414 |
qemu_put_be32(f, s->current_tm.tm_min); |
415 |
qemu_put_be32(f, s->current_tm.tm_hour); |
416 |
qemu_put_be32(f, s->current_tm.tm_wday); |
417 |
qemu_put_be32(f, s->current_tm.tm_mday); |
418 |
qemu_put_be32(f, s->current_tm.tm_mon); |
419 |
qemu_put_be32(f, s->current_tm.tm_year); |
420 |
|
421 |
qemu_put_timer(f, s->periodic_timer); |
422 |
qemu_put_be64(f, s->next_periodic_time); |
423 |
|
424 |
qemu_put_be64(f, s->next_second_time); |
425 |
qemu_put_timer(f, s->second_timer); |
426 |
qemu_put_timer(f, s->second_timer2); |
427 |
} |
428 |
|
429 |
static int rtc_load(QEMUFile *f, void *opaque, int version_id) |
430 |
{ |
431 |
RTCState *s = opaque; |
432 |
|
433 |
if (version_id != 1) |
434 |
return -EINVAL;
|
435 |
|
436 |
qemu_get_buffer(f, s->cmos_data, 128);
|
437 |
qemu_get_8s(f, &s->cmos_index); |
438 |
|
439 |
s->current_tm.tm_sec=qemu_get_be32(f); |
440 |
s->current_tm.tm_min=qemu_get_be32(f); |
441 |
s->current_tm.tm_hour=qemu_get_be32(f); |
442 |
s->current_tm.tm_wday=qemu_get_be32(f); |
443 |
s->current_tm.tm_mday=qemu_get_be32(f); |
444 |
s->current_tm.tm_mon=qemu_get_be32(f); |
445 |
s->current_tm.tm_year=qemu_get_be32(f); |
446 |
|
447 |
qemu_get_timer(f, s->periodic_timer); |
448 |
s->next_periodic_time=qemu_get_be64(f); |
449 |
|
450 |
s->next_second_time=qemu_get_be64(f); |
451 |
qemu_get_timer(f, s->second_timer); |
452 |
qemu_get_timer(f, s->second_timer2); |
453 |
return 0; |
454 |
} |
455 |
|
456 |
RTCState *rtc_init(int base, qemu_irq irq)
|
457 |
{ |
458 |
RTCState *s; |
459 |
|
460 |
s = qemu_mallocz(sizeof(RTCState));
|
461 |
if (!s)
|
462 |
return NULL; |
463 |
|
464 |
s->irq = irq; |
465 |
s->cmos_data[RTC_REG_A] = 0x26;
|
466 |
s->cmos_data[RTC_REG_B] = 0x02;
|
467 |
s->cmos_data[RTC_REG_C] = 0x00;
|
468 |
s->cmos_data[RTC_REG_D] = 0x80;
|
469 |
|
470 |
rtc_set_date_from_host(s); |
471 |
|
472 |
s->periodic_timer = qemu_new_timer(vm_clock, |
473 |
rtc_periodic_timer, s); |
474 |
s->second_timer = qemu_new_timer(vm_clock, |
475 |
rtc_update_second, s); |
476 |
s->second_timer2 = qemu_new_timer(vm_clock, |
477 |
rtc_update_second2, s); |
478 |
|
479 |
s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100; |
480 |
qemu_mod_timer(s->second_timer2, s->next_second_time); |
481 |
|
482 |
register_ioport_write(base, 2, 1, cmos_ioport_write, s); |
483 |
register_ioport_read(base, 2, 1, cmos_ioport_read, s); |
484 |
|
485 |
register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s); |
486 |
return s;
|
487 |
} |
488 |
|
489 |
/* Memory mapped interface */
|
490 |
static uint32_t cmos_mm_readb (void *opaque, target_phys_addr_t addr) |
491 |
{ |
492 |
RTCState *s = opaque; |
493 |
|
494 |
return cmos_ioport_read(s, addr >> s->it_shift) & 0xFF; |
495 |
} |
496 |
|
497 |
static void cmos_mm_writeb (void *opaque, |
498 |
target_phys_addr_t addr, uint32_t value) |
499 |
{ |
500 |
RTCState *s = opaque; |
501 |
|
502 |
cmos_ioport_write(s, addr >> s->it_shift, value & 0xFF);
|
503 |
} |
504 |
|
505 |
static uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr) |
506 |
{ |
507 |
RTCState *s = opaque; |
508 |
uint32_t val; |
509 |
|
510 |
val = cmos_ioport_read(s, addr >> s->it_shift) & 0xFFFF;
|
511 |
#ifdef TARGET_WORDS_BIGENDIAN
|
512 |
val = bswap16(val); |
513 |
#endif
|
514 |
return val;
|
515 |
} |
516 |
|
517 |
static void cmos_mm_writew (void *opaque, |
518 |
target_phys_addr_t addr, uint32_t value) |
519 |
{ |
520 |
RTCState *s = opaque; |
521 |
#ifdef TARGET_WORDS_BIGENDIAN
|
522 |
value = bswap16(value); |
523 |
#endif
|
524 |
cmos_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
|
525 |
} |
526 |
|
527 |
static uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr) |
528 |
{ |
529 |
RTCState *s = opaque; |
530 |
uint32_t val; |
531 |
|
532 |
val = cmos_ioport_read(s, addr >> s->it_shift); |
533 |
#ifdef TARGET_WORDS_BIGENDIAN
|
534 |
val = bswap32(val); |
535 |
#endif
|
536 |
return val;
|
537 |
} |
538 |
|
539 |
static void cmos_mm_writel (void *opaque, |
540 |
target_phys_addr_t addr, uint32_t value) |
541 |
{ |
542 |
RTCState *s = opaque; |
543 |
#ifdef TARGET_WORDS_BIGENDIAN
|
544 |
value = bswap32(value); |
545 |
#endif
|
546 |
cmos_ioport_write(s, addr >> s->it_shift, value); |
547 |
} |
548 |
|
549 |
static CPUReadMemoryFunc *rtc_mm_read[] = {
|
550 |
&cmos_mm_readb, |
551 |
&cmos_mm_readw, |
552 |
&cmos_mm_readl, |
553 |
}; |
554 |
|
555 |
static CPUWriteMemoryFunc *rtc_mm_write[] = {
|
556 |
&cmos_mm_writeb, |
557 |
&cmos_mm_writew, |
558 |
&cmos_mm_writel, |
559 |
}; |
560 |
|
561 |
RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq)
|
562 |
{ |
563 |
RTCState *s; |
564 |
int io_memory;
|
565 |
|
566 |
s = qemu_mallocz(sizeof(RTCState));
|
567 |
if (!s)
|
568 |
return NULL; |
569 |
|
570 |
s->irq = irq; |
571 |
s->cmos_data[RTC_REG_A] = 0x26;
|
572 |
s->cmos_data[RTC_REG_B] = 0x02;
|
573 |
s->cmos_data[RTC_REG_C] = 0x00;
|
574 |
s->cmos_data[RTC_REG_D] = 0x80;
|
575 |
|
576 |
rtc_set_date_from_host(s); |
577 |
|
578 |
s->periodic_timer = qemu_new_timer(vm_clock, |
579 |
rtc_periodic_timer, s); |
580 |
s->second_timer = qemu_new_timer(vm_clock, |
581 |
rtc_update_second, s); |
582 |
s->second_timer2 = qemu_new_timer(vm_clock, |
583 |
rtc_update_second2, s); |
584 |
|
585 |
s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100; |
586 |
qemu_mod_timer(s->second_timer2, s->next_second_time); |
587 |
|
588 |
io_memory = cpu_register_io_memory(0, rtc_mm_read, rtc_mm_write, s);
|
589 |
cpu_register_physical_memory(base, 2 << it_shift, io_memory);
|
590 |
|
591 |
register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s); |
592 |
return s;
|
593 |
} |