root / hw / sh_timer.c @ 8e31bf38
History | View | Annotate | Download (8.6 kB)
1 |
/*
|
---|---|
2 |
* SuperH Timer modules.
|
3 |
*
|
4 |
* Copyright (c) 2007 Magnus Damm
|
5 |
* Based on arm_timer.c by Paul Brook
|
6 |
* Copyright (c) 2005-2006 CodeSourcery.
|
7 |
*
|
8 |
* This code is licensed under the GPL.
|
9 |
*/
|
10 |
|
11 |
#include "hw.h" |
12 |
#include "sh.h" |
13 |
#include "qemu-timer.h" |
14 |
|
15 |
//#define DEBUG_TIMER
|
16 |
|
17 |
#define TIMER_TCR_TPSC (7 << 0) |
18 |
#define TIMER_TCR_CKEG (3 << 3) |
19 |
#define TIMER_TCR_UNIE (1 << 5) |
20 |
#define TIMER_TCR_ICPE (3 << 6) |
21 |
#define TIMER_TCR_UNF (1 << 8) |
22 |
#define TIMER_TCR_ICPF (1 << 9) |
23 |
#define TIMER_TCR_RESERVED (0x3f << 10) |
24 |
|
25 |
#define TIMER_FEAT_CAPT (1 << 0) |
26 |
#define TIMER_FEAT_EXTCLK (1 << 1) |
27 |
|
28 |
#define OFFSET_TCOR 0 |
29 |
#define OFFSET_TCNT 1 |
30 |
#define OFFSET_TCR 2 |
31 |
#define OFFSET_TCPR 3 |
32 |
|
33 |
typedef struct { |
34 |
ptimer_state *timer; |
35 |
uint32_t tcnt; |
36 |
uint32_t tcor; |
37 |
uint32_t tcr; |
38 |
uint32_t tcpr; |
39 |
int freq;
|
40 |
int int_level;
|
41 |
int old_level;
|
42 |
int feat;
|
43 |
int enabled;
|
44 |
qemu_irq irq; |
45 |
} sh_timer_state; |
46 |
|
47 |
/* Check all active timers, and schedule the next timer interrupt. */
|
48 |
|
49 |
static void sh_timer_update(sh_timer_state *s) |
50 |
{ |
51 |
int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE);
|
52 |
|
53 |
if (new_level != s->old_level)
|
54 |
qemu_set_irq (s->irq, new_level); |
55 |
|
56 |
s->old_level = s->int_level; |
57 |
s->int_level = new_level; |
58 |
} |
59 |
|
60 |
static uint32_t sh_timer_read(void *opaque, target_phys_addr_t offset) |
61 |
{ |
62 |
sh_timer_state *s = (sh_timer_state *)opaque; |
63 |
|
64 |
switch (offset >> 2) { |
65 |
case OFFSET_TCOR:
|
66 |
return s->tcor;
|
67 |
case OFFSET_TCNT:
|
68 |
return ptimer_get_count(s->timer);
|
69 |
case OFFSET_TCR:
|
70 |
return s->tcr | (s->int_level ? TIMER_TCR_UNF : 0); |
71 |
case OFFSET_TCPR:
|
72 |
if (s->feat & TIMER_FEAT_CAPT)
|
73 |
return s->tcpr;
|
74 |
default:
|
75 |
hw_error("sh_timer_read: Bad offset %x\n", (int)offset); |
76 |
return 0; |
77 |
} |
78 |
} |
79 |
|
80 |
static void sh_timer_write(void *opaque, target_phys_addr_t offset, |
81 |
uint32_t value) |
82 |
{ |
83 |
sh_timer_state *s = (sh_timer_state *)opaque; |
84 |
int freq;
|
85 |
|
86 |
switch (offset >> 2) { |
87 |
case OFFSET_TCOR:
|
88 |
s->tcor = value; |
89 |
ptimer_set_limit(s->timer, s->tcor, 0);
|
90 |
break;
|
91 |
case OFFSET_TCNT:
|
92 |
s->tcnt = value; |
93 |
ptimer_set_count(s->timer, s->tcnt); |
94 |
break;
|
95 |
case OFFSET_TCR:
|
96 |
if (s->enabled) {
|
97 |
/* Pause the timer if it is running. This may cause some
|
98 |
inaccuracy dure to rounding, but avoids a whole lot of other
|
99 |
messyness. */
|
100 |
ptimer_stop(s->timer); |
101 |
} |
102 |
freq = s->freq; |
103 |
/* ??? Need to recalculate expiry time after changing divisor. */
|
104 |
switch (value & TIMER_TCR_TPSC) {
|
105 |
case 0: freq >>= 2; break; |
106 |
case 1: freq >>= 4; break; |
107 |
case 2: freq >>= 6; break; |
108 |
case 3: freq >>= 8; break; |
109 |
case 4: freq >>= 10; break; |
110 |
case 6: |
111 |
case 7: if (s->feat & TIMER_FEAT_EXTCLK) break; |
112 |
default: hw_error("sh_timer_write: Reserved TPSC value\n"); break; |
113 |
} |
114 |
switch ((value & TIMER_TCR_CKEG) >> 3) { |
115 |
case 0: break; |
116 |
case 1: |
117 |
case 2: |
118 |
case 3: if (s->feat & TIMER_FEAT_EXTCLK) break; |
119 |
default: hw_error("sh_timer_write: Reserved CKEG value\n"); break; |
120 |
} |
121 |
switch ((value & TIMER_TCR_ICPE) >> 6) { |
122 |
case 0: break; |
123 |
case 2: |
124 |
case 3: if (s->feat & TIMER_FEAT_CAPT) break; |
125 |
default: hw_error("sh_timer_write: Reserved ICPE value\n"); break; |
126 |
} |
127 |
if ((value & TIMER_TCR_UNF) == 0) |
128 |
s->int_level = 0;
|
129 |
|
130 |
value &= ~TIMER_TCR_UNF; |
131 |
|
132 |
if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT)))
|
133 |
hw_error("sh_timer_write: Reserved ICPF value\n");
|
134 |
|
135 |
value &= ~TIMER_TCR_ICPF; /* capture not supported */
|
136 |
|
137 |
if (value & TIMER_TCR_RESERVED)
|
138 |
hw_error("sh_timer_write: Reserved TCR bits set\n");
|
139 |
s->tcr = value; |
140 |
ptimer_set_limit(s->timer, s->tcor, 0);
|
141 |
ptimer_set_freq(s->timer, freq); |
142 |
if (s->enabled) {
|
143 |
/* Restart the timer if still enabled. */
|
144 |
ptimer_run(s->timer, 0);
|
145 |
} |
146 |
break;
|
147 |
case OFFSET_TCPR:
|
148 |
if (s->feat & TIMER_FEAT_CAPT) {
|
149 |
s->tcpr = value; |
150 |
break;
|
151 |
} |
152 |
default:
|
153 |
hw_error("sh_timer_write: Bad offset %x\n", (int)offset); |
154 |
} |
155 |
sh_timer_update(s); |
156 |
} |
157 |
|
158 |
static void sh_timer_start_stop(void *opaque, int enable) |
159 |
{ |
160 |
sh_timer_state *s = (sh_timer_state *)opaque; |
161 |
|
162 |
#ifdef DEBUG_TIMER
|
163 |
printf("sh_timer_start_stop %d (%d)\n", enable, s->enabled);
|
164 |
#endif
|
165 |
|
166 |
if (s->enabled && !enable) {
|
167 |
ptimer_stop(s->timer); |
168 |
} |
169 |
if (!s->enabled && enable) {
|
170 |
ptimer_run(s->timer, 0);
|
171 |
} |
172 |
s->enabled = !!enable; |
173 |
|
174 |
#ifdef DEBUG_TIMER
|
175 |
printf("sh_timer_start_stop done %d\n", s->enabled);
|
176 |
#endif
|
177 |
} |
178 |
|
179 |
static void sh_timer_tick(void *opaque) |
180 |
{ |
181 |
sh_timer_state *s = (sh_timer_state *)opaque; |
182 |
s->int_level = s->enabled; |
183 |
sh_timer_update(s); |
184 |
} |
185 |
|
186 |
static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq) |
187 |
{ |
188 |
sh_timer_state *s; |
189 |
QEMUBH *bh; |
190 |
|
191 |
s = (sh_timer_state *)qemu_mallocz(sizeof(sh_timer_state));
|
192 |
s->freq = freq; |
193 |
s->feat = feat; |
194 |
s->tcor = 0xffffffff;
|
195 |
s->tcnt = 0xffffffff;
|
196 |
s->tcpr = 0xdeadbeef;
|
197 |
s->tcr = 0;
|
198 |
s->enabled = 0;
|
199 |
s->irq = irq; |
200 |
|
201 |
bh = qemu_bh_new(sh_timer_tick, s); |
202 |
s->timer = ptimer_init(bh); |
203 |
|
204 |
sh_timer_write(s, OFFSET_TCOR >> 2, s->tcor);
|
205 |
sh_timer_write(s, OFFSET_TCNT >> 2, s->tcnt);
|
206 |
sh_timer_write(s, OFFSET_TCPR >> 2, s->tcpr);
|
207 |
sh_timer_write(s, OFFSET_TCR >> 2, s->tcpr);
|
208 |
/* ??? Save/restore. */
|
209 |
return s;
|
210 |
} |
211 |
|
212 |
typedef struct { |
213 |
void *timer[3]; |
214 |
int level[3]; |
215 |
uint32_t tocr; |
216 |
uint32_t tstr; |
217 |
int feat;
|
218 |
} tmu012_state; |
219 |
|
220 |
static uint32_t tmu012_read(void *opaque, target_phys_addr_t offset) |
221 |
{ |
222 |
tmu012_state *s = (tmu012_state *)opaque; |
223 |
|
224 |
#ifdef DEBUG_TIMER
|
225 |
printf("tmu012_read 0x%lx\n", (unsigned long) offset); |
226 |
#endif
|
227 |
|
228 |
if (offset >= 0x20) { |
229 |
if (!(s->feat & TMU012_FEAT_3CHAN))
|
230 |
hw_error("tmu012_write: Bad channel offset %x\n", (int)offset); |
231 |
return sh_timer_read(s->timer[2], offset - 0x20); |
232 |
} |
233 |
|
234 |
if (offset >= 0x14) |
235 |
return sh_timer_read(s->timer[1], offset - 0x14); |
236 |
|
237 |
if (offset >= 0x08) |
238 |
return sh_timer_read(s->timer[0], offset - 0x08); |
239 |
|
240 |
if (offset == 4) |
241 |
return s->tstr;
|
242 |
|
243 |
if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) |
244 |
return s->tocr;
|
245 |
|
246 |
hw_error("tmu012_write: Bad offset %x\n", (int)offset); |
247 |
return 0; |
248 |
} |
249 |
|
250 |
static void tmu012_write(void *opaque, target_phys_addr_t offset, |
251 |
uint32_t value) |
252 |
{ |
253 |
tmu012_state *s = (tmu012_state *)opaque; |
254 |
|
255 |
#ifdef DEBUG_TIMER
|
256 |
printf("tmu012_write 0x%lx 0x%08x\n", (unsigned long) offset, value); |
257 |
#endif
|
258 |
|
259 |
if (offset >= 0x20) { |
260 |
if (!(s->feat & TMU012_FEAT_3CHAN))
|
261 |
hw_error("tmu012_write: Bad channel offset %x\n", (int)offset); |
262 |
sh_timer_write(s->timer[2], offset - 0x20, value); |
263 |
return;
|
264 |
} |
265 |
|
266 |
if (offset >= 0x14) { |
267 |
sh_timer_write(s->timer[1], offset - 0x14, value); |
268 |
return;
|
269 |
} |
270 |
|
271 |
if (offset >= 0x08) { |
272 |
sh_timer_write(s->timer[0], offset - 0x08, value); |
273 |
return;
|
274 |
} |
275 |
|
276 |
if (offset == 4) { |
277 |
sh_timer_start_stop(s->timer[0], value & (1 << 0)); |
278 |
sh_timer_start_stop(s->timer[1], value & (1 << 1)); |
279 |
if (s->feat & TMU012_FEAT_3CHAN)
|
280 |
sh_timer_start_stop(s->timer[2], value & (1 << 2)); |
281 |
else
|
282 |
if (value & (1 << 2)) |
283 |
hw_error("tmu012_write: Bad channel\n");
|
284 |
|
285 |
s->tstr = value; |
286 |
return;
|
287 |
} |
288 |
|
289 |
if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) { |
290 |
s->tocr = value & (1 << 0); |
291 |
} |
292 |
} |
293 |
|
294 |
static CPUReadMemoryFunc * const tmu012_readfn[] = { |
295 |
tmu012_read, |
296 |
tmu012_read, |
297 |
tmu012_read |
298 |
}; |
299 |
|
300 |
static CPUWriteMemoryFunc * const tmu012_writefn[] = { |
301 |
tmu012_write, |
302 |
tmu012_write, |
303 |
tmu012_write |
304 |
}; |
305 |
|
306 |
void tmu012_init(target_phys_addr_t base, int feat, uint32_t freq, |
307 |
qemu_irq ch0_irq, qemu_irq ch1_irq, |
308 |
qemu_irq ch2_irq0, qemu_irq ch2_irq1) |
309 |
{ |
310 |
int iomemtype;
|
311 |
tmu012_state *s; |
312 |
int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0; |
313 |
|
314 |
s = (tmu012_state *)qemu_mallocz(sizeof(tmu012_state));
|
315 |
s->feat = feat; |
316 |
s->timer[0] = sh_timer_init(freq, timer_feat, ch0_irq);
|
317 |
s->timer[1] = sh_timer_init(freq, timer_feat, ch1_irq);
|
318 |
if (feat & TMU012_FEAT_3CHAN)
|
319 |
s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT,
|
320 |
ch2_irq0); /* ch2_irq1 not supported */
|
321 |
iomemtype = cpu_register_io_memory(tmu012_readfn, |
322 |
tmu012_writefn, s, |
323 |
DEVICE_NATIVE_ENDIAN); |
324 |
cpu_register_physical_memory(P4ADDR(base), 0x00001000, iomemtype);
|
325 |
cpu_register_physical_memory(A7ADDR(base), 0x00001000, iomemtype);
|
326 |
/* ??? Save/restore. */
|
327 |
} |