Revision 8e71621f target-arm/helper.c
| b/target-arm/helper.c | ||
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#else |
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extern int semihosting_enabled; |
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/* Map CPU modes onto saved register banks. */ |
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static inline int bank_number (int mode) |
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{
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| ... | ... | |
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offset = 4; |
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break; |
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case EXCP_SWI: |
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if (semihosting_enabled) {
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/* Check for semihosting interrupt. */ |
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if (env->thumb) {
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mask = lduw_code(env->regs[15] - 2) & 0xff; |
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} else {
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mask = ldl_code(env->regs[15] - 4) & 0xffffff; |
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} |
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/* Only intercept calls from privileged modes, to provide some |
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semblance of security. */ |
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if (((mask == 0x123456 && !env->thumb) |
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|| (mask == 0xab && env->thumb)) |
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&& (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
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env->regs[0] = do_arm_semihosting(env); |
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return; |
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} |
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} |
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new_mode = ARM_CPU_MODE_SVC; |
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addr = 0x08; |
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mask = CPSR_I; |
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