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/*
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* QEMU PowerPC 405 embedded processors emulation
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*
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h"
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extern int loglevel;
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extern FILE *logfile;
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#define DEBUG_MMIO
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#define DEBUG_OPBA
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#define DEBUG_SDRAM
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#define DEBUG_GPIO
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#define DEBUG_SERIAL
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#define DEBUG_OCM
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#define DEBUG_I2C
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#define DEBUG_UIC
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#define DEBUG_CLOCKS
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#define DEBUG_UNASSIGNED
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/*****************************************************************************/
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/* Generic PowerPC 405 processor instanciation */
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CPUState *ppc405_init (const unsigned char *cpu_model,
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clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
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uint32_t sysclk)
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{
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CPUState *env;
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ppc_def_t *def;
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/* init CPUs */
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env = cpu_init();
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qemu_register_reset(&cpu_ppc_reset, env);
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register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
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ppc_find_by_name(cpu_model, &def);
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if (def == NULL) {
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cpu_abort(env, "Unable to find PowerPC %s CPU definition\n",
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cpu_model);
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}
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cpu_ppc_register(env, def);
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cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */
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cpu_clk->opaque = env;
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/* Set time-base frequency to sysclk */
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tb_clk->cb = ppc_emb_timers_init(env, sysclk);
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tb_clk->opaque = env;
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ppc_dcr_init(env, NULL, NULL);
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return env;
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}
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/*****************************************************************************/
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/* Shared peripherals */
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/*****************************************************************************/
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/* Fake device used to map multiple devices in a single memory page */
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#define MMIO_AREA_BITS 8
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#define MMIO_AREA_LEN (1 << MMIO_AREA_BITS)
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#define MMIO_AREA_NB (1 << (TARGET_PAGE_BITS - MMIO_AREA_BITS))
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#define MMIO_IDX(addr) (((addr) >> MMIO_AREA_BITS) & (MMIO_AREA_NB - 1))
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struct ppc4xx_mmio_t {
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uint32_t base;
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CPUReadMemoryFunc **mem_read[MMIO_AREA_NB];
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CPUWriteMemoryFunc **mem_write[MMIO_AREA_NB];
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void *opaque[MMIO_AREA_NB];
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};
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static uint32_t unassigned_mem_readb (void *opaque, target_phys_addr_t addr)
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{
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#ifdef DEBUG_UNASSIGNED
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printf("Unassigned mem read 0x" PADDRX "\n", addr);
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#endif
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return 0;
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}
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static void unassigned_mem_writeb (void *opaque,
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target_phys_addr_t addr, uint32_t val)
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{
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#ifdef DEBUG_UNASSIGNED
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printf("Unassigned mem write 0x" PADDRX " = 0x%x\n", addr, val);
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#endif
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}
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static CPUReadMemoryFunc *unassigned_mem_read[3] = {
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unassigned_mem_readb,
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unassigned_mem_readb,
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unassigned_mem_readb,
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};
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static CPUWriteMemoryFunc *unassigned_mem_write[3] = {
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unassigned_mem_writeb,
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unassigned_mem_writeb,
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unassigned_mem_writeb,
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};
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static uint32_t mmio_readlen (ppc4xx_mmio_t *mmio,
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target_phys_addr_t addr, int len)
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{
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CPUReadMemoryFunc **mem_read;
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uint32_t ret;
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int idx;
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idx = MMIO_IDX(addr - mmio->base);
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#if defined(DEBUG_MMIO)
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printf("%s: mmio %p len %d addr " PADDRX " idx %d\n", __func__,
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mmio, len, addr, idx);
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#endif
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mem_read = mmio->mem_read[idx];
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ret = (*mem_read[len])(mmio->opaque[idx], addr);
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return ret;
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}
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static void mmio_writelen (ppc4xx_mmio_t *mmio,
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target_phys_addr_t addr, uint32_t value, int len)
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{
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CPUWriteMemoryFunc **mem_write;
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int idx;
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idx = MMIO_IDX(addr - mmio->base);
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#if defined(DEBUG_MMIO)
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printf("%s: mmio %p len %d addr " PADDRX " idx %d value %08x\n", __func__,
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mmio, len, addr, idx, value);
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#endif
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mem_write = mmio->mem_write[idx];
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(*mem_write[len])(mmio->opaque[idx], addr, value);
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}
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static uint32_t mmio_readb (void *opaque, target_phys_addr_t addr)
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{
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#if defined(DEBUG_MMIO)
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printf("%s: addr " PADDRX "\n", __func__, addr);
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#endif
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return mmio_readlen(opaque, addr, 0);
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}
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static void mmio_writeb (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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#if defined(DEBUG_MMIO)
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printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
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#endif
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mmio_writelen(opaque, addr, value, 0);
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}
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static uint32_t mmio_readw (void *opaque, target_phys_addr_t addr)
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{
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#if defined(DEBUG_MMIO)
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printf("%s: addr " PADDRX "\n", __func__, addr);
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#endif
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return mmio_readlen(opaque, addr, 1);
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}
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static void mmio_writew (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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#if defined(DEBUG_MMIO)
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printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
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#endif
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mmio_writelen(opaque, addr, value, 1);
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}
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static uint32_t mmio_readl (void *opaque, target_phys_addr_t addr)
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{
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#if defined(DEBUG_MMIO)
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printf("%s: addr " PADDRX "\n", __func__, addr);
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#endif
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return mmio_readlen(opaque, addr, 2);
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}
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static void mmio_writel (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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#if defined(DEBUG_MMIO)
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printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
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#endif
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mmio_writelen(opaque, addr, value, 2);
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}
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static CPUReadMemoryFunc *mmio_read[] = {
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&mmio_readb,
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&mmio_readw,
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&mmio_readl,
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};
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static CPUWriteMemoryFunc *mmio_write[] = {
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&mmio_writeb,
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&mmio_writew,
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&mmio_writel,
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};
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int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
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uint32_t offset, uint32_t len,
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CPUReadMemoryFunc **mem_read,
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CPUWriteMemoryFunc **mem_write, void *opaque)
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{
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uint32_t end;
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int idx, eidx;
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if ((offset + len) > TARGET_PAGE_SIZE)
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return -1;
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idx = MMIO_IDX(offset);
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end = offset + len - 1;
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eidx = MMIO_IDX(end);
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#if defined(DEBUG_MMIO)
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printf("%s: offset %08x len %08x %08x %d %d\n", __func__, offset, len,
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end, idx, eidx);
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#endif
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for (; idx <= eidx; idx++) {
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mmio->mem_read[idx] = mem_read;
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mmio->mem_write[idx] = mem_write;
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mmio->opaque[idx] = opaque;
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}
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return 0;
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}
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ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, uint32_t base)
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{
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ppc4xx_mmio_t *mmio;
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int mmio_memory;
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mmio = qemu_mallocz(sizeof(ppc4xx_mmio_t));
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if (mmio != NULL) {
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mmio->base = base;
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mmio_memory = cpu_register_io_memory(0, mmio_read, mmio_write, mmio);
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#if defined(DEBUG_MMIO)
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printf("%s: %p base %08x len %08x %d\n", __func__,
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mmio, base, TARGET_PAGE_SIZE, mmio_memory);
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#endif
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cpu_register_physical_memory(base, TARGET_PAGE_SIZE, mmio_memory);
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ppc4xx_mmio_register(env, mmio, 0, TARGET_PAGE_SIZE,
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unassigned_mem_read, unassigned_mem_write, NULL);
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}
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return mmio;
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}
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/*****************************************************************************/
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/* Peripheral local bus arbitrer */
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enum {
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PLB0_BESR = 0x084,
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PLB0_BEAR = 0x086,
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PLB0_ACR = 0x087,
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};
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typedef struct ppc4xx_plb_t ppc4xx_plb_t;
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struct ppc4xx_plb_t {
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uint32_t acr;
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uint32_t bear;
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uint32_t besr;
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};
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static target_ulong dcr_read_plb (void *opaque, int dcrn)
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{
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ppc4xx_plb_t *plb;
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target_ulong ret;
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plb = opaque;
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switch (dcrn) {
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case PLB0_ACR:
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ret = plb->acr;
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break;
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case PLB0_BEAR:
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ret = plb->bear;
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break;
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case PLB0_BESR:
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ret = plb->besr;
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break;
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default:
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/* Avoid gcc warning */
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ret = 0;
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break;
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}
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return ret;
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}
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static void dcr_write_plb (void *opaque, int dcrn, target_ulong val)
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{
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ppc4xx_plb_t *plb;
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plb = opaque;
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switch (dcrn) {
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case PLB0_ACR:
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plb->acr = val & 0xFC000000;
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break;
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case PLB0_BEAR:
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/* Read only */
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break;
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case PLB0_BESR:
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/* Write-clear */
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plb->besr &= ~val;
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break;
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}
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}
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318 |
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static void ppc4xx_plb_reset (void *opaque)
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{
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ppc4xx_plb_t *plb;
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plb = opaque;
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plb->acr = 0x00000000;
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plb->bear = 0x00000000;
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plb->besr = 0x00000000;
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}
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328 |
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void ppc4xx_plb_init (CPUState *env)
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{
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ppc4xx_plb_t *plb;
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plb = qemu_mallocz(sizeof(ppc4xx_plb_t));
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if (plb != NULL) {
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ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
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ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
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ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
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ppc4xx_plb_reset(plb);
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qemu_register_reset(ppc4xx_plb_reset, plb);
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}
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}
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342 |
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343 |
/*****************************************************************************/
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344 |
/* PLB to OPB bridge */
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enum {
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POB0_BESR0 = 0x0A0,
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POB0_BESR1 = 0x0A2,
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POB0_BEAR = 0x0A4,
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};
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350 |
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typedef struct ppc4xx_pob_t ppc4xx_pob_t;
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struct ppc4xx_pob_t {
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uint32_t bear;
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354 |
uint32_t besr[2];
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};
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356 |
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357 |
static target_ulong dcr_read_pob (void *opaque, int dcrn)
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358 |
{
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359 |
ppc4xx_pob_t *pob;
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360 |
target_ulong ret;
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361 |
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362 |
pob = opaque;
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363 |
switch (dcrn) {
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364 |
case POB0_BEAR:
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365 |
ret = pob->bear;
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366 |
break;
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367 |
case POB0_BESR0:
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368 |
case POB0_BESR1:
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369 |
ret = pob->besr[dcrn - POB0_BESR0];
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370 |
break;
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371 |
default:
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372 |
/* Avoid gcc warning */
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373 |
ret = 0;
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374 |
break;
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375 |
}
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return ret;
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}
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379 |
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380 |
static void dcr_write_pob (void *opaque, int dcrn, target_ulong val)
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381 |
{
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382 |
ppc4xx_pob_t *pob;
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383 |
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384 |
pob = opaque;
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385 |
switch (dcrn) {
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386 |
case POB0_BEAR:
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387 |
/* Read only */
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388 |
break;
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389 |
case POB0_BESR0:
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390 |
case POB0_BESR1:
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391 |
/* Write-clear */
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392 |
pob->besr[dcrn - POB0_BESR0] &= ~val;
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393 |
break;
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394 |
}
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|
395 |
}
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|
396 |
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397 |
static void ppc4xx_pob_reset (void *opaque)
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|
398 |
{
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399 |
ppc4xx_pob_t *pob;
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|
400 |
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401 |
pob = opaque;
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402 |
/* No error */
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403 |
pob->bear = 0x00000000;
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404 |
pob->besr[0] = 0x0000000;
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405 |
pob->besr[1] = 0x0000000;
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406 |
}
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407 |
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408 |
void ppc4xx_pob_init (CPUState *env)
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|
409 |
{
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|
410 |
ppc4xx_pob_t *pob;
|
|
411 |
|
|
412 |
pob = qemu_mallocz(sizeof(ppc4xx_pob_t));
|
|
413 |
if (pob != NULL) {
|
|
414 |
ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
|
|
415 |
ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
|
|
416 |
ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
|
|
417 |
qemu_register_reset(ppc4xx_pob_reset, pob);
|
|
418 |
ppc4xx_pob_reset(env);
|
|
419 |
}
|
|
420 |
}
|
|
421 |
|
|
422 |
/*****************************************************************************/
|
|
423 |
/* OPB arbitrer */
|
|
424 |
typedef struct ppc4xx_opba_t ppc4xx_opba_t;
|
|
425 |
struct ppc4xx_opba_t {
|
|
426 |
target_ulong base;
|
|
427 |
uint8_t cr;
|
|
428 |
uint8_t pr;
|
|
429 |
};
|
|
430 |
|
|
431 |
static uint32_t opba_readb (void *opaque, target_phys_addr_t addr)
|
|
432 |
{
|
|
433 |
ppc4xx_opba_t *opba;
|
|
434 |
uint32_t ret;
|
|
435 |
|
|
436 |
#ifdef DEBUG_OPBA
|
|
437 |
printf("%s: addr " PADDRX "\n", __func__, addr);
|
|
438 |
#endif
|
|
439 |
opba = opaque;
|
|
440 |
switch (addr - opba->base) {
|
|
441 |
case 0x00:
|
|
442 |
ret = opba->cr;
|
|
443 |
break;
|
|
444 |
case 0x01:
|
|
445 |
ret = opba->pr;
|
|
446 |
break;
|
|
447 |
default:
|
|
448 |
ret = 0x00;
|
|
449 |
break;
|
|
450 |
}
|
|
451 |
|
|
452 |
return ret;
|
|
453 |
}
|
|
454 |
|
|
455 |
static void opba_writeb (void *opaque,
|
|
456 |
target_phys_addr_t addr, uint32_t value)
|
|
457 |
{
|
|
458 |
ppc4xx_opba_t *opba;
|
|
459 |
|
|
460 |
#ifdef DEBUG_OPBA
|
|
461 |
printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
|
|
462 |
#endif
|
|
463 |
opba = opaque;
|
|
464 |
switch (addr - opba->base) {
|
|
465 |
case 0x00:
|
|
466 |
opba->cr = value & 0xF8;
|
|
467 |
break;
|
|
468 |
case 0x01:
|
|
469 |
opba->pr = value & 0xFF;
|
|
470 |
break;
|
|
471 |
default:
|
|
472 |
break;
|
|
473 |
}
|
|
474 |
}
|
|
475 |
|
|
476 |
static uint32_t opba_readw (void *opaque, target_phys_addr_t addr)
|
|
477 |
{
|
|
478 |
uint32_t ret;
|
|
479 |
|
|
480 |
#ifdef DEBUG_OPBA
|
|
481 |
printf("%s: addr " PADDRX "\n", __func__, addr);
|
|
482 |
#endif
|
|
483 |
ret = opba_readb(opaque, addr) << 8;
|
|
484 |
ret |= opba_readb(opaque, addr + 1);
|
|
485 |
|
|
486 |
return ret;
|
|
487 |
}
|
|
488 |
|
|
489 |
static void opba_writew (void *opaque,
|
|
490 |
target_phys_addr_t addr, uint32_t value)
|
|
491 |
{
|
|
492 |
#ifdef DEBUG_OPBA
|
|
493 |
printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
|
|
494 |
#endif
|
|
495 |
opba_writeb(opaque, addr, value >> 8);
|
|
496 |
opba_writeb(opaque, addr + 1, value);
|
|
497 |
}
|
|
498 |
|
|
499 |
static uint32_t opba_readl (void *opaque, target_phys_addr_t addr)
|
|
500 |
{
|
|
501 |
uint32_t ret;
|
|
502 |
|
|
503 |
#ifdef DEBUG_OPBA
|
|
504 |
printf("%s: addr " PADDRX "\n", __func__, addr);
|
|
505 |
#endif
|
|
506 |
ret = opba_readb(opaque, addr) << 24;
|
|
507 |
ret |= opba_readb(opaque, addr + 1) << 16;
|
|
508 |
|
|
509 |
return ret;
|
|
510 |
}
|
|
511 |
|
|
512 |
static void opba_writel (void *opaque,
|
|
513 |
target_phys_addr_t addr, uint32_t value)
|
|
514 |
{
|
|
515 |
#ifdef DEBUG_OPBA
|
|
516 |
printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
|
|
517 |
#endif
|
|
518 |
opba_writeb(opaque, addr, value >> 24);
|
|
519 |
opba_writeb(opaque, addr + 1, value >> 16);
|
|
520 |
}
|
|
521 |
|
|
522 |
static CPUReadMemoryFunc *opba_read[] = {
|
|
523 |
&opba_readb,
|
|
524 |
&opba_readw,
|
|
525 |
&opba_readl,
|
|
526 |
};
|
|
527 |
|
|
528 |
static CPUWriteMemoryFunc *opba_write[] = {
|
|
529 |
&opba_writeb,
|
|
530 |
&opba_writew,
|
|
531 |
&opba_writel,
|
|
532 |
};
|
|
533 |
|
|
534 |
static void ppc4xx_opba_reset (void *opaque)
|
|
535 |
{
|
|
536 |
ppc4xx_opba_t *opba;
|
|
537 |
|
|
538 |
opba = opaque;
|
|
539 |
opba->cr = 0x00; /* No dynamic priorities - park disabled */
|
|
540 |
opba->pr = 0x11;
|
|
541 |
}
|
|
542 |
|
|
543 |
void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio, uint32_t offset)
|
|
544 |
{
|
|
545 |
ppc4xx_opba_t *opba;
|
|
546 |
|
|
547 |
opba = qemu_mallocz(sizeof(ppc4xx_opba_t));
|
|
548 |
if (opba != NULL) {
|
|
549 |
opba->base = mmio->base + offset;
|
|
550 |
#ifdef DEBUG_OPBA
|
|
551 |
printf("%s: offset=%08x\n", __func__, offset);
|
|
552 |
#endif
|
|
553 |
ppc4xx_mmio_register(env, mmio, offset, 0x002,
|
|
554 |
opba_read, opba_write, opba);
|
|
555 |
qemu_register_reset(ppc4xx_opba_reset, opba);
|
|
556 |
ppc4xx_opba_reset(opba);
|
|
557 |
}
|
|
558 |
}
|
|
559 |
|
|
560 |
/*****************************************************************************/
|
|
561 |
/* "Universal" Interrupt controller */
|
|
562 |
enum {
|
|
563 |
DCR_UICSR = 0x000,
|
|
564 |
DCR_UICSRS = 0x001,
|
|
565 |
DCR_UICER = 0x002,
|
|
566 |
DCR_UICCR = 0x003,
|
|
567 |
DCR_UICPR = 0x004,
|
|
568 |
DCR_UICTR = 0x005,
|
|
569 |
DCR_UICMSR = 0x006,
|
|
570 |
DCR_UICVR = 0x007,
|
|
571 |
DCR_UICVCR = 0x008,
|
|
572 |
DCR_UICMAX = 0x009,
|
|
573 |
};
|
|
574 |
|
|
575 |
#define UIC_MAX_IRQ 32
|
|
576 |
typedef struct ppcuic_t ppcuic_t;
|
|
577 |
struct ppcuic_t {
|
|
578 |
uint32_t dcr_base;
|
|
579 |
int use_vectors;
|
|
580 |
uint32_t uicsr; /* Status register */
|
|
581 |
uint32_t uicer; /* Enable register */
|
|
582 |
uint32_t uiccr; /* Critical register */
|
|
583 |
uint32_t uicpr; /* Polarity register */
|
|
584 |
uint32_t uictr; /* Triggering register */
|
|
585 |
uint32_t uicvcr; /* Vector configuration register */
|
|
586 |
uint32_t uicvr;
|
|
587 |
qemu_irq *irqs;
|
|
588 |
};
|
|
589 |
|
|
590 |
static void ppcuic_trigger_irq (ppcuic_t *uic)
|
|
591 |
{
|
|
592 |
uint32_t ir, cr;
|
|
593 |
int start, end, inc, i;
|
|
594 |
|
|
595 |
/* Trigger interrupt if any is pending */
|
|
596 |
ir = uic->uicsr & uic->uicer & (~uic->uiccr);
|
|
597 |
cr = uic->uicsr & uic->uicer & uic->uiccr;
|
|
598 |
#ifdef DEBUG_UIC
|
|
599 |
if (loglevel & CPU_LOG_INT) {
|
|
600 |
fprintf(logfile, "%s: uicsr %08x uicer %08x uiccr %08x\n"
|
|
601 |
" %08x ir %08x cr %08x\n", __func__,
|
|
602 |
uic->uicsr, uic->uicer, uic->uiccr,
|
|
603 |
uic->uicsr & uic->uicer, ir, cr);
|
|
604 |
}
|
|
605 |
#endif
|
|
606 |
if (ir != 0x0000000) {
|
|
607 |
#ifdef DEBUG_UIC
|
|
608 |
if (loglevel & CPU_LOG_INT) {
|
|
609 |
fprintf(logfile, "Raise UIC interrupt\n");
|
|
610 |
}
|
|
611 |
#endif
|
|
612 |
qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]);
|
|
613 |
} else {
|
|
614 |
#ifdef DEBUG_UIC
|
|
615 |
if (loglevel & CPU_LOG_INT) {
|
|
616 |
fprintf(logfile, "Lower UIC interrupt\n");
|
|
617 |
}
|
|
618 |
#endif
|
|
619 |
qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]);
|
|
620 |
}
|
|
621 |
/* Trigger critical interrupt if any is pending and update vector */
|
|
622 |
if (cr != 0x0000000) {
|
|
623 |
qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]);
|
|
624 |
if (uic->use_vectors) {
|
|
625 |
/* Compute critical IRQ vector */
|
|
626 |
if (uic->uicvcr & 1) {
|
|
627 |
start = 31;
|
|
628 |
end = 0;
|
|
629 |
inc = -1;
|
|
630 |
} else {
|
|
631 |
start = 0;
|
|
632 |
end = 31;
|
|
633 |
inc = 1;
|
|
634 |
}
|
|
635 |
uic->uicvr = uic->uicvcr & 0xFFFFFFFC;
|
|
636 |
for (i = start; i <= end; i += inc) {
|
|
637 |
if (cr & (1 << i)) {
|
|
638 |
uic->uicvr += (i - start) * 512 * inc;
|
|
639 |
break;
|
|
640 |
}
|
|
641 |
}
|
|
642 |
}
|
|
643 |
#ifdef DEBUG_UIC
|
|
644 |
if (loglevel & CPU_LOG_INT) {
|
|
645 |
fprintf(logfile, "Raise UIC critical interrupt - vector %08x\n",
|
|
646 |
uic->uicvr);
|
|
647 |
}
|
|
648 |
#endif
|
|
649 |
} else {
|
|
650 |
#ifdef DEBUG_UIC
|
|
651 |
if (loglevel & CPU_LOG_INT) {
|
|
652 |
fprintf(logfile, "Lower UIC critical interrupt\n");
|
|
653 |
}
|
|
654 |
#endif
|
|
655 |
qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]);
|
|
656 |
uic->uicvr = 0x00000000;
|
|
657 |
}
|
|
658 |
}
|
|
659 |
|
|
660 |
static void ppcuic_set_irq (void *opaque, int irq_num, int level)
|
|
661 |
{
|
|
662 |
ppcuic_t *uic;
|
|
663 |
uint32_t mask, sr;
|
|
664 |
|
|
665 |
uic = opaque;
|
|
666 |
mask = 1 << irq_num;
|
|
667 |
#ifdef DEBUG_UIC
|
|
668 |
if (loglevel & CPU_LOG_INT) {
|
|
669 |
fprintf(logfile, "%s: irq %d level %d uicsr %08x mask %08x => %08x "
|
|
670 |
"%08x\n", __func__, irq_num, level,
|
|
671 |
uic->uicsr, mask, uic->uicsr & mask, level << irq_num);
|
|
672 |
}
|
|
673 |
#endif
|
|
674 |
if (irq_num < 0 || irq_num > 31)
|
|
675 |
return;
|
|
676 |
sr = uic->uicsr;
|
|
677 |
if (!(uic->uicpr & mask)) {
|
|
678 |
/* Negatively asserted IRQ */
|
|
679 |
level = level == 0 ? 1 : 0;
|
|
680 |
}
|
|
681 |
/* Update status register */
|
|
682 |
if (uic->uictr & mask) {
|
|
683 |
/* Edge sensitive interrupt */
|
|
684 |
if (level == 1)
|
|
685 |
uic->uicsr |= mask;
|
|
686 |
} else {
|
|
687 |
/* Level sensitive interrupt */
|
|
688 |
if (level == 1)
|
|
689 |
uic->uicsr |= mask;
|
|
690 |
else
|
|
691 |
uic->uicsr &= ~mask;
|
|
692 |
}
|
|
693 |
#ifdef DEBUG_UIC
|
|
694 |
if (loglevel & CPU_LOG_INT) {
|
|
695 |
fprintf(logfile, "%s: irq %d level %d sr %08x => %08x\n", __func__,
|
|
696 |
irq_num, level, uic->uicsr, sr);
|
|
697 |
}
|
|
698 |
#endif
|
|
699 |
if (sr != uic->uicsr)
|
|
700 |
ppcuic_trigger_irq(uic);
|
|
701 |
}
|
|
702 |
|
|
703 |
static target_ulong dcr_read_uic (void *opaque, int dcrn)
|
|
704 |
{
|
|
705 |
ppcuic_t *uic;
|
|
706 |
target_ulong ret;
|
|
707 |
|
|
708 |
uic = opaque;
|
|
709 |
dcrn -= uic->dcr_base;
|
|
710 |
switch (dcrn) {
|
|
711 |
case DCR_UICSR:
|
|
712 |
case DCR_UICSRS:
|
|
713 |
ret = uic->uicsr;
|
|
714 |
break;
|
|
715 |
case DCR_UICER:
|
|
716 |
ret = uic->uicer;
|
|
717 |
break;
|
|
718 |
case DCR_UICCR:
|
|
719 |
ret = uic->uiccr;
|
|
720 |
break;
|
|
721 |
case DCR_UICPR:
|
|
722 |
ret = uic->uicpr;
|
|
723 |
break;
|
|
724 |
case DCR_UICTR:
|
|
725 |
ret = uic->uictr;
|
|
726 |
break;
|
|
727 |
case DCR_UICMSR:
|
|
728 |
ret = uic->uicsr & uic->uicer;
|
|
729 |
break;
|
|
730 |
case DCR_UICVR:
|
|
731 |
if (!uic->use_vectors)
|
|
732 |
goto no_read;
|
|
733 |
ret = uic->uicvr;
|
|
734 |
break;
|
|
735 |
case DCR_UICVCR:
|
|
736 |
if (!uic->use_vectors)
|
|
737 |
goto no_read;
|
|
738 |
ret = uic->uicvcr;
|
|
739 |
break;
|
|
740 |
default:
|
|
741 |
no_read:
|
|
742 |
ret = 0x00000000;
|
|
743 |
break;
|
|
744 |
}
|
|
745 |
|
|
746 |
return ret;
|
|
747 |
}
|
|
748 |
|
|
749 |
static void dcr_write_uic (void *opaque, int dcrn, target_ulong val)
|
|
750 |
{
|
|
751 |
ppcuic_t *uic;
|
|
752 |
|
|
753 |
uic = opaque;
|
|
754 |
dcrn -= uic->dcr_base;
|
|
755 |
#ifdef DEBUG_UIC
|
|
756 |
if (loglevel & CPU_LOG_INT) {
|
|
757 |
fprintf(logfile, "%s: dcr %d val " ADDRX "\n", __func__, dcrn, val);
|
|
758 |
}
|
|
759 |
#endif
|
|
760 |
switch (dcrn) {
|
|
761 |
case DCR_UICSR:
|
|
762 |
uic->uicsr &= ~val;
|
|
763 |
ppcuic_trigger_irq(uic);
|
|
764 |
break;
|
|
765 |
case DCR_UICSRS:
|
|
766 |
uic->uicsr |= val;
|
|
767 |
ppcuic_trigger_irq(uic);
|
|
768 |
break;
|
|
769 |
case DCR_UICER:
|
|
770 |
uic->uicer = val;
|
|
771 |
ppcuic_trigger_irq(uic);
|
|
772 |
break;
|
|
773 |
case DCR_UICCR:
|
|
774 |
uic->uiccr = val;
|
|
775 |
ppcuic_trigger_irq(uic);
|
|
776 |
break;
|
|
777 |
case DCR_UICPR:
|
|
778 |
uic->uicpr = val;
|
|
779 |
ppcuic_trigger_irq(uic);
|
|
780 |
break;
|
|
781 |
case DCR_UICTR:
|
|
782 |
uic->uictr = val;
|
|
783 |
ppcuic_trigger_irq(uic);
|
|
784 |
break;
|
|
785 |
case DCR_UICMSR:
|
|
786 |
break;
|
|
787 |
case DCR_UICVR:
|
|
788 |
break;
|
|
789 |
case DCR_UICVCR:
|
|
790 |
uic->uicvcr = val & 0xFFFFFFFD;
|
|
791 |
ppcuic_trigger_irq(uic);
|
|
792 |
break;
|
|
793 |
}
|
|
794 |
}
|
|
795 |
|
|
796 |
static void ppcuic_reset (void *opaque)
|
|
797 |
{
|
|
798 |
ppcuic_t *uic;
|
|
799 |
|
|
800 |
uic = opaque;
|
|
801 |
uic->uiccr = 0x00000000;
|
|
802 |
uic->uicer = 0x00000000;
|
|
803 |
uic->uicpr = 0x00000000;
|
|
804 |
uic->uicsr = 0x00000000;
|
|
805 |
uic->uictr = 0x00000000;
|
|
806 |
if (uic->use_vectors) {
|
|
807 |
uic->uicvcr = 0x00000000;
|
|
808 |
uic->uicvr = 0x0000000;
|
|
809 |
}
|
|
810 |
}
|
|
811 |
|
|
812 |
qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
|
|
813 |
uint32_t dcr_base, int has_ssr, int has_vr)
|
|
814 |
{
|
|
815 |
ppcuic_t *uic;
|
|
816 |
int i;
|
|
817 |
|
|
818 |
uic = qemu_mallocz(sizeof(ppcuic_t));
|
|
819 |
if (uic != NULL) {
|
|
820 |
uic->dcr_base = dcr_base;
|
|
821 |
uic->irqs = irqs;
|
|
822 |
if (has_vr)
|
|
823 |
uic->use_vectors = 1;
|
|
824 |
for (i = 0; i < DCR_UICMAX; i++) {
|
|
825 |
ppc_dcr_register(env, dcr_base + i, uic,
|
|
826 |
&dcr_read_uic, &dcr_write_uic);
|
|
827 |
}
|
|
828 |
qemu_register_reset(ppcuic_reset, uic);
|
|
829 |
ppcuic_reset(uic);
|
|
830 |
}
|
|
831 |
|
|
832 |
return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
|
|
833 |
}
|
|
834 |
|
|
835 |
/*****************************************************************************/
|
|
836 |
/* Code decompression controller */
|
|
837 |
/* XXX: TODO */
|
|
838 |
|
|
839 |
/*****************************************************************************/
|
|
840 |
/* SDRAM controller */
|
|
841 |
typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
|
|
842 |
struct ppc4xx_sdram_t {
|
|
843 |
uint32_t addr;
|
|
844 |
int nbanks;
|
|
845 |
target_ulong ram_bases[4];
|
|
846 |
target_ulong ram_sizes[4];
|
|
847 |
uint32_t besr0;
|
|
848 |
uint32_t besr1;
|
|
849 |
uint32_t bear;
|
|
850 |
uint32_t cfg;
|
|
851 |
uint32_t status;
|
|
852 |
uint32_t rtr;
|
|
853 |
uint32_t pmit;
|
|
854 |
uint32_t bcr[4];
|
|
855 |
uint32_t tr;
|
|
856 |
uint32_t ecccfg;
|
|
857 |
uint32_t eccesr;
|
|
858 |
qemu_irq irq;
|
|
859 |
};
|
|
860 |
|
|
861 |
enum {
|
|
862 |
SDRAM0_CFGADDR = 0x010,
|
|
863 |
SDRAM0_CFGDATA = 0x011,
|
|
864 |
};
|
|
865 |
|
|
866 |
static uint32_t sdram_bcr (target_ulong ram_base, target_ulong ram_size)
|
|
867 |
{
|
|
868 |
uint32_t bcr;
|
|
869 |
|
|
870 |
switch (ram_size) {
|
|
871 |
case (4 * 1024 * 1024):
|
|
872 |
bcr = 0x00000000;
|
|
873 |
break;
|
|
874 |
case (8 * 1024 * 1024):
|
|
875 |
bcr = 0x00020000;
|
|
876 |
break;
|
|
877 |
case (16 * 1024 * 1024):
|
|
878 |
bcr = 0x00040000;
|
|
879 |
break;
|
|
880 |
case (32 * 1024 * 1024):
|
|
881 |
bcr = 0x00060000;
|
|
882 |
break;
|
|
883 |
case (64 * 1024 * 1024):
|
|
884 |
bcr = 0x00080000;
|
|
885 |
break;
|
|
886 |
case (128 * 1024 * 1024):
|
|
887 |
bcr = 0x000A0000;
|
|
888 |
break;
|
|
889 |
case (256 * 1024 * 1024):
|
|
890 |
bcr = 0x000C0000;
|
|
891 |
break;
|
|
892 |
default:
|
|
893 |
printf("%s: invalid RAM size " TARGET_FMT_ld "\n", __func__, ram_size);
|
|
894 |
return 0x00000000;
|
|
895 |
}
|
|
896 |
bcr |= ram_base & 0xFF800000;
|
|
897 |
bcr |= 1;
|
|
898 |
|
|
899 |
return bcr;
|
|
900 |
}
|
|
901 |
|
|
902 |
static inline target_ulong sdram_base (uint32_t bcr)
|
|
903 |
{
|
|
904 |
return bcr & 0xFF800000;
|
|
905 |
}
|
|
906 |
|
|
907 |
static target_ulong sdram_size (uint32_t bcr)
|
|
908 |
{
|
|
909 |
target_ulong size;
|
|
910 |
int sh;
|
|
911 |
|
|
912 |
sh = (bcr >> 17) & 0x7;
|
|
913 |
if (sh == 7)
|
|
914 |
size = -1;
|
|
915 |
else
|
|
916 |
size = (4 * 1024 * 1024) << sh;
|
|
917 |
|
|
918 |
return size;
|
|
919 |
}
|
|
920 |
|
|
921 |
static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled)
|
|
922 |
{
|
|
923 |
if (*bcrp & 0x00000001) {
|
|
924 |
/* Unmap RAM */
|
|
925 |
#ifdef DEBUG_SDRAM
|
|
926 |
printf("%s: unmap RAM area " ADDRX " " ADDRX "\n", __func__,
|
|
927 |
sdram_base(*bcrp), sdram_size(*bcrp));
|
|
928 |
#endif
|
|
929 |
cpu_register_physical_memory(sdram_base(*bcrp), sdram_size(*bcrp),
|
|
930 |
IO_MEM_UNASSIGNED);
|
|
931 |
}
|
|
932 |
*bcrp = bcr & 0xFFDEE001;
|
|
933 |
if (enabled && (bcr & 0x00000001)) {
|
|
934 |
#ifdef DEBUG_SDRAM
|
|
935 |
printf("%s: Map RAM area " ADDRX " " ADDRX "\n", __func__,
|
|
936 |
sdram_base(bcr), sdram_size(bcr));
|
|
937 |
#endif
|
|
938 |
cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr),
|
|
939 |
sdram_base(bcr) | IO_MEM_RAM);
|
|
940 |
}
|
|
941 |
}
|
|
942 |
|
|
943 |
static void sdram_map_bcr (ppc4xx_sdram_t *sdram)
|
|
944 |
{
|
|
945 |
int i;
|
|
946 |
|
|
947 |
for (i = 0; i < sdram->nbanks; i++) {
|
|
948 |
if (sdram->ram_sizes[i] != 0) {
|
|
949 |
sdram_set_bcr(&sdram->bcr[i],
|
|
950 |
sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]),
|
|
951 |
1);
|
|
952 |
} else {
|
|
953 |
sdram_set_bcr(&sdram->bcr[i], 0x00000000, 0);
|
|
954 |
}
|
|
955 |
}
|
|
956 |
}
|
|
957 |
|
|
958 |
static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram)
|
|
959 |
{
|
|
960 |
int i;
|
|
961 |
|
|
962 |
for (i = 0; i < sdram->nbanks; i++) {
|
|
963 |
cpu_register_physical_memory(sdram_base(sdram->bcr[i]),
|
|
964 |
sdram_size(sdram->bcr[i]),
|
|
965 |
IO_MEM_UNASSIGNED);
|
|
966 |
}
|
|
967 |
}
|
|
968 |
|
|
969 |
static target_ulong dcr_read_sdram (void *opaque, int dcrn)
|
|
970 |
{
|
|
971 |
ppc4xx_sdram_t *sdram;
|
|
972 |
target_ulong ret;
|
|
973 |
|
|
974 |
sdram = opaque;
|
|
975 |
switch (dcrn) {
|
|
976 |
case SDRAM0_CFGADDR:
|
|
977 |
ret = sdram->addr;
|
|
978 |
break;
|
|
979 |
case SDRAM0_CFGDATA:
|
|
980 |
switch (sdram->addr) {
|
|
981 |
case 0x00: /* SDRAM_BESR0 */
|
|
982 |
ret = sdram->besr0;
|
|
983 |
break;
|
|
984 |
case 0x08: /* SDRAM_BESR1 */
|
|
985 |
ret = sdram->besr1;
|
|
986 |
break;
|
|
987 |
case 0x10: /* SDRAM_BEAR */
|
|
988 |
ret = sdram->bear;
|
|
989 |
break;
|
|
990 |
case 0x20: /* SDRAM_CFG */
|
|
991 |
ret = sdram->cfg;
|
|
992 |
break;
|
|
993 |
case 0x24: /* SDRAM_STATUS */
|
|
994 |
ret = sdram->status;
|
|
995 |
break;
|
|
996 |
case 0x30: /* SDRAM_RTR */
|
|
997 |
ret = sdram->rtr;
|
|
998 |
break;
|
|
999 |
case 0x34: /* SDRAM_PMIT */
|
|
1000 |
ret = sdram->pmit;
|
|
1001 |
break;
|
|
1002 |
case 0x40: /* SDRAM_B0CR */
|
|
1003 |
ret = sdram->bcr[0];
|
|
1004 |
break;
|
|
1005 |
case 0x44: /* SDRAM_B1CR */
|
|
1006 |
ret = sdram->bcr[1];
|
|
1007 |
break;
|
|
1008 |
case 0x48: /* SDRAM_B2CR */
|
|
1009 |
ret = sdram->bcr[2];
|
|
1010 |
break;
|
|
1011 |
case 0x4C: /* SDRAM_B3CR */
|
|
1012 |
ret = sdram->bcr[3];
|
|
1013 |
break;
|
|
1014 |
case 0x80: /* SDRAM_TR */
|
|
1015 |
ret = -1; /* ? */
|
|
1016 |
break;
|
|
1017 |
case 0x94: /* SDRAM_ECCCFG */
|
|
1018 |
ret = sdram->ecccfg;
|
|
1019 |
break;
|
|
1020 |
case 0x98: /* SDRAM_ECCESR */
|
|
1021 |
ret = sdram->eccesr;
|
|
1022 |
break;
|
|
1023 |
default: /* Error */
|
|
1024 |
ret = -1;
|
|
1025 |
break;
|
|
1026 |
}
|
|
1027 |
break;
|
|
1028 |
default:
|
|
1029 |
/* Avoid gcc warning */
|
|
1030 |
ret = 0x00000000;
|
|
1031 |
break;
|
|
1032 |
}
|
|
1033 |
|
|
1034 |
return ret;
|
|
1035 |
}
|
|
1036 |
|
|
1037 |
static void dcr_write_sdram (void *opaque, int dcrn, target_ulong val)
|
|
1038 |
{
|
|
1039 |
ppc4xx_sdram_t *sdram;
|
|
1040 |
|
|
1041 |
sdram = opaque;
|
|
1042 |
switch (dcrn) {
|
|
1043 |
case SDRAM0_CFGADDR:
|
|
1044 |
sdram->addr = val;
|
|
1045 |
break;
|
|
1046 |
case SDRAM0_CFGDATA:
|
|
1047 |
switch (sdram->addr) {
|
|
1048 |
case 0x00: /* SDRAM_BESR0 */
|
|
1049 |
sdram->besr0 &= ~val;
|
|
1050 |
break;
|
|
1051 |
case 0x08: /* SDRAM_BESR1 */
|
|
1052 |
sdram->besr1 &= ~val;
|
|
1053 |
break;
|
|
1054 |
case 0x10: /* SDRAM_BEAR */
|
|
1055 |
sdram->bear = val;
|
|
1056 |
break;
|
|
1057 |
case 0x20: /* SDRAM_CFG */
|
|
1058 |
val &= 0xFFE00000;
|
|
1059 |
if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) {
|
|
1060 |
#ifdef DEBUG_SDRAM
|
|
1061 |
printf("%s: enable SDRAM controller\n", __func__);
|
|
1062 |
#endif
|
|
1063 |
/* validate all RAM mappings */
|
|
1064 |
sdram_map_bcr(sdram);
|
|
1065 |
sdram->status &= ~0x80000000;
|
|
1066 |
} else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) {
|
|
1067 |
#ifdef DEBUG_SDRAM
|
|
1068 |
printf("%s: disable SDRAM controller\n", __func__);
|
|
1069 |
#endif
|
|
1070 |
/* invalidate all RAM mappings */
|
|
1071 |
sdram_unmap_bcr(sdram);
|
|
1072 |
sdram->status |= 0x80000000;
|
|
1073 |
}
|
|
1074 |
if (!(sdram->cfg & 0x40000000) && (val & 0x40000000))
|
|
1075 |
sdram->status |= 0x40000000;
|
|
1076 |
else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000))
|
|
1077 |
sdram->status &= ~0x40000000;
|
|
1078 |
sdram->cfg = val;
|
|
1079 |
break;
|
|
1080 |
case 0x24: /* SDRAM_STATUS */
|
|
1081 |
/* Read-only register */
|
|
1082 |
break;
|
|
1083 |
case 0x30: /* SDRAM_RTR */
|
|
1084 |
sdram->rtr = val & 0x3FF80000;
|
|
1085 |
break;
|
|
1086 |
case 0x34: /* SDRAM_PMIT */
|
|
1087 |
sdram->pmit = (val & 0xF8000000) | 0x07C00000;
|
|
1088 |
break;
|
|
1089 |
case 0x40: /* SDRAM_B0CR */
|
|
1090 |
sdram_set_bcr(&sdram->bcr[0], val, sdram->cfg & 0x80000000);
|
|
1091 |
break;
|
|
1092 |
case 0x44: /* SDRAM_B1CR */
|
|
1093 |
sdram_set_bcr(&sdram->bcr[1], val, sdram->cfg & 0x80000000);
|
|
1094 |
break;
|
|
1095 |
case 0x48: /* SDRAM_B2CR */
|
|
1096 |
sdram_set_bcr(&sdram->bcr[2], val, sdram->cfg & 0x80000000);
|
|
1097 |
break;
|
|
1098 |
case 0x4C: /* SDRAM_B3CR */
|
|
1099 |
sdram_set_bcr(&sdram->bcr[3], val, sdram->cfg & 0x80000000);
|
|
1100 |
break;
|
|
1101 |
case 0x80: /* SDRAM_TR */
|
|
1102 |
sdram->tr = val & 0x018FC01F;
|
|
1103 |
break;
|
|
1104 |
case 0x94: /* SDRAM_ECCCFG */
|
|
1105 |
sdram->ecccfg = val & 0x00F00000;
|
|
1106 |
break;
|
|
1107 |
case 0x98: /* SDRAM_ECCESR */
|
|
1108 |
val &= 0xFFF0F000;
|
|
1109 |
if (sdram->eccesr == 0 && val != 0)
|
|
1110 |
qemu_irq_raise(sdram->irq);
|
|
1111 |
else if (sdram->eccesr != 0 && val == 0)
|
|
1112 |
qemu_irq_lower(sdram->irq);
|
|
1113 |
sdram->eccesr = val;
|
|
1114 |
break;
|
|
1115 |
default: /* Error */
|
|
1116 |
break;
|
|
1117 |
}
|
|
1118 |
break;
|
|
1119 |
}
|
|
1120 |
}
|
|
1121 |
|
|
1122 |
static void sdram_reset (void *opaque)
|
|
1123 |
{
|
|
1124 |
ppc4xx_sdram_t *sdram;
|
|
1125 |
|
|
1126 |
sdram = opaque;
|
|
1127 |
sdram->addr = 0x00000000;
|
|
1128 |
sdram->bear = 0x00000000;
|
|
1129 |
sdram->besr0 = 0x00000000; /* No error */
|
|
1130 |
sdram->besr1 = 0x00000000; /* No error */
|
|
1131 |
sdram->cfg = 0x00000000;
|
|
1132 |
sdram->ecccfg = 0x00000000; /* No ECC */
|
|
1133 |
sdram->eccesr = 0x00000000; /* No error */
|
|
1134 |
sdram->pmit = 0x07C00000;
|
|
1135 |
sdram->rtr = 0x05F00000;
|
|
1136 |
sdram->tr = 0x00854009;
|
|
1137 |
/* We pre-initialize RAM banks */
|
|
1138 |
sdram->status = 0x00000000;
|
|
1139 |
sdram->cfg = 0x00800000;
|
|
1140 |
sdram_unmap_bcr(sdram);
|
|
1141 |
}
|
|
1142 |
|
|
1143 |
void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
|
|
1144 |
target_ulong *ram_bases, target_ulong *ram_sizes)
|
|
1145 |
{
|
|
1146 |
ppc4xx_sdram_t *sdram;
|
|
1147 |
|
|
1148 |
sdram = qemu_mallocz(sizeof(ppc4xx_sdram_t));
|
|
1149 |
if (sdram != NULL) {
|
|
1150 |
sdram->irq = irq;
|
|
1151 |
sdram->nbanks = nbanks;
|
|
1152 |
memset(sdram->ram_bases, 0, 4 * sizeof(target_ulong));
|
|
1153 |
memcpy(sdram->ram_bases, ram_bases, nbanks * sizeof(target_ulong));
|
|
1154 |
memset(sdram->ram_sizes, 0, 4 * sizeof(target_ulong));
|
|
1155 |
memcpy(sdram->ram_sizes, ram_sizes, nbanks * sizeof(target_ulong));
|
|
1156 |
sdram_reset(sdram);
|
|
1157 |
qemu_register_reset(&sdram_reset, sdram);
|
|
1158 |
ppc_dcr_register(env, SDRAM0_CFGADDR,
|
|
1159 |
sdram, &dcr_read_sdram, &dcr_write_sdram);
|
|
1160 |
ppc_dcr_register(env, SDRAM0_CFGDATA,
|
|
1161 |
sdram, &dcr_read_sdram, &dcr_write_sdram);
|
|
1162 |
}
|
|
1163 |
}
|
|
1164 |
|
|
1165 |
/*****************************************************************************/
|
|
1166 |
/* Peripheral controller */
|
|
1167 |
typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
|
|
1168 |
struct ppc4xx_ebc_t {
|
|
1169 |
uint32_t addr;
|
|
1170 |
uint32_t bcr[8];
|
|
1171 |
uint32_t bap[8];
|
|
1172 |
uint32_t bear;
|
|
1173 |
uint32_t besr0;
|
|
1174 |
uint32_t besr1;
|
|
1175 |
uint32_t cfg;
|
|
1176 |
};
|
|
1177 |
|
|
1178 |
enum {
|
|
1179 |
EBC0_CFGADDR = 0x012,
|
|
1180 |
EBC0_CFGDATA = 0x013,
|
|
1181 |
};
|
|
1182 |
|
|
1183 |
static target_ulong dcr_read_ebc (void *opaque, int dcrn)
|
|
1184 |
{
|
|
1185 |
ppc4xx_ebc_t *ebc;
|
|
1186 |
target_ulong ret;
|
|
1187 |
|
|
1188 |
ebc = opaque;
|
|
1189 |
switch (dcrn) {
|
|
1190 |
case EBC0_CFGADDR:
|
|
1191 |
ret = ebc->addr;
|
|
1192 |
break;
|
|
1193 |
case EBC0_CFGDATA:
|
|
1194 |
switch (ebc->addr) {
|
|
1195 |
case 0x00: /* B0CR */
|
|
1196 |
ret = ebc->bcr[0];
|
|
1197 |
break;
|
|
1198 |
case 0x01: /* B1CR */
|
|
1199 |
ret = ebc->bcr[1];
|
|
1200 |
break;
|
|
1201 |
case 0x02: /* B2CR */
|
|
1202 |
ret = ebc->bcr[2];
|
|
1203 |
break;
|
|
1204 |
case 0x03: /* B3CR */
|
|
1205 |
ret = ebc->bcr[3];
|
|
1206 |
break;
|
|
1207 |
case 0x04: /* B4CR */
|
|
1208 |
ret = ebc->bcr[4];
|
|
1209 |
break;
|
|
1210 |
case 0x05: /* B5CR */
|
|
1211 |
ret = ebc->bcr[5];
|
|
1212 |
break;
|
|
1213 |
case 0x06: /* B6CR */
|
|
1214 |
ret = ebc->bcr[6];
|
|
1215 |
break;
|
|
1216 |
case 0x07: /* B7CR */
|
|
1217 |
ret = ebc->bcr[7];
|
|
1218 |
break;
|
|
1219 |
case 0x10: /* B0AP */
|
|
1220 |
ret = ebc->bap[0];
|
|
1221 |
break;
|
|
1222 |
case 0x11: /* B1AP */
|
|
1223 |
ret = ebc->bap[1];
|
|
1224 |
break;
|
|
1225 |
case 0x12: /* B2AP */
|
|
1226 |
ret = ebc->bap[2];
|
|
1227 |
break;
|
|
1228 |
case 0x13: /* B3AP */
|
|
1229 |
ret = ebc->bap[3];
|
|
1230 |
break;
|
|
1231 |
case 0x14: /* B4AP */
|
|
1232 |
ret = ebc->bap[4];
|
|
1233 |
break;
|
|
1234 |
case 0x15: /* B5AP */
|
|
1235 |
ret = ebc->bap[5];
|
|
1236 |
break;
|
|
1237 |
case 0x16: /* B6AP */
|
|
1238 |
ret = ebc->bap[6];
|
|
1239 |
break;
|
|
1240 |
case 0x17: /* B7AP */
|
|
1241 |
ret = ebc->bap[7];
|
|
1242 |
break;
|
|
1243 |
case 0x20: /* BEAR */
|
|
1244 |
ret = ebc->bear;
|
|
1245 |
break;
|
|
1246 |
case 0x21: /* BESR0 */
|
|
1247 |
ret = ebc->besr0;
|
|
1248 |
break;
|
|
1249 |
case 0x22: /* BESR1 */
|
|
1250 |
ret = ebc->besr1;
|
|
1251 |
break;
|
|
1252 |
case 0x23: /* CFG */
|
|
1253 |
ret = ebc->cfg;
|
|
1254 |
break;
|
|
1255 |
default:
|
|
1256 |
ret = 0x00000000;
|
|
1257 |
break;
|
|
1258 |
}
|
|
1259 |
default:
|
|
1260 |
ret = 0x00000000;
|
|
1261 |
break;
|
|
1262 |
}
|
|
1263 |
|
|
1264 |
return ret;
|
|
1265 |
}
|
|
1266 |
|
|
1267 |
static void dcr_write_ebc (void *opaque, int dcrn, target_ulong val)
|
|
1268 |
{
|
|
1269 |
ppc4xx_ebc_t *ebc;
|
|
1270 |
|
|
1271 |
ebc = opaque;
|
|
1272 |
switch (dcrn) {
|
|
1273 |
case EBC0_CFGADDR:
|
|
1274 |
ebc->addr = val;
|
|
1275 |
break;
|
|
1276 |
case EBC0_CFGDATA:
|
|
1277 |
switch (ebc->addr) {
|
|
1278 |
case 0x00: /* B0CR */
|
|
1279 |
break;
|
|
1280 |
case 0x01: /* B1CR */
|
|
1281 |
break;
|
|
1282 |
case 0x02: /* B2CR */
|
|
1283 |
break;
|
|
1284 |
case 0x03: /* B3CR */
|
|
1285 |
break;
|
|
1286 |
case 0x04: /* B4CR */
|
|
1287 |
break;
|