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root / target-ppc @ 8eee0af9

Name Size
STATUS 10.6 kB
cpu.h 59.4 kB
exec.h 1.5 kB
helper.c 93.7 kB
helper.h 13.8 kB
helper_regs.h 3.4 kB
kvm.c 4.8 kB
kvm_ppc.c 2.6 kB
kvm_ppc.h 434 Bytes
machine.c 5.8 kB
mfrom_table.c 3.3 kB
mfrom_table_gen.c 652 Bytes
op_helper.c 124.4 kB
translate.c 309.7 kB
translate_init.c 412.8 kB

Latest revisions

# Date Author Comment
8eee0af9 03/07/2009 10:57 pm blueswir1

Keep SLB in-CPU

Real 970 CPUs have the SLB not memory backed, but inside the CPU.
This breaks bridge mode for 970 for now, but at least keeps us from
overwriting physical addresses 0x0 - 0x300, rendering our interrupt
handlers useless.

I put in a stub for bridge mode operation that could be enabled...
29c8ca6f 03/07/2009 10:57 pm blueswir1

Fix NX bit

ctx->nx only got ORed, but never reset. So when one page in the
lifetime of the VM was ever NX, all later pages were too.

Signed-off-by: Alexander Graf <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6755 c046a42c-6fe2-441c-8c8c-71466251a162
2ada0ed7 03/07/2009 10:56 pm blueswir1

Fix RFI

The current implementation masks some MSR bits from SRR1 as it is
given on rfi(d). This looks pretty wrong and breaks Altivec.

Signed-off-by: Alexander Graf <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6754 c046a42c-6fe2-441c-8c8c-71466251a162
4911012d 03/07/2009 10:55 pm blueswir1

Implement mtfsf.L encoding

Mtfsf can have the L bit set, so all the register contents get stored
in FPSCR. Linux uses it, so let's implement it.

Signed-off-by: Alexander Graf <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6753 c046a42c-6fe2-441c-8c8c-71466251a162
6ce0ca12 03/07/2009 10:54 pm blueswir1

Enable 64bit mode on interrupts

Real 970s enable MSR_SF on all interrupts. The current code didn't do
this until now, so let's activate it!

Signed-off-by: Alexander Graf <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6752 c046a42c-6fe2-441c-8c8c-71466251a162
4e98d8cf 03/07/2009 10:54 pm blueswir1

Nop some SPRs on 970fx

Linux tries to access some SPRs on PPC64 boot. Let's just ignore those
for the 970fx for now to make it happy.

Signed-off-by: Alexander Graf <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6751 c046a42c-6fe2-441c-8c8c-71466251a162
bf14b1ce 03/07/2009 10:52 pm blueswir1

Implment tlbiel

Linux uses tlbiel to flush TLB entries in PPC64 mode. This special TLB
flush opcode only flushes an entry for the CPU it runs on, not across
all CPUs in the system.

Signed-off-by: Alexander Graf <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6749 c046a42c-6fe2-441c-8c8c-71466251a162
5b5aba4f 03/07/2009 10:51 pm blueswir1

Implement large pages

The current SLB/PTE code does not support large pages, which are
required by Linux, as it boots up with the kernel regions up as large.

This patch implements large page support, so we can run Linux.

Signed-off-by: Alexander Graf <>...
f6b868fc 03/07/2009 10:50 pm blueswir1

Implement slbmte

In order to modify SLB entries on recent PPC64 machines, the slbmte
instruction is used.

This patch implements the slbmte instruction and makes the "bridge"
mode code use the slb set functions, so we can move the SLB into
the CPU struct later....
50773fd2 03/07/2009 05:59 pm blueswir1

Sparse fixes: add extern to ELF opcode tables to avoid warnings

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6740 c046a42c-6fe2-441c-8c8c-71466251a162

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