Revision 8f091a59 target-i386/cpu.h
b/target-i386/cpu.h | ||
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#define MSR_IA32_SYSENTER_ESP 0x175 |
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#define MSR_IA32_SYSENTER_EIP 0x176 |
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#define MSR_MCG_CAP 0x179 |
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#define MSR_MCG_STATUS 0x17a |
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#define MSR_MCG_CTL 0x17b |
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#define MSR_PAT 0x277 |
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#define MSR_EFER 0xc0000080 |
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#define MSR_EFER_SCE (1 << 0) |
... | ... | |
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#define CPUID_PGE (1 << 13) |
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#define CPUID_MCA (1 << 14) |
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#define CPUID_CMOV (1 << 15) |
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#define CPUID_PAT (1 << 16) |
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#define CPUID_CLFLUSH (1 << 19) |
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/* ... */ |
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#define CPUID_MMX (1 << 23) |
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#define CPUID_FXSR (1 << 24) |
... | ... | |
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target_ulong kernelgsbase; |
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#endif |
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uint64_t pat; |
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/* temporary data for USE_CODE_COPY mode */ |
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#ifdef USE_CODE_COPY |
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uint32_t tmp0; |
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