Revision 8f4efc55 target-sparc/cpu.h
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uint64_t tte; |
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} SparcTLBEntry; |
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struct CPUTimer |
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{
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const char *name; |
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uint32_t frequency; |
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uint32_t disabled; |
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uint64_t disabled_mask; |
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int64_t clock_offset; |
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struct QEMUTimer *qtimer; |
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}; |
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typedef struct CPUTimer CPUTimer; |
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struct QEMUFile; |
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void cpu_put_timer(struct QEMUFile *f, CPUTimer *s); |
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void cpu_get_timer(struct QEMUFile *f, CPUTimer *s); |
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typedef struct CPUSPARCState {
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target_ulong gregs[8]; /* general registers */ |
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target_ulong *regwptr; /* pointer to current register window */ |
| ... | ... | |
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uint64_t mgregs[8]; /* mmu general registers */ |
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uint64_t fprs; |
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uint64_t tick_cmpr, stick_cmpr; |
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void *tick, *stick;
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CPUTimer *tick, *stick;
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#define TICK_NPT_MASK 0x8000000000000000ULL |
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#define TICK_INT_DIS 0x8000000000000000ULL |
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uint64_t gsr; |
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uint32_t gl; // UA2005 |
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/* UA 2005 hyperprivileged registers */ |
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uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr; |
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void *hstick; // UA 2005
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CPUTimer *hstick; // UA 2005
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uint32_t softint; |
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#define SOFTINT_TIMER 1 |
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#define SOFTINT_STIMER (1 << 16) |
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#define cpu_signal_handler cpu_sparc_signal_handler |
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#define cpu_list sparc_cpu_list |
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#define CPU_SAVE_VERSION 5
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#define CPU_SAVE_VERSION 6
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/* MMU modes definitions */ |
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#define MMU_MODE0_SUFFIX _user |
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#ifdef TARGET_SPARC64 |
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/* sun4u.c */ |
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void cpu_tick_set_count(void *opaque, uint64_t count);
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uint64_t cpu_tick_get_count(void *opaque);
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void cpu_tick_set_limit(void *opaque, uint64_t limit);
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void cpu_tick_set_count(CPUTimer *timer, uint64_t count);
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uint64_t cpu_tick_get_count(CPUTimer *timer);
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void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit);
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trap_state* cpu_tsptr(CPUState* env); |
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#endif |
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