/ - Diff - qemu - Greek Research and Technology Network's projects

Revision 8f6f6026

     #define WTH2 (env->fpu->ft2.w[!FP_ENDIAN_IDX])
     #endif
     #if defined (DEBUG_OP)
     # define RETURN() __asm__ __volatile__("nop" : : : "memory");
     #else
     # define RETURN() __asm__ __volatile__("" : : : "memory");
     #endif
     #include "cpu.h"
     #include "exec-all.h"

         void glue(glue(op_load_fpr_,tregname), FREG) (void)  \
         {                                                    \
             treg = env->fpu->fpr[FREG].fs[FP_ENDIAN_IDX];    \
             RETURN();                                        \
             FORCE_RET();                                     \
+        }
     #define OP_WSTORE_FREG(treg, tregname, FREG)             \
         void glue(glue(op_store_fpr_,tregname), FREG) (void) \
         {                                                    \
             env->fpu->fpr[FREG].fs[FP_ENDIAN_IDX] = treg;    \
             RETURN();                                        \
             FORCE_RET();                                     \
+        }
     /* WT0 = FREG.w: op_load_fpr_WT0_fprFREG */
-...
             else                                             \
                 treg = (uint64_t)(env->fpu->fpr[FREG | 1].fs[FP_ENDIAN_IDX]) << 32 | \
                        env->fpu->fpr[FREG & ~1].fs[FP_ENDIAN_IDX]; \
             RETURN();                                        \
             FORCE_RET();                                     \
+        }
     #define OP_DSTORE_FREG(treg, tregname, FREG)             \
-...
                 env->fpu->fpr[FREG | 1].fs[FP_ENDIAN_IDX] = treg >> 32; \
                 env->fpu->fpr[FREG & ~1].fs[FP_ENDIAN_IDX] = treg;      \
             }                                                \
             RETURN();                                        \
             FORCE_RET();                                     \
+        }
     OP_DLOAD_FREG(DT0, DT0_fpr, FREG)
-...
         void glue(glue(op_load_fpr_,tregname), FREG) (void)  \
         {                                                    \
             treg = env->fpu->fpr[FREG].fs[!FP_ENDIAN_IDX];   \
             RETURN();                                        \
             FORCE_RET();                                     \
+        }
     #define OP_PSSTORE_FREG(treg, tregname, FREG)            \
         void glue(glue(op_store_fpr_,tregname), FREG) (void) \
         {                                                    \
             env->fpu->fpr[FREG].fs[!FP_ENDIAN_IDX] = treg;   \
             RETURN();                                        \
             FORCE_RET();                                     \
+        }
     OP_PSLOAD_FREG(WTH0, WTH0_fpr, FREG)
-...
         void glue(op_set, tregname)(void)    \
         {                                    \
             treg = PARAM1;                   \
             RETURN();                        \
             FORCE_RET();                     \
         }                                    \
         void glue(op_reset, tregname)(void)  \
         {                                    \
             treg = 0;                        \
             RETURN();                        \
             FORCE_RET();                     \
+        }
     SET_RESET(WT0, _WT0)

b/target-mips/op.c
250	250	void op_dup_T0 (void)
251	251	{
252	252	T2 = T0;
253		RETURN();
	253	FORCE_RET();
254	254	}
255	255
256	256	void op_load_HI (void)
257	257	{
258	258	T0 = env->HI[PARAM1][env->current_tc];
259		RETURN();
	259	FORCE_RET();
260	260	}
261	261
262	262	void op_store_HI (void)
263	263	{
264	264	env->HI[PARAM1][env->current_tc] = T0;
265		RETURN();
	265	FORCE_RET();
266	266	}
267	267
268	268	void op_load_LO (void)
269	269	{
270	270	T0 = env->LO[PARAM1][env->current_tc];
271		RETURN();
	271	FORCE_RET();
272	272	}
273	273
274	274	void op_store_LO (void)
275	275	{
276	276	env->LO[PARAM1][env->current_tc] = T0;
277		RETURN();
	277	FORCE_RET();
278	278	}
279	279
280	280	/* Load and store */
...	...
308	308	else
309	309	#endif
310	310	T0 += T1;
311		RETURN();
	311	FORCE_RET();
312	312	}
313	313
314	314	/* Arithmetic */
315	315	void op_add (void)
316	316	{
317	317	T0 = (int32_t)((int32_t)T0 + (int32_t)T1);
318		RETURN();
	318	FORCE_RET();
319	319	}
320	320
321	321	void op_addo (void)
...	...
329	329	CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
330	330	}
331	331	T0 = (int32_t)T0;
332		RETURN();
	332	FORCE_RET();
333	333	}
334	334
335	335	void op_sub (void)
336	336	{
337	337	T0 = (int32_t)((int32_t)T0 - (int32_t)T1);
338		RETURN();
	338	FORCE_RET();
339	339	}
340	340
341	341	void op_subo (void)
...	...
349	349	CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
350	350	}
351	351	T0 = (int32_t)T0;
352		RETURN();
	352	FORCE_RET();
353	353	}
354	354
355	355	void op_mul (void)
356	356	{
357	357	T0 = (int32_t)((int32_t)T0 * (int32_t)T1);
358		RETURN();
	358	FORCE_RET();
359	359	}
360	360
361	361	#if HOST_LONG_BITS < 64
362	362	void op_div (void)
363	363	{
364	364	CALL_FROM_TB0(do_div);
365		RETURN();
	365	FORCE_RET();
366	366	}
367	367	#else
368	368	void op_div (void)
...	...
371	371	env->LO[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 / (int32_t)T1);
372	372	env->HI[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 % (int32_t)T1);
373	373	}
374		RETURN();
	374	FORCE_RET();
375	375	}
376	376	#endif
377	377
...	...
381	381	env->LO[0][env->current_tc] = (int32_t)((uint32_t)T0 / (uint32_t)T1);
382	382	env->HI[0][env->current_tc] = (int32_t)((uint32_t)T0 % (uint32_t)T1);
383	383	}
384		RETURN();
	384	FORCE_RET();
385	385	}
386	386
387	387	#if defined(TARGET_MIPS64)
...	...
389	389	void op_dadd (void)
390	390	{
391	391	T0 += T1;
392		RETURN();
	392	FORCE_RET();
393	393	}
394	394
395	395	void op_daddo (void)
...	...
402	402	/* operands of same sign, result different sign */
403	403	CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
404	404	}
405		RETURN();
	405	FORCE_RET();
406	406	}
407	407
408	408	void op_dsub (void)
409	409	{
410	410	T0 -= T1;
411		RETURN();
	411	FORCE_RET();
412	412	}
413	413
414	414	void op_dsubo (void)
...	...
421	421	/* operands of different sign, first operand and result different sign */
422	422	CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
423	423	}
424		RETURN();
	424	FORCE_RET();
425	425	}
426	426
427	427	void op_dmul (void)
428	428	{
429	429	T0 = (int64_t)T0 * (int64_t)T1;
430		RETURN();
	430	FORCE_RET();
431	431	}
432	432
433	433	/* Those might call libgcc functions. */
434	434	void op_ddiv (void)
435	435	{
436	436	do_ddiv();
437		RETURN();
	437	FORCE_RET();
438	438	}
439	439
440	440	#if TARGET_LONG_BITS > HOST_LONG_BITS
441	441	void op_ddivu (void)
442	442	{
443	443	do_ddivu();
444		RETURN();
	444	FORCE_RET();
445	445	}
446	446	#else
447	447	void op_ddivu (void)
...	...
450	450	env->LO[0][env->current_tc] = T0 / T1;
451	451	env->HI[0][env->current_tc] = T0 % T1;
452	452	}
453		RETURN();
	453	FORCE_RET();
454	454	}
455	455	#endif
456	456	#endif /* TARGET_MIPS64 */
...	...
459	459	void op_and (void)
460	460	{
461	461	T0 &= T1;
462		RETURN();
	462	FORCE_RET();
463	463	}
464	464
465	465	void op_nor (void)
466	466	{
467	467	T0 = ~(T0 \| T1);
468		RETURN();
	468	FORCE_RET();
469	469	}
470	470
471	471	void op_or (void)
472	472	{
473	473	T0 \|= T1;
474		RETURN();
	474	FORCE_RET();
475	475	}
476	476
477	477	void op_xor (void)
478	478	{
479	479	T0 ^= T1;
480		RETURN();
	480	FORCE_RET();
481	481	}
482	482
483	483	void op_sll (void)
484	484	{
485	485	T0 = (int32_t)((uint32_t)T0 << T1);
486		RETURN();
	486	FORCE_RET();
487	487	}
488	488
489	489	void op_sra (void)
490	490	{
491	491	T0 = (int32_t)((int32_t)T0 >> T1);
492		RETURN();
	492	FORCE_RET();
493	493	}
494	494
495	495	void op_srl (void)
496	496	{
497	497	T0 = (int32_t)((uint32_t)T0 >> T1);
498		RETURN();
	498	FORCE_RET();
499	499	}
500	500
501	501	void op_rotr (void)
...	...
506	506	tmp = (int32_t)((uint32_t)T0 << (0x20 - T1));
507	507	T0 = (int32_t)((uint32_t)T0 >> T1) \| tmp;
508	508	}
509		RETURN();
	509	FORCE_RET();
510	510	}
511	511
512	512	void op_sllv (void)
513	513	{
514	514	T0 = (int32_t)((uint32_t)T1 << ((uint32_t)T0 & 0x1F));
515		RETURN();
	515	FORCE_RET();
516	516	}
517	517
518	518	void op_srav (void)
519	519	{
520	520	T0 = (int32_t)((int32_t)T1 >> (T0 & 0x1F));
521		RETURN();
	521	FORCE_RET();
522	522	}
523	523
524	524	void op_srlv (void)
525	525	{
526	526	T0 = (int32_t)((uint32_t)T1 >> (T0 & 0x1F));
527		RETURN();
	527	FORCE_RET();
528	528	}
529	529
530	530	void op_rotrv (void)
...	...
537	537	T0 = (int32_t)((uint32_t)T1 >> T0) \| tmp;
538	538	} else
539	539	T0 = T1;
540		RETURN();
	540	FORCE_RET();
541	541	}
542	542
543	543	void op_clo (void)
544	544	{
545	545	T0 = clo32(T0);
546		RETURN();
	546	FORCE_RET();
547	547	}
548	548
549	549	void op_clz (void)
550	550	{
551	551	T0 = clz32(T0);
552		RETURN();
	552	FORCE_RET();
553	553	}
554	554
555	555	#if defined(TARGET_MIPS64)
...	...
559	559	void op_dsll (void)
560	560	{
561	561	CALL_FROM_TB0(do_dsll);
562		RETURN();
	562	FORCE_RET();
563	563	}
564	564
565	565	void op_dsll32 (void)
566	566	{
567	567	CALL_FROM_TB0(do_dsll32);
568		RETURN();
	568	FORCE_RET();
569	569	}
570	570
571	571	void op_dsra (void)
572	572	{
573	573	CALL_FROM_TB0(do_dsra);
574		RETURN();
	574	FORCE_RET();
575	575	}
576	576
577	577	void op_dsra32 (void)
578	578	{
579	579	CALL_FROM_TB0(do_dsra32);
580		RETURN();
	580	FORCE_RET();
581	581	}
582	582
583	583	void op_dsrl (void)
584	584	{
585	585	CALL_FROM_TB0(do_dsrl);
586		RETURN();
	586	FORCE_RET();
587	587	}
588	588
589	589	void op_dsrl32 (void)
590	590	{
591	591	CALL_FROM_TB0(do_dsrl32);
592		RETURN();
	592	FORCE_RET();
593	593	}
594	594
595	595	void op_drotr (void)
596	596	{
597	597	CALL_FROM_TB0(do_drotr);
598		RETURN();
	598	FORCE_RET();
599	599	}
600	600
601	601	void op_drotr32 (void)
602	602	{
603	603	CALL_FROM_TB0(do_drotr32);
604		RETURN();
	604	FORCE_RET();
605	605	}
606	606
607	607	void op_dsllv (void)
608	608	{
609	609	CALL_FROM_TB0(do_dsllv);
610		RETURN();
	610	FORCE_RET();
611	611	}
612	612
613	613	void op_dsrav (void)
614	614	{
615	615	CALL_FROM_TB0(do_dsrav);
616		RETURN();
	616	FORCE_RET();
617	617	}
618	618
619	619	void op_dsrlv (void)
620	620	{
621	621	CALL_FROM_TB0(do_dsrlv);
622		RETURN();
	622	FORCE_RET();
623	623	}
624	624
625	625	void op_drotrv (void)
626	626	{
627	627	CALL_FROM_TB0(do_drotrv);
628		RETURN();
	628	FORCE_RET();
629	629	}
630	630
631	631	void op_dclo (void)
632	632	{
633	633	CALL_FROM_TB0(do_dclo);
634		RETURN();
	634	FORCE_RET();
635	635	}
636	636
637	637	void op_dclz (void)
638	638	{
639	639	CALL_FROM_TB0(do_dclz);
640		RETURN();
	640	FORCE_RET();
641	641	}
642	642
643	643	#else /* TARGET_LONG_BITS > HOST_LONG_BITS */
...	...
645	645	void op_dsll (void)
646	646	{
647	647	T0 = T0 << T1;
648		RETURN();
	648	FORCE_RET();
649	649	}
650	650
651	651	void op_dsll32 (void)
652	652	{
653	653	T0 = T0 << (T1 + 32);
654		RETURN();
	654	FORCE_RET();
655	655	}
656	656
657	657	void op_dsra (void)
658	658	{
659	659	T0 = (int64_t)T0 >> T1;
660		RETURN();
	660	FORCE_RET();
661	661	}
662	662
663	663	void op_dsra32 (void)
664	664	{
665	665	T0 = (int64_t)T0 >> (T1 + 32);
666		RETURN();
	666	FORCE_RET();
667	667	}
668	668
669	669	void op_dsrl (void)
670	670	{
671	671	T0 = T0 >> T1;
672		RETURN();
	672	FORCE_RET();
673	673	}
674	674
675	675	void op_dsrl32 (void)
676	676	{
677	677	T0 = T0 >> (T1 + 32);
678		RETURN();
	678	FORCE_RET();
679	679	}
680	680
681	681	void op_drotr (void)
...	...
686	686	tmp = T0 << (0x40 - T1);
687	687	T0 = (T0 >> T1) \| tmp;
688	688	}
689		RETURN();
	689	FORCE_RET();
690	690	}
691	691
692	692	void op_drotr32 (void)
...	...
697	697	tmp = T0 << (0x40 - (32 + T1));
698	698	T0 = (T0 >> (32 + T1)) \| tmp;
699	699	}
700		RETURN();
	700	FORCE_RET();
701	701	}
702	702
703	703	void op_dsllv (void)
704	704	{
705	705	T0 = T1 << (T0 & 0x3F);
706		RETURN();
	706	FORCE_RET();
707	707	}
708	708
709	709	void op_dsrav (void)
710	710	{
711	711	T0 = (int64_t)T1 >> (T0 & 0x3F);
712		RETURN();
	712	FORCE_RET();
713	713	}
714	714
715	715	void op_dsrlv (void)
716	716	{
717	717	T0 = T1 >> (T0 & 0x3F);
718		RETURN();
	718	FORCE_RET();
719	719	}
720	720
721	721	void op_drotrv (void)
...	...
728	728	T0 = (T1 >> T0) \| tmp;
729	729	} else
730	730	T0 = T1;
731		RETURN();
	731	FORCE_RET();
732	732	}
733	733
734	734	void op_dclo (void)
735	735	{
736	736	T0 = clo64(T0);
737		RETURN();
	737	FORCE_RET();
738	738	}
739	739
740	740	void op_dclz (void)
741	741	{
742	742	T0 = clz64(T0);
743		RETURN();
	743	FORCE_RET();
744	744	}
745	745	#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
746	746	#endif /* TARGET_MIPS64 */
...	...
750	750	void op_mult (void)
751	751	{
752	752	CALL_FROM_TB0(do_mult);
753		RETURN();
	753	FORCE_RET();
754	754	}
755	755
756	756	void op_multu (void)
757	757	{
758	758	CALL_FROM_TB0(do_multu);
759		RETURN();
	759	FORCE_RET();
760	760	}
761	761
762	762	void op_madd (void)
763	763	{
764	764	CALL_FROM_TB0(do_madd);
765		RETURN();
	765	FORCE_RET();
766	766	}
767	767
768	768	void op_maddu (void)
769	769	{
770	770	CALL_FROM_TB0(do_maddu);
771		RETURN();
	771	FORCE_RET();
772	772	}
773	773
774	774	void op_msub (void)
775	775	{
776	776	CALL_FROM_TB0(do_msub);
777		RETURN();
	777	FORCE_RET();
778	778	}
779	779
780	780	void op_msubu (void)
781	781	{
782	782	CALL_FROM_TB0(do_msubu);
783		RETURN();
	783	FORCE_RET();
784	784	}
785	785
786	786	#else /* TARGET_LONG_BITS > HOST_LONG_BITS */
...	...
800	800	void op_mult (void)
801	801	{
802	802	set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
803		RETURN();
	803	FORCE_RET();
804	804	}
805	805
806	806	void op_multu (void)
807	807	{
808	808	set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
809		RETURN();
	809	FORCE_RET();
810	810	}
811	811
812	812	void op_madd (void)
...	...
815	815
816	816	tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
817	817	set_HILO((int64_t)get_HILO() + tmp);
818		RETURN();
	818	FORCE_RET();
819	819	}
820	820
821	821	void op_maddu (void)
...	...
824	824
825	825	tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
826	826	set_HILO(get_HILO() + tmp);
827		RETURN();
	827	FORCE_RET();
828	828	}
829	829
830	830	void op_msub (void)
...	...
833	833
834	834	tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
835	835	set_HILO((int64_t)get_HILO() - tmp);
836		RETURN();
	836	FORCE_RET();
837	837	}
838	838
839	839	void op_msubu (void)
...	...
842	842
843	843	tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
844	844	set_HILO(get_HILO() - tmp);
845		RETURN();
	845	FORCE_RET();
846	846	}
847	847	#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
848	848
...	...
850	850	void op_dmult (void)
851	851	{
852	852	CALL_FROM_TB4(muls64, &(env->LO[0][env->current_tc]), &(env->HI[0][env->current_tc]), T0, T1);
853		RETURN();
	853	FORCE_RET();
854	854	}
855	855
856	856	void op_dmultu (void)
857	857	{
858	858	CALL_FROM_TB4(mulu64, &(env->LO[0][env->current_tc]), &(env->HI[0][env->current_tc]), T0, T1);
859		RETURN();
	859	FORCE_RET();
860	860	}
861	861	#endif
862	862
...	...
865	865	{
866	866	if (T1 != 0)
867	867	env->gpr[PARAM1][env->current_tc] = T0;
868		RETURN();
	868	FORCE_RET();
869	869	}
870	870
871	871	void op_movz (void)
872	872	{
873	873	if (T1 == 0)
874	874	env->gpr[PARAM1][env->current_tc] = T0;
875		RETURN();
	875	FORCE_RET();
876	876	}
877	877
878	878	void op_movf (void)
879	879	{
880	880	if (!(env->fpu->fcr31 & PARAM1))
881	881	T0 = T1;
882		RETURN();
	882	FORCE_RET();
883	883	}
884	884
885	885	void op_movt (void)
886	886	{
887	887	if (env->fpu->fcr31 & PARAM1)
888	888	T0 = T1;
889		RETURN();
	889	FORCE_RET();
890	890	}
891	891
892	892	/* Tests */
...	...
898	898	} else { \
899	899	T0 = 0; \
900	900	} \
901		RETURN(); \
	901	FORCE_RET(); \
902	902	}
903	903
904	904	OP_COND(eq, T0 == T1);
...	...
916	916	void OPPROTO op_goto_tb0(void)
917	917	{
918	918	GOTO_TB(op_goto_tb0, PARAM1, 0);
919		RETURN();
	919	FORCE_RET();
920	920	}
921	921
922	922	void OPPROTO op_goto_tb1(void)
923	923	{
924	924	GOTO_TB(op_goto_tb1, PARAM1, 1);
925		RETURN();
	925	FORCE_RET();
926	926	}
927	927
928	928	/* Branch to register */
929	929	void op_save_breg_target (void)
930	930	{
931	931	env->btarget = T2;
932		RETURN();
	932	FORCE_RET();
933	933	}
934	934
935	935	void op_restore_breg_target (void)
936	936	{
937	937	T2 = env->btarget;
938		RETURN();
	938	FORCE_RET();
939	939	}
940	940
941	941	void op_breg (void)
942	942	{
943	943	env->PC[env->current_tc] = T2;
944		RETURN();
	944	FORCE_RET();
945	945	}
946	946
947	947	void op_save_btarget (void)
948	948	{
949	949	env->btarget = PARAM1;
950		RETURN();
	950	FORCE_RET();
951	951	}
952	952
953	953	#if defined(TARGET_MIPS64)
954	954	void op_save_btarget64 (void)
955	955	{
956	956	env->btarget = ((uint64_t)PARAM1 << 32) \| (uint32_t)PARAM2;
957		RETURN();
	957	FORCE_RET();
958	958	}
959	959	#endif
960	960
...	...
962	962	void op_set_bcond (void)
963	963	{
964	964	T2 = T0;
965		RETURN();
	965	FORCE_RET();
966	966	}
967	967
968	968	void op_save_bcond (void)
969	969	{
970	970	env->bcond = T2;
971		RETURN();
	971	FORCE_RET();
972	972	}
973	973
974	974	void op_restore_bcond (void)
975	975	{
976	976	T2 = env->bcond;
977		RETURN();
	977	FORCE_RET();
978	978	}
979	979
980	980	void op_jnz_T2 (void)
981	981	{
982	982	if (T2)
983	983	GOTO_LABEL_PARAM(1);
984		RETURN();
	984	FORCE_RET();
985	985	}
986	986
987	987	/* CP0 functions */
988	988	void op_mfc0_index (void)
989	989	{
990	990	T0 = env->CP0_Index;
991		RETURN();
	991	FORCE_RET();
992	992	}
993	993
994	994	void op_mfc0_mvpcontrol (void)
995	995	{
996	996	T0 = env->mvp->CP0_MVPControl;
997		RETURN();
	997	FORCE_RET();
998	998	}
999	999
1000	1000	void op_mfc0_mvpconf0 (void)
1001	1001	{
1002	1002	T0 = env->mvp->CP0_MVPConf0;
1003		RETURN();
	1003	FORCE_RET();
1004	1004	}
1005	1005
1006	1006	void op_mfc0_mvpconf1 (void)
1007	1007	{
1008	1008	T0 = env->mvp->CP0_MVPConf1;
1009		RETURN();
	1009	FORCE_RET();
1010	1010	}
1011	1011
1012	1012	void op_mfc0_random (void)
1013	1013	{
1014	1014	CALL_FROM_TB0(do_mfc0_random);
1015		RETURN();
	1015	FORCE_RET();
1016	1016	}
1017	1017
1018	1018	void op_mfc0_vpecontrol (void)
1019	1019	{
1020	1020	T0 = env->CP0_VPEControl;
1021		RETURN();
	1021	FORCE_RET();
1022	1022	}
1023	1023
1024	1024	void op_mfc0_vpeconf0 (void)
1025	1025	{
1026	1026	T0 = env->CP0_VPEConf0;
1027		RETURN();
	1027	FORCE_RET();
1028	1028	}
1029	1029
1030	1030	void op_mfc0_vpeconf1 (void)
1031	1031	{
1032	1032	T0 = env->CP0_VPEConf1;
1033		RETURN();
	1033	FORCE_RET();
1034	1034	}
1035	1035
1036	1036	void op_mfc0_yqmask (void)
1037	1037	{
1038	1038	T0 = env->CP0_YQMask;
1039		RETURN();
	1039	FORCE_RET();
1040	1040	}
1041	1041
1042	1042	void op_mfc0_vpeschedule (void)
1043	1043	{
1044	1044	T0 = env->CP0_VPESchedule;
1045		RETURN();
	1045	FORCE_RET();
1046	1046	}
1047	1047
1048	1048	void op_mfc0_vpeschefback (void)
1049	1049	{
1050	1050	T0 = env->CP0_VPEScheFBack;
1051		RETURN();
	1051	FORCE_RET();
1052	1052	}
1053	1053
1054	1054	void op_mfc0_vpeopt (void)
1055	1055	{
1056	1056	T0 = env->CP0_VPEOpt;
1057		RETURN();
	1057	FORCE_RET();
1058	1058	}
1059	1059
1060	1060	void op_mfc0_entrylo0 (void)
1061	1061	{
1062	1062	T0 = (int32_t)env->CP0_EntryLo0;
1063		RETURN();
	1063	FORCE_RET();
1064	1064	}
1065	1065
1066	1066	void op_mfc0_tcstatus (void)
1067	1067	{
1068	1068	T0 = env->CP0_TCStatus[env->current_tc];
1069		RETURN();
	1069	FORCE_RET();
1070	1070	}
1071	1071
1072	1072	void op_mftc0_tcstatus(void)
...	...
1074	1074	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1075	1075
1076	1076	T0 = env->CP0_TCStatus[other_tc];
1077		RETURN();
	1077	FORCE_RET();
1078	1078	}
1079	1079
1080	1080	void op_mfc0_tcbind (void)
1081	1081	{
1082	1082	T0 = env->CP0_TCBind[env->current_tc];
1083		RETURN();
	1083	FORCE_RET();
1084	1084	}
1085	1085
1086	1086	void op_mftc0_tcbind(void)
...	...
1088	1088	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1089	1089
1090	1090	T0 = env->CP0_TCBind[other_tc];
1091		RETURN();
	1091	FORCE_RET();
1092	1092	}
1093	1093
1094	1094	void op_mfc0_tcrestart (void)
1095	1095	{
1096	1096	T0 = env->PC[env->current_tc];
1097		RETURN();
	1097	FORCE_RET();
1098	1098	}
1099	1099
1100	1100	void op_mftc0_tcrestart(void)
...	...
1102	1102	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1103	1103
1104	1104	T0 = env->PC[other_tc];
1105		RETURN();
	1105	FORCE_RET();
1106	1106	}
1107	1107
1108	1108	void op_mfc0_tchalt (void)
1109	1109	{
1110	1110	T0 = env->CP0_TCHalt[env->current_tc];
1111		RETURN();
	1111	FORCE_RET();
1112	1112	}
1113	1113
1114	1114	void op_mftc0_tchalt(void)
...	...
1116	1116	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1117	1117
1118	1118	T0 = env->CP0_TCHalt[other_tc];
1119		RETURN();
	1119	FORCE_RET();
1120	1120	}
1121	1121
1122	1122	void op_mfc0_tccontext (void)
1123	1123	{
1124	1124	T0 = env->CP0_TCContext[env->current_tc];
1125		RETURN();
	1125	FORCE_RET();
1126	1126	}
1127	1127
1128	1128	void op_mftc0_tccontext(void)
...	...
1130	1130	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1131	1131
1132	1132	T0 = env->CP0_TCContext[other_tc];
1133		RETURN();
	1133	FORCE_RET();
1134	1134	}
1135	1135
1136	1136	void op_mfc0_tcschedule (void)
1137	1137	{
1138	1138	T0 = env->CP0_TCSchedule[env->current_tc];
1139		RETURN();
	1139	FORCE_RET();
1140	1140	}
1141	1141
1142	1142	void op_mftc0_tcschedule(void)
...	...
1144	1144	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1145	1145
1146	1146	T0 = env->CP0_TCSchedule[other_tc];
1147		RETURN();
	1147	FORCE_RET();
1148	1148	}
1149	1149
1150	1150	void op_mfc0_tcschefback (void)
1151	1151	{
1152	1152	T0 = env->CP0_TCScheFBack[env->current_tc];
1153		RETURN();
	1153	FORCE_RET();
1154	1154	}
1155	1155
1156	1156	void op_mftc0_tcschefback(void)
...	...
1158	1158	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1159	1159
1160	1160	T0 = env->CP0_TCScheFBack[other_tc];
1161		RETURN();
	1161	FORCE_RET();
1162	1162	}
1163	1163
1164	1164	void op_mfc0_entrylo1 (void)
1165	1165	{
1166	1166	T0 = (int32_t)env->CP0_EntryLo1;
1167		RETURN();
	1167	FORCE_RET();
1168	1168	}
1169	1169
1170	1170	void op_mfc0_context (void)
1171	1171	{
1172	1172	T0 = (int32_t)env->CP0_Context;
1173		RETURN();
	1173	FORCE_RET();
1174	1174	}
1175	1175
1176	1176	void op_mfc0_pagemask (void)
1177	1177	{
1178	1178	T0 = env->CP0_PageMask;
1179		RETURN();
	1179	FORCE_RET();
1180	1180	}
1181	1181
1182	1182	void op_mfc0_pagegrain (void)
1183	1183	{
1184	1184	T0 = env->CP0_PageGrain;
1185		RETURN();
	1185	FORCE_RET();
1186	1186	}
1187	1187
1188	1188	void op_mfc0_wired (void)
1189	1189	{
1190	1190	T0 = env->CP0_Wired;
1191		RETURN();
	1191	FORCE_RET();
1192	1192	}
1193	1193
1194	1194	void op_mfc0_srsconf0 (void)
1195	1195	{
1196	1196	T0 = env->CP0_SRSConf0;
1197		RETURN();
	1197	FORCE_RET();
1198	1198	}
1199	1199
1200	1200	void op_mfc0_srsconf1 (void)
1201	1201	{
1202	1202	T0 = env->CP0_SRSConf1;
1203		RETURN();
	1203	FORCE_RET();
1204	1204	}
1205	1205
1206	1206	void op_mfc0_srsconf2 (void)
1207	1207	{
1208	1208	T0 = env->CP0_SRSConf2;
1209		RETURN();
	1209	FORCE_RET();
1210	1210	}
1211	1211
1212	1212	void op_mfc0_srsconf3 (void)
1213	1213	{
1214	1214	T0 = env->CP0_SRSConf3;
1215		RETURN();
	1215	FORCE_RET();
1216	1216	}
1217	1217
1218	1218	void op_mfc0_srsconf4 (void)
1219	1219	{
1220	1220	T0 = env->CP0_SRSConf4;
1221		RETURN();
	1221	FORCE_RET();
1222	1222	}
1223	1223
1224	1224	void op_mfc0_hwrena (void)
1225	1225	{
1226	1226	T0 = env->CP0_HWREna;
1227		RETURN();
	1227	FORCE_RET();
1228	1228	}
1229	1229
1230	1230	void op_mfc0_badvaddr (void)
1231	1231	{
1232	1232	T0 = (int32_t)env->CP0_BadVAddr;
1233		RETURN();
	1233	FORCE_RET();
1234	1234	}
1235	1235
1236	1236	void op_mfc0_count (void)
1237	1237	{
1238	1238	CALL_FROM_TB0(do_mfc0_count);
1239		RETURN();
	1239	FORCE_RET();
1240	1240	}
1241	1241
1242	1242	void op_mfc0_entryhi (void)
1243	1243	{
1244	1244	T0 = (int32_t)env->CP0_EntryHi;
1245		RETURN();
	1245	FORCE_RET();
1246	1246	}
1247	1247
1248	1248	void op_mftc0_entryhi(void)
...	...
1250	1250	int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1251	1251
1252	1252	T0 = (env->CP0_EntryHi & ~0xff) \| (env->CP0_TCStatus[other_tc] & 0xff);
1253		RETURN();
	1253	FORCE_RET();
1254	1254	}
1255	1255
1256	1256	void op_mfc0_compare (void)
1257	1257	{
1258	1258	T0 = env->CP0_Compare;
1259		RETURN();
	1259	FORCE_RET();
1260	1260	}
1261	1261
1262	1262	void op_mfc0_status (void)
1263	1263	{
1264	1264	T0 = env->CP0_Status;
1265		RETURN();
	1265	FORCE_RET();
1266	1266	}
1267	1267
1268	1268	void op_mftc0_status(void)
...	...
1274	1274	T0 \|= tcstatus & (0xf << CP0TCSt_TCU0);
1275	1275	T0 \|= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX);
1276	1276	T0 \|= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU);
1277		RETURN();
	1277	FORCE_RET();
1278	1278	}
1279	1279
1280	1280	void op_mfc0_intctl (void)
1281	1281	{
1282	1282	T0 = env->CP0_IntCtl;
1283		RETURN();
	1283	FORCE_RET();
1284	1284	}
1285	1285
1286	1286	void op_mfc0_srsctl (void)
1287	1287	{
1288	1288	T0 = env->CP0_SRSCtl;
1289		RETURN();
	1289	FORCE_RET();
1290	1290	}
1291	1291
1292	1292	void op_mfc0_srsmap (void)
1293	1293	{
1294	1294	T0 = env->CP0_SRSMap;
1295		RETURN();
	1295	FORCE_RET();
1296	1296	}
1297	1297
1298	1298	void op_mfc0_cause (void)
1299	1299	{
1300	1300	T0 = env->CP0_Cause;
1301		RETURN();
	1301	FORCE_RET();
1302	1302	}
1303	1303
1304	1304	void op_mfc0_epc (void)
1305	1305	{
1306	1306	T0 = (int32_t)env->CP0_EPC;
1307		RETURN();
	1307	FORCE_RET();
1308	1308	}
1309	1309
1310	1310	void op_mfc0_prid (void)
1311	1311	{
1312	1312	T0 = env->CP0_PRid;
1313		RETURN();
	1313	FORCE_RET();
1314	1314	}
1315	1315
1316	1316	void op_mfc0_ebase (void)
1317	1317	{
1318	1318	T0 = env->CP0_EBase;
1319		RETURN();
	1319	FORCE_RET();
1320	1320	}
1321	1321
1322	1322	void op_mfc0_config0 (void)
1323	1323	{
1324	1324	T0 = env->CP0_Config0;
1325		RETURN();
	1325	FORCE_RET();
1326	1326	}
1327	1327
1328	1328	void op_mfc0_config1 (void)
1329	1329	{
1330	1330	T0 = env->CP0_Config1;
1331		RETURN();
	1331	FORCE_RET();
1332	1332	}
1333	1333
1334	1334	void op_mfc0_config2 (void)
1335	1335	{
1336	1336	T0 = env->CP0_Config2;
1337		RETURN();
	1337	FORCE_RET();
1338	1338	}
1339	1339
1340	1340	void op_mfc0_config3 (void)
1341	1341	{
1342	1342	T0 = env->CP0_Config3;
1343		RETURN();
	1343	FORCE_RET();
1344	1344	}
1345	1345
1346	1346	void op_mfc0_config6 (void)
1347	1347	{
1348	1348	T0 = env->CP0_Config6;
1349		RETURN();
	1349	FORCE_RET();
1350	1350	}
1351	1351
1352	1352	void op_mfc0_config7 (void)
1353	1353	{
1354	1354	T0 = env->CP0_Config7;
1355		RETURN();
	1355	FORCE_RET();
1356	1356	}
1357	1357
1358	1358	void op_mfc0_lladdr (void)
1359	1359	{
1360	1360	T0 = (int32_t)env->CP0_LLAddr >> 4;
1361		RETURN();
	1361	FORCE_RET();
1362	1362	}
1363	1363
1364	1364	void op_mfc0_watchlo (void)
1365	1365	{
1366	1366	T0 = (int32_t)env->CP0_WatchLo[PARAM1];
1367		RETURN();
	1367	FORCE_RET();
1368	1368	}
1369	1369
1370	1370	void op_mfc0_watchhi (void)
1371	1371	{
1372	1372	T0 = env->CP0_WatchHi[PARAM1];
1373		RETURN();
	1373	FORCE_RET();
1374	1374	}
1375	1375
1376	1376	void op_mfc0_xcontext (void)
1377	1377	{
1378	1378	T0 = (int32_t)env->CP0_XContext;
1379		RETURN();
	1379	FORCE_RET();
1380	1380	}
1381	1381
1382	1382	void op_mfc0_framemask (void)
1383	1383	{
1384	1384	T0 = env->CP0_Framemask;
1385		RETURN();
	1385	FORCE_RET();
1386	1386	}
1387	1387
1388	1388	void op_mfc0_debug (void)
...	...
1390	1390	T0 = env->CP0_Debug;
1391	1391	if (env->hflags & MIPS_HFLAG_DM)
1392	1392	T0 \|= 1 << CP0DB_DM;
1393		RETURN();
	1393	FORCE_RET();
1394	1394	}
1395	1395
1396	1396	void op_mftc0_debug(void)
...	...
1401	1401	T0 = (env->CP0_Debug & ~((1 << CP0DB_SSt) \| (1 << CP0DB_Halt))) \|
1402	1402	(env->CP0_Debug_tcstatus[other_tc] &
1403	1403	((1 << CP0DB_SSt) \| (1 << CP0DB_Halt)));
1404		RETURN();
	1404	FORCE_RET();
1405	1405	}
1406	1406
1407	1407	void op_mfc0_depc (void)
1408	1408	{
1409	1409	T0 = (int32_t)env->CP0_DEPC;
1410		RETURN();
	1410	FORCE_RET();
1411	1411	}
1412	1412
1413	1413	void op_mfc0_performance0 (void)
1414	1414	{
1415	1415	T0 = env->CP0_Performance0;
1416		RETURN();
	1416	FORCE_RET();
1417	1417	}
1418	1418
1419	1419	void op_mfc0_taglo (void)
1420	1420	{
1421	1421	T0 = env->CP0_TagLo;
1422		RETURN();
	1422	FORCE_RET();
1423	1423	}
1424	1424
1425	1425	void op_mfc0_datalo (void)
1426	1426	{
1427	1427	T0 = env->CP0_DataLo;
1428		RETURN();
	1428	FORCE_RET();
1429	1429	}
1430	1430
1431	1431	void op_mfc0_taghi (void)
1432	1432	{
1433	1433	T0 = env->CP0_TagHi;
1434		RETURN();
	1434	FORCE_RET();
1435	1435	}
1436	1436
1437	1437	void op_mfc0_datahi (void)
1438	1438	{
1439	1439	T0 = env->CP0_DataHi;
1440		RETURN();
	1440	FORCE_RET();
1441	1441	}
1442	1442
1443	1443	void op_mfc0_errorepc (void)
1444	1444	{
1445	1445	T0 = (int32_t)env->CP0_ErrorEPC;
1446		RETURN();
	1446	FORCE_RET();
1447	1447	}
1448	1448
1449	1449	void op_mfc0_desave (void)
1450	1450	{
1451	1451	T0 = env->CP0_DESAVE;
1452		RETURN();
	1452	FORCE_RET();
1453	1453	}
1454	1454
1455	1455	void op_mtc0_index (void)
...	...
1462	1462	num <<= 1;
1463	1463	} while (tmp);
1464	1464	env->CP0_Index = (env->CP0_Index & 0x80000000) \| (T0 & (num - 1));
1465		RETURN();
	1465	FORCE_RET();
1466	1466	}
1467	1467
1468	1468	void op_mtc0_mvpcontrol (void)
...	...
1480	1480	// TODO: Enable/disable shared TLB, enable/disable VPEs.
1481	1481
1482	1482	env->mvp->CP0_MVPControl = newval;
1483		RETURN();
	1483	FORCE_RET();
1484	1484	}
1485	1485
1486	1486	void op_mtc0_vpecontrol (void)
...	...
1498	1498	// TODO: Enable/disable TCs.
1499	1499
1500	1500	env->CP0_VPEControl = newval;
1501		RETURN();
	1501	FORCE_RET();
1502	1502	}
1503	1503
1504	1504	void op_mtc0_vpeconf0 (void)
...	...
1516	1516	// TODO: TC exclusive handling due to ERL/EXL.
1517	1517
1518	1518	env->CP0_VPEConf0 = newval;
1519		RETURN();
	1519	FORCE_RET();
1520	1520	}
1521	1521
1522	1522	void op_mtc0_vpeconf1 (void)
...	...
1535	1535	// TODO: Handle FPU (CP1) binding.
1536	1536
1537	1537	env->CP0_VPEConf1 = newval;
1538		RETURN();
	1538	FORCE_RET();
1539	1539	}
1540	1540
1541	1541	void op_mtc0_yqmask (void)
1542	1542	{
1543	1543	/* Yield qualifier inputs not implemented. */
1544	1544	env->CP0_YQMask = 0x00000000;
1545		RETURN();
	1545	FORCE_RET();
1546	1546	}
1547	1547
1548	1548	void op_mtc0_vpeschedule (void)
1549	1549	{
1550	1550	env->CP0_VPESchedule = T0;
1551		RETURN();
	1551	FORCE_RET();
1552	1552	}
1553	1553
1554	1554	void op_mtc0_vpeschefback (void)
1555	1555	{
1556	1556	env->CP0_VPEScheFBack = T0;
1557		RETURN();
	1557	FORCE_RET();
1558	1558	}
1559	1559
1560	1560	void op_mtc0_vpeopt (void)
1561	1561	{
1562	1562	env->CP0_VPEOpt = T0 & 0x0000ffff;
1563		RETURN();
	1563	FORCE_RET();
1564	1564	}
1565	1565
1566	1566	void op_mtc0_entrylo0 (void)
...	...
1568	1568	/* Large physaddr not implemented */
1569	1569	/* 1k pages not implemented */
1570	1570	env->CP0_EntryLo0 = T0 & 0x3FFFFFFF;
1571		RETURN();
	1571	FORCE_RET();
1572	1572	}
1573	1573
1574	1574	void op_mtc0_tcstatus (void)
...	...
1581	1581	// TODO: Sync with CP0_Status.
1582	1582
1583	1583	env->CP0_TCStatus[env->current_tc] = newval;
1584		RETURN();
	1584	FORCE_RET();
1585	1585	}
1586	1586
1587	1587	void op_mttc0_tcstatus (void)
...	...
1591	1591	// TODO: Sync with CP0_Status.
1592	1592
1593	1593	env->CP0_TCStatus[other_tc] = T0;
1594		RETURN();
	1594	FORCE_RET();
1595	1595	}
1596	1596
1597	1597	void op_mtc0_tcbind (void)
...	...
1603	1603	mask \|= (1 << CP0TCBd_CurVPE);
1604	1604	newval = (env->CP0_TCBind[env->current_tc] & ~mask) \| (T0 & mask);
1605	1605	env->CP0_TCBind[env->current_tc] = newval;
1606		RETURN();
	1606	FORCE_RET();
1607	1607	}
1608	1608
1609	1609	void op_mttc0_tcbind (void)
...	...
1616	1616	mask \|= (1 << CP0TCBd_CurVPE);
1617	1617	newval = (env->CP0_TCBind[other_tc] & ~mask) \| (T0 & mask);
1618	1618	env->CP0_TCBind[other_tc] = newval;
1619		RETURN();
	1619	FORCE_RET();
1620	1620	}
1621	1621
1622	1622	void op_mtc0_tcrestart (void)
...	...
1625	1625	env->CP0_TCStatus[env->current_tc] &= ~(1 << CP0TCSt_TDS);
1626	1626	env->CP0_LLAddr = 0ULL;
1627	1627	/* MIPS16 not implemented. */
1628		RETURN();
	1628	FORCE_RET();
1629	1629	}
1630	1630
1631	1631	void op_mttc0_tcrestart (void)
...	...
1636	1636	env->CP0_TCStatus[other_tc] &= ~(1 << CP0TCSt_TDS);
1637	1637	env->CP0_LLAddr = 0ULL;
1638	1638	/* MIPS16 not implemented. */
1639		RETURN();
	1639	FORCE_RET();
1640	1640	}
1641	1641
1642	1642	void op_mtc0_tchalt (void)
...	...
1645	1645
1646	1646	// TODO: Halt TC / Restart (if allocated+active) TC.

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Archipelago » qemu

Revision 8f6f6026