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1 | 2c0262af | bellard | /*
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2 | 2c0262af | bellard | * ARM translation
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3 | 5fafdf24 | ths | *
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4 | 2c0262af | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 9ee6e8bb | pbrook | * Copyright (c) 2005-2007 CodeSourcery
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6 | 18c9b560 | balrog | * Copyright (c) 2007 OpenedHand, Ltd.
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7 | 2c0262af | bellard | *
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8 | 2c0262af | bellard | * This library is free software; you can redistribute it and/or
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9 | 2c0262af | bellard | * modify it under the terms of the GNU Lesser General Public
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10 | 2c0262af | bellard | * License as published by the Free Software Foundation; either
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11 | 2c0262af | bellard | * version 2 of the License, or (at your option) any later version.
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12 | 2c0262af | bellard | *
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13 | 2c0262af | bellard | * This library is distributed in the hope that it will be useful,
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14 | 2c0262af | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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15 | 2c0262af | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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16 | 2c0262af | bellard | * Lesser General Public License for more details.
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17 | 2c0262af | bellard | *
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18 | 2c0262af | bellard | * You should have received a copy of the GNU Lesser General Public
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19 | 2c0262af | bellard | * License along with this library; if not, write to the Free Software
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20 | 2c0262af | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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21 | 2c0262af | bellard | */
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22 | 2c0262af | bellard | #include <stdarg.h> |
23 | 2c0262af | bellard | #include <stdlib.h> |
24 | 2c0262af | bellard | #include <stdio.h> |
25 | 2c0262af | bellard | #include <string.h> |
26 | 2c0262af | bellard | #include <inttypes.h> |
27 | 2c0262af | bellard | |
28 | 2c0262af | bellard | #include "cpu.h" |
29 | 2c0262af | bellard | #include "exec-all.h" |
30 | 2c0262af | bellard | #include "disas.h" |
31 | 57fec1fe | bellard | #include "tcg-op.h" |
32 | 1497c961 | pbrook | |
33 | 1497c961 | pbrook | #define GEN_HELPER 1 |
34 | b26eefb6 | pbrook | #include "helpers.h" |
35 | 2c0262af | bellard | |
36 | 9ee6e8bb | pbrook | #define ENABLE_ARCH_5J 0 |
37 | 9ee6e8bb | pbrook | #define ENABLE_ARCH_6 arm_feature(env, ARM_FEATURE_V6)
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38 | 9ee6e8bb | pbrook | #define ENABLE_ARCH_6K arm_feature(env, ARM_FEATURE_V6K)
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39 | 9ee6e8bb | pbrook | #define ENABLE_ARCH_6T2 arm_feature(env, ARM_FEATURE_THUMB2)
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40 | 9ee6e8bb | pbrook | #define ENABLE_ARCH_7 arm_feature(env, ARM_FEATURE_V7)
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41 | b5ff1b31 | bellard | |
42 | b5ff1b31 | bellard | #define ARCH(x) if (!ENABLE_ARCH_##x) goto illegal_op; |
43 | b5ff1b31 | bellard | |
44 | 2c0262af | bellard | /* internal defines */
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45 | 2c0262af | bellard | typedef struct DisasContext { |
46 | 0fa85d43 | bellard | target_ulong pc; |
47 | 2c0262af | bellard | int is_jmp;
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48 | e50e6a20 | bellard | /* Nonzero if this instruction has been conditionally skipped. */
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49 | e50e6a20 | bellard | int condjmp;
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50 | e50e6a20 | bellard | /* The label that will be jumped to when the instruction is skipped. */
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51 | e50e6a20 | bellard | int condlabel;
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52 | 9ee6e8bb | pbrook | /* Thumb-2 condtional execution bits. */
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53 | 9ee6e8bb | pbrook | int condexec_mask;
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54 | 9ee6e8bb | pbrook | int condexec_cond;
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55 | 2c0262af | bellard | struct TranslationBlock *tb;
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56 | 8aaca4c0 | bellard | int singlestep_enabled;
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57 | 5899f386 | bellard | int thumb;
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58 | 6658ffb8 | pbrook | int is_mem;
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59 | b5ff1b31 | bellard | #if !defined(CONFIG_USER_ONLY)
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60 | b5ff1b31 | bellard | int user;
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61 | b5ff1b31 | bellard | #endif
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62 | 2c0262af | bellard | } DisasContext; |
63 | 2c0262af | bellard | |
64 | b5ff1b31 | bellard | #if defined(CONFIG_USER_ONLY)
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65 | b5ff1b31 | bellard | #define IS_USER(s) 1 |
66 | b5ff1b31 | bellard | #else
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67 | b5ff1b31 | bellard | #define IS_USER(s) (s->user)
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68 | b5ff1b31 | bellard | #endif
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69 | b5ff1b31 | bellard | |
70 | 9ee6e8bb | pbrook | /* These instructions trap after executing, so defer them until after the
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71 | 9ee6e8bb | pbrook | conditional executions state has been updated. */
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72 | 9ee6e8bb | pbrook | #define DISAS_WFI 4 |
73 | 9ee6e8bb | pbrook | #define DISAS_SWI 5 |
74 | 2c0262af | bellard | |
75 | 2c0262af | bellard | /* XXX: move that elsewhere */
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76 | 2c0262af | bellard | extern FILE *logfile;
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77 | 2c0262af | bellard | extern int loglevel; |
78 | 2c0262af | bellard | |
79 | b26eefb6 | pbrook | static TCGv cpu_env;
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80 | b26eefb6 | pbrook | /* FIXME: These should be removed. */
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81 | 8f8e3aa4 | pbrook | static TCGv cpu_T[2]; |
82 | 4373f3ce | pbrook | static TCGv cpu_F0s, cpu_F1s, cpu_F0d, cpu_F1d;
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83 | b26eefb6 | pbrook | |
84 | b26eefb6 | pbrook | /* initialize TCG globals. */
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85 | b26eefb6 | pbrook | void arm_translate_init(void) |
86 | b26eefb6 | pbrook | { |
87 | b26eefb6 | pbrook | cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
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88 | b26eefb6 | pbrook | |
89 | b26eefb6 | pbrook | cpu_T[0] = tcg_global_reg_new(TCG_TYPE_I32, TCG_AREG1, "T0"); |
90 | b26eefb6 | pbrook | cpu_T[1] = tcg_global_reg_new(TCG_TYPE_I32, TCG_AREG2, "T1"); |
91 | b26eefb6 | pbrook | } |
92 | b26eefb6 | pbrook | |
93 | b26eefb6 | pbrook | /* The code generator doesn't like lots of temporaries, so maintain our own
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94 | b26eefb6 | pbrook | cache for reuse within a function. */
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95 | b26eefb6 | pbrook | #define MAX_TEMPS 8 |
96 | b26eefb6 | pbrook | static int num_temps; |
97 | b26eefb6 | pbrook | static TCGv temps[MAX_TEMPS];
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98 | b26eefb6 | pbrook | |
99 | b26eefb6 | pbrook | /* Allocate a temporary variable. */
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100 | b26eefb6 | pbrook | static TCGv new_tmp(void) |
101 | b26eefb6 | pbrook | { |
102 | b26eefb6 | pbrook | TCGv tmp; |
103 | b26eefb6 | pbrook | if (num_temps == MAX_TEMPS)
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104 | b26eefb6 | pbrook | abort(); |
105 | b26eefb6 | pbrook | |
106 | b26eefb6 | pbrook | if (GET_TCGV(temps[num_temps]))
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107 | b26eefb6 | pbrook | return temps[num_temps++];
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108 | b26eefb6 | pbrook | |
109 | b26eefb6 | pbrook | tmp = tcg_temp_new(TCG_TYPE_I32); |
110 | b26eefb6 | pbrook | temps[num_temps++] = tmp; |
111 | b26eefb6 | pbrook | return tmp;
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112 | b26eefb6 | pbrook | } |
113 | b26eefb6 | pbrook | |
114 | b26eefb6 | pbrook | /* Release a temporary variable. */
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115 | b26eefb6 | pbrook | static void dead_tmp(TCGv tmp) |
116 | b26eefb6 | pbrook | { |
117 | b26eefb6 | pbrook | int i;
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118 | b26eefb6 | pbrook | num_temps--; |
119 | b26eefb6 | pbrook | i = num_temps; |
120 | b26eefb6 | pbrook | if (GET_TCGV(temps[i]) == GET_TCGV(tmp))
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121 | b26eefb6 | pbrook | return;
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122 | b26eefb6 | pbrook | |
123 | b26eefb6 | pbrook | /* Shuffle this temp to the last slot. */
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124 | b26eefb6 | pbrook | while (GET_TCGV(temps[i]) != GET_TCGV(tmp))
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125 | b26eefb6 | pbrook | i--; |
126 | b26eefb6 | pbrook | while (i < num_temps) {
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127 | b26eefb6 | pbrook | temps[i] = temps[i + 1];
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128 | b26eefb6 | pbrook | i++; |
129 | b26eefb6 | pbrook | } |
130 | b26eefb6 | pbrook | temps[i] = tmp; |
131 | b26eefb6 | pbrook | } |
132 | b26eefb6 | pbrook | |
133 | d9ba4830 | pbrook | static inline TCGv load_cpu_offset(int offset) |
134 | d9ba4830 | pbrook | { |
135 | d9ba4830 | pbrook | TCGv tmp = new_tmp(); |
136 | d9ba4830 | pbrook | tcg_gen_ld_i32(tmp, cpu_env, offset); |
137 | d9ba4830 | pbrook | return tmp;
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138 | d9ba4830 | pbrook | } |
139 | d9ba4830 | pbrook | |
140 | d9ba4830 | pbrook | #define load_cpu_field(name) load_cpu_offset(offsetof(CPUState, name))
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141 | d9ba4830 | pbrook | |
142 | d9ba4830 | pbrook | static inline void store_cpu_offset(TCGv var, int offset) |
143 | d9ba4830 | pbrook | { |
144 | d9ba4830 | pbrook | tcg_gen_st_i32(var, cpu_env, offset); |
145 | d9ba4830 | pbrook | dead_tmp(var); |
146 | d9ba4830 | pbrook | } |
147 | d9ba4830 | pbrook | |
148 | d9ba4830 | pbrook | #define store_cpu_field(var, name) \
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149 | d9ba4830 | pbrook | store_cpu_offset(var, offsetof(CPUState, name)) |
150 | d9ba4830 | pbrook | |
151 | b26eefb6 | pbrook | /* Set a variable to the value of a CPU register. */
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152 | b26eefb6 | pbrook | static void load_reg_var(DisasContext *s, TCGv var, int reg) |
153 | b26eefb6 | pbrook | { |
154 | b26eefb6 | pbrook | if (reg == 15) { |
155 | b26eefb6 | pbrook | uint32_t addr; |
156 | b26eefb6 | pbrook | /* normaly, since we updated PC, we need only to add one insn */
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157 | b26eefb6 | pbrook | if (s->thumb)
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158 | b26eefb6 | pbrook | addr = (long)s->pc + 2; |
159 | b26eefb6 | pbrook | else
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160 | b26eefb6 | pbrook | addr = (long)s->pc + 4; |
161 | b26eefb6 | pbrook | tcg_gen_movi_i32(var, addr); |
162 | b26eefb6 | pbrook | } else {
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163 | b26eefb6 | pbrook | tcg_gen_ld_i32(var, cpu_env, offsetof(CPUState, regs[reg])); |
164 | b26eefb6 | pbrook | } |
165 | b26eefb6 | pbrook | } |
166 | b26eefb6 | pbrook | |
167 | b26eefb6 | pbrook | /* Create a new temporary and set it to the value of a CPU register. */
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168 | b26eefb6 | pbrook | static inline TCGv load_reg(DisasContext *s, int reg) |
169 | b26eefb6 | pbrook | { |
170 | b26eefb6 | pbrook | TCGv tmp = new_tmp(); |
171 | b26eefb6 | pbrook | load_reg_var(s, tmp, reg); |
172 | b26eefb6 | pbrook | return tmp;
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173 | b26eefb6 | pbrook | } |
174 | b26eefb6 | pbrook | |
175 | b26eefb6 | pbrook | /* Set a CPU register. The source must be a temporary and will be
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176 | b26eefb6 | pbrook | marked as dead. */
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177 | b26eefb6 | pbrook | static void store_reg(DisasContext *s, int reg, TCGv var) |
178 | b26eefb6 | pbrook | { |
179 | b26eefb6 | pbrook | if (reg == 15) { |
180 | b26eefb6 | pbrook | tcg_gen_andi_i32(var, var, ~1);
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181 | b26eefb6 | pbrook | s->is_jmp = DISAS_JUMP; |
182 | b26eefb6 | pbrook | } |
183 | b26eefb6 | pbrook | tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, regs[reg])); |
184 | b26eefb6 | pbrook | dead_tmp(var); |
185 | b26eefb6 | pbrook | } |
186 | b26eefb6 | pbrook | |
187 | b26eefb6 | pbrook | |
188 | b26eefb6 | pbrook | /* Basic operations. */
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189 | b26eefb6 | pbrook | #define gen_op_movl_T0_T1() tcg_gen_mov_i32(cpu_T[0], cpu_T[1]) |
190 | b26eefb6 | pbrook | #define gen_op_movl_T1_T0() tcg_gen_mov_i32(cpu_T[1], cpu_T[0]) |
191 | b26eefb6 | pbrook | #define gen_op_movl_T0_im(im) tcg_gen_movi_i32(cpu_T[0], im) |
192 | b26eefb6 | pbrook | #define gen_op_movl_T1_im(im) tcg_gen_movi_i32(cpu_T[1], im) |
193 | b26eefb6 | pbrook | |
194 | b26eefb6 | pbrook | #define gen_op_addl_T1_im(im) tcg_gen_addi_i32(cpu_T[1], cpu_T[1], im) |
195 | b26eefb6 | pbrook | #define gen_op_addl_T0_T1() tcg_gen_add_i32(cpu_T[0], cpu_T[0], cpu_T[1]) |
196 | b26eefb6 | pbrook | #define gen_op_subl_T0_T1() tcg_gen_sub_i32(cpu_T[0], cpu_T[0], cpu_T[1]) |
197 | b26eefb6 | pbrook | #define gen_op_rsbl_T0_T1() tcg_gen_sub_i32(cpu_T[0], cpu_T[1], cpu_T[0]) |
198 | b26eefb6 | pbrook | |
199 | 8984bd2e | pbrook | #define gen_op_addl_T0_T1_cc() gen_helper_add_cc(cpu_T[0], cpu_T[0], cpu_T[1]) |
200 | 8984bd2e | pbrook | #define gen_op_adcl_T0_T1_cc() gen_helper_adc_cc(cpu_T[0], cpu_T[0], cpu_T[1]) |
201 | 8984bd2e | pbrook | #define gen_op_subl_T0_T1_cc() gen_helper_sub_cc(cpu_T[0], cpu_T[0], cpu_T[1]) |
202 | 8984bd2e | pbrook | #define gen_op_sbcl_T0_T1_cc() gen_helper_sbc_cc(cpu_T[0], cpu_T[0], cpu_T[1]) |
203 | 8984bd2e | pbrook | #define gen_op_rsbl_T0_T1_cc() gen_helper_sub_cc(cpu_T[0], cpu_T[1], cpu_T[0]) |
204 | 8984bd2e | pbrook | #define gen_op_rscl_T0_T1_cc() gen_helper_sbc_cc(cpu_T[0], cpu_T[1], cpu_T[0]) |
205 | 8984bd2e | pbrook | |
206 | b26eefb6 | pbrook | #define gen_op_andl_T0_T1() tcg_gen_and_i32(cpu_T[0], cpu_T[0], cpu_T[1]) |
207 | b26eefb6 | pbrook | #define gen_op_xorl_T0_T1() tcg_gen_xor_i32(cpu_T[0], cpu_T[0], cpu_T[1]) |
208 | b26eefb6 | pbrook | #define gen_op_orl_T0_T1() tcg_gen_or_i32(cpu_T[0], cpu_T[0], cpu_T[1]) |
209 | b26eefb6 | pbrook | #define gen_op_notl_T0() tcg_gen_not_i32(cpu_T[0], cpu_T[0]) |
210 | b26eefb6 | pbrook | #define gen_op_notl_T1() tcg_gen_not_i32(cpu_T[1], cpu_T[1]) |
211 | b26eefb6 | pbrook | #define gen_op_logic_T0_cc() gen_logic_CC(cpu_T[0]); |
212 | b26eefb6 | pbrook | #define gen_op_logic_T1_cc() gen_logic_CC(cpu_T[1]); |
213 | b26eefb6 | pbrook | |
214 | b26eefb6 | pbrook | #define gen_op_shll_T0_im(im) tcg_gen_shli_i32(cpu_T[0], cpu_T[0], im) |
215 | b26eefb6 | pbrook | #define gen_op_shll_T1_im(im) tcg_gen_shli_i32(cpu_T[1], cpu_T[1], im) |
216 | b26eefb6 | pbrook | #define gen_op_shrl_T1_im(im) tcg_gen_shri_i32(cpu_T[1], cpu_T[1], im) |
217 | b26eefb6 | pbrook | #define gen_op_sarl_T1_im(im) tcg_gen_sari_i32(cpu_T[1], cpu_T[1], im) |
218 | b26eefb6 | pbrook | #define gen_op_rorl_T1_im(im) tcg_gen_rori_i32(cpu_T[1], cpu_T[1], im) |
219 | b26eefb6 | pbrook | |
220 | b26eefb6 | pbrook | /* Value extensions. */
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221 | b26eefb6 | pbrook | #define gen_uxtb(var) tcg_gen_andi_i32(var, var, 0xff) |
222 | b26eefb6 | pbrook | #define gen_uxth(var) tcg_gen_andi_i32(var, var, 0xffff) |
223 | b26eefb6 | pbrook | #define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
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224 | b26eefb6 | pbrook | #define gen_sxth(var) tcg_gen_ext16s_i32(var, var)
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225 | b26eefb6 | pbrook | |
226 | 1497c961 | pbrook | #define gen_sxtb16(var) gen_helper_sxtb16(var, var)
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227 | 1497c961 | pbrook | #define gen_uxtb16(var) gen_helper_uxtb16(var, var)
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228 | 8f01245e | pbrook | |
229 | 8f01245e | pbrook | #define gen_op_mul_T0_T1() tcg_gen_mul_i32(cpu_T[0], cpu_T[0], cpu_T[1]) |
230 | b26eefb6 | pbrook | |
231 | d9ba4830 | pbrook | #define gen_set_cpsr(var, mask) gen_helper_cpsr_write(var, tcg_const_i32(mask))
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232 | d9ba4830 | pbrook | /* Set NZCV flags from the high 4 bits of var. */
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233 | d9ba4830 | pbrook | #define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
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234 | d9ba4830 | pbrook | |
235 | d9ba4830 | pbrook | static void gen_exception(int excp) |
236 | d9ba4830 | pbrook | { |
237 | d9ba4830 | pbrook | TCGv tmp = new_tmp(); |
238 | d9ba4830 | pbrook | tcg_gen_movi_i32(tmp, excp); |
239 | d9ba4830 | pbrook | gen_helper_exception(tmp); |
240 | d9ba4830 | pbrook | dead_tmp(tmp); |
241 | d9ba4830 | pbrook | } |
242 | d9ba4830 | pbrook | |
243 | 3670669c | pbrook | static void gen_smul_dual(TCGv a, TCGv b) |
244 | 3670669c | pbrook | { |
245 | 3670669c | pbrook | TCGv tmp1 = new_tmp(); |
246 | 3670669c | pbrook | TCGv tmp2 = new_tmp(); |
247 | 3670669c | pbrook | tcg_gen_ext8s_i32(tmp1, a); |
248 | 3670669c | pbrook | tcg_gen_ext8s_i32(tmp2, b); |
249 | 3670669c | pbrook | tcg_gen_mul_i32(tmp1, tmp1, tmp2); |
250 | 3670669c | pbrook | dead_tmp(tmp2); |
251 | 3670669c | pbrook | tcg_gen_sari_i32(a, a, 16);
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252 | 3670669c | pbrook | tcg_gen_sari_i32(b, b, 16);
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253 | 3670669c | pbrook | tcg_gen_mul_i32(b, b, a); |
254 | 3670669c | pbrook | tcg_gen_mov_i32(a, tmp1); |
255 | 3670669c | pbrook | dead_tmp(tmp1); |
256 | 3670669c | pbrook | } |
257 | 3670669c | pbrook | |
258 | 3670669c | pbrook | /* Byteswap each halfword. */
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259 | 3670669c | pbrook | static void gen_rev16(TCGv var) |
260 | 3670669c | pbrook | { |
261 | 3670669c | pbrook | TCGv tmp = new_tmp(); |
262 | 3670669c | pbrook | tcg_gen_shri_i32(tmp, var, 8);
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263 | 3670669c | pbrook | tcg_gen_andi_i32(tmp, tmp, 0x00ff00ff);
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264 | 3670669c | pbrook | tcg_gen_shli_i32(var, var, 8);
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265 | 3670669c | pbrook | tcg_gen_andi_i32(var, var, 0xff00ff00);
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266 | 3670669c | pbrook | tcg_gen_or_i32(var, var, tmp); |
267 | 3670669c | pbrook | dead_tmp(tmp); |
268 | 3670669c | pbrook | } |
269 | 3670669c | pbrook | |
270 | 3670669c | pbrook | /* Byteswap low halfword and sign extend. */
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271 | 3670669c | pbrook | static void gen_revsh(TCGv var) |
272 | 3670669c | pbrook | { |
273 | 3670669c | pbrook | TCGv tmp = new_tmp(); |
274 | 3670669c | pbrook | tcg_gen_shri_i32(tmp, var, 8);
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275 | 3670669c | pbrook | tcg_gen_andi_i32(tmp, tmp, 0x00ff);
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276 | 3670669c | pbrook | tcg_gen_shli_i32(var, var, 8);
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277 | 3670669c | pbrook | tcg_gen_ext8s_i32(var, var); |
278 | 3670669c | pbrook | tcg_gen_or_i32(var, var, tmp); |
279 | 3670669c | pbrook | dead_tmp(tmp); |
280 | 3670669c | pbrook | } |
281 | 3670669c | pbrook | |
282 | 3670669c | pbrook | /* Unsigned bitfield extract. */
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283 | 3670669c | pbrook | static void gen_ubfx(TCGv var, int shift, uint32_t mask) |
284 | 3670669c | pbrook | { |
285 | 3670669c | pbrook | if (shift)
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286 | 3670669c | pbrook | tcg_gen_shri_i32(var, var, shift); |
287 | 3670669c | pbrook | tcg_gen_andi_i32(var, var, mask); |
288 | 3670669c | pbrook | } |
289 | 3670669c | pbrook | |
290 | 3670669c | pbrook | /* Signed bitfield extract. */
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291 | 3670669c | pbrook | static void gen_sbfx(TCGv var, int shift, int width) |
292 | 3670669c | pbrook | { |
293 | 3670669c | pbrook | uint32_t signbit; |
294 | 3670669c | pbrook | |
295 | 3670669c | pbrook | if (shift)
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296 | 3670669c | pbrook | tcg_gen_sari_i32(var, var, shift); |
297 | 3670669c | pbrook | if (shift + width < 32) { |
298 | 3670669c | pbrook | signbit = 1u << (width - 1); |
299 | 3670669c | pbrook | tcg_gen_andi_i32(var, var, (1u << width) - 1); |
300 | 3670669c | pbrook | tcg_gen_xori_i32(var, var, signbit); |
301 | 3670669c | pbrook | tcg_gen_subi_i32(var, var, signbit); |
302 | 3670669c | pbrook | } |
303 | 3670669c | pbrook | } |
304 | 3670669c | pbrook | |
305 | 3670669c | pbrook | /* Bitfield insertion. Insert val into base. Clobbers base and val. */
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306 | 3670669c | pbrook | static void gen_bfi(TCGv dest, TCGv base, TCGv val, int shift, uint32_t mask) |
307 | 3670669c | pbrook | { |
308 | 3670669c | pbrook | tcg_gen_andi_i32(val, val, mask); |
309 | 8f8e3aa4 | pbrook | tcg_gen_shli_i32(val, val, shift); |
310 | 8f8e3aa4 | pbrook | tcg_gen_andi_i32(base, base, ~(mask << shift)); |
311 | 3670669c | pbrook | tcg_gen_or_i32(dest, base, val); |
312 | 3670669c | pbrook | } |
313 | 3670669c | pbrook | |
314 | d9ba4830 | pbrook | /* Round the top 32 bits of a 64-bit value. */
|
315 | d9ba4830 | pbrook | static void gen_roundqd(TCGv a, TCGv b) |
316 | 3670669c | pbrook | { |
317 | d9ba4830 | pbrook | tcg_gen_shri_i32(a, a, 31);
|
318 | d9ba4830 | pbrook | tcg_gen_add_i32(a, a, b); |
319 | 3670669c | pbrook | } |
320 | 3670669c | pbrook | |
321 | 8f01245e | pbrook | /* FIXME: Most targets have native widening multiplication.
|
322 | 8f01245e | pbrook | It would be good to use that instead of a full wide multiply. */
|
323 | 5e3f878a | pbrook | /* 32x32->64 multiply. Marks inputs as dead. */
|
324 | 5e3f878a | pbrook | static TCGv gen_mulu_i64_i32(TCGv a, TCGv b)
|
325 | 5e3f878a | pbrook | { |
326 | 5e3f878a | pbrook | TCGv tmp1 = tcg_temp_new(TCG_TYPE_I64); |
327 | 5e3f878a | pbrook | TCGv tmp2 = tcg_temp_new(TCG_TYPE_I64); |
328 | 5e3f878a | pbrook | |
329 | 5e3f878a | pbrook | tcg_gen_extu_i32_i64(tmp1, a); |
330 | 5e3f878a | pbrook | dead_tmp(a); |
331 | 5e3f878a | pbrook | tcg_gen_extu_i32_i64(tmp2, b); |
332 | 5e3f878a | pbrook | dead_tmp(b); |
333 | 5e3f878a | pbrook | tcg_gen_mul_i64(tmp1, tmp1, tmp2); |
334 | 5e3f878a | pbrook | return tmp1;
|
335 | 5e3f878a | pbrook | } |
336 | 5e3f878a | pbrook | |
337 | 5e3f878a | pbrook | static TCGv gen_muls_i64_i32(TCGv a, TCGv b)
|
338 | 5e3f878a | pbrook | { |
339 | 5e3f878a | pbrook | TCGv tmp1 = tcg_temp_new(TCG_TYPE_I64); |
340 | 5e3f878a | pbrook | TCGv tmp2 = tcg_temp_new(TCG_TYPE_I64); |
341 | 5e3f878a | pbrook | |
342 | 5e3f878a | pbrook | tcg_gen_ext_i32_i64(tmp1, a); |
343 | 5e3f878a | pbrook | dead_tmp(a); |
344 | 5e3f878a | pbrook | tcg_gen_ext_i32_i64(tmp2, b); |
345 | 5e3f878a | pbrook | dead_tmp(b); |
346 | 5e3f878a | pbrook | tcg_gen_mul_i64(tmp1, tmp1, tmp2); |
347 | 5e3f878a | pbrook | return tmp1;
|
348 | 5e3f878a | pbrook | } |
349 | 5e3f878a | pbrook | |
350 | 8f01245e | pbrook | /* Unsigned 32x32->64 multiply. */
|
351 | 8f01245e | pbrook | static void gen_op_mull_T0_T1(void) |
352 | 8f01245e | pbrook | { |
353 | 8f01245e | pbrook | TCGv tmp1 = tcg_temp_new(TCG_TYPE_I64); |
354 | 8f01245e | pbrook | TCGv tmp2 = tcg_temp_new(TCG_TYPE_I64); |
355 | 8f01245e | pbrook | |
356 | 8f01245e | pbrook | tcg_gen_extu_i32_i64(tmp1, cpu_T[0]);
|
357 | 8f01245e | pbrook | tcg_gen_extu_i32_i64(tmp2, cpu_T[1]);
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358 | 8f01245e | pbrook | tcg_gen_mul_i64(tmp1, tmp1, tmp2); |
359 | 8f01245e | pbrook | tcg_gen_trunc_i64_i32(cpu_T[0], tmp1);
|
360 | 8f01245e | pbrook | tcg_gen_shri_i64(tmp1, tmp1, 32);
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361 | 8f01245e | pbrook | tcg_gen_trunc_i64_i32(cpu_T[1], tmp1);
|
362 | 8f01245e | pbrook | } |
363 | 8f01245e | pbrook | |
364 | 8f01245e | pbrook | /* Signed 32x32->64 multiply. */
|
365 | d9ba4830 | pbrook | static void gen_imull(TCGv a, TCGv b) |
366 | 8f01245e | pbrook | { |
367 | 8f01245e | pbrook | TCGv tmp1 = tcg_temp_new(TCG_TYPE_I64); |
368 | 8f01245e | pbrook | TCGv tmp2 = tcg_temp_new(TCG_TYPE_I64); |
369 | 8f01245e | pbrook | |
370 | d9ba4830 | pbrook | tcg_gen_ext_i32_i64(tmp1, a); |
371 | d9ba4830 | pbrook | tcg_gen_ext_i32_i64(tmp2, b); |
372 | 8f01245e | pbrook | tcg_gen_mul_i64(tmp1, tmp1, tmp2); |
373 | d9ba4830 | pbrook | tcg_gen_trunc_i64_i32(a, tmp1); |
374 | 8f01245e | pbrook | tcg_gen_shri_i64(tmp1, tmp1, 32);
|
375 | d9ba4830 | pbrook | tcg_gen_trunc_i64_i32(b, tmp1); |
376 | d9ba4830 | pbrook | } |
377 | d9ba4830 | pbrook | #define gen_op_imull_T0_T1() gen_imull(cpu_T[0], cpu_T[1]) |
378 | d9ba4830 | pbrook | |
379 | 8f01245e | pbrook | /* Swap low and high halfwords. */
|
380 | 8f01245e | pbrook | static void gen_swap_half(TCGv var) |
381 | 8f01245e | pbrook | { |
382 | 8f01245e | pbrook | TCGv tmp = new_tmp(); |
383 | 8f01245e | pbrook | tcg_gen_shri_i32(tmp, var, 16);
|
384 | 8f01245e | pbrook | tcg_gen_shli_i32(var, var, 16);
|
385 | 8f01245e | pbrook | tcg_gen_or_i32(var, var, tmp); |
386 | 3670669c | pbrook | dead_tmp(tmp); |
387 | 8f01245e | pbrook | } |
388 | 8f01245e | pbrook | |
389 | b26eefb6 | pbrook | /* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
|
390 | b26eefb6 | pbrook | tmp = (t0 ^ t1) & 0x8000;
|
391 | b26eefb6 | pbrook | t0 &= ~0x8000;
|
392 | b26eefb6 | pbrook | t1 &= ~0x8000;
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393 | b26eefb6 | pbrook | t0 = (t0 + t1) ^ tmp;
|
394 | b26eefb6 | pbrook | */
|
395 | b26eefb6 | pbrook | |
396 | b26eefb6 | pbrook | static void gen_add16(TCGv t0, TCGv t1) |
397 | b26eefb6 | pbrook | { |
398 | b26eefb6 | pbrook | TCGv tmp = new_tmp(); |
399 | b26eefb6 | pbrook | tcg_gen_xor_i32(tmp, t0, t1); |
400 | b26eefb6 | pbrook | tcg_gen_andi_i32(tmp, tmp, 0x8000);
|
401 | b26eefb6 | pbrook | tcg_gen_andi_i32(t0, t0, ~0x8000);
|
402 | b26eefb6 | pbrook | tcg_gen_andi_i32(t1, t1, ~0x8000);
|
403 | b26eefb6 | pbrook | tcg_gen_add_i32(t0, t0, t1); |
404 | b26eefb6 | pbrook | tcg_gen_xor_i32(t0, t0, tmp); |
405 | b26eefb6 | pbrook | dead_tmp(tmp); |
406 | b26eefb6 | pbrook | dead_tmp(t1); |
407 | b26eefb6 | pbrook | } |
408 | b26eefb6 | pbrook | |
409 | 9a119ff6 | pbrook | #define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF))
|
410 | 9a119ff6 | pbrook | |
411 | b26eefb6 | pbrook | /* Set CF to the top bit of var. */
|
412 | b26eefb6 | pbrook | static void gen_set_CF_bit31(TCGv var) |
413 | b26eefb6 | pbrook | { |
414 | b26eefb6 | pbrook | TCGv tmp = new_tmp(); |
415 | b26eefb6 | pbrook | tcg_gen_shri_i32(tmp, var, 31);
|
416 | 9a119ff6 | pbrook | gen_set_CF(var); |
417 | b26eefb6 | pbrook | dead_tmp(tmp); |
418 | b26eefb6 | pbrook | } |
419 | b26eefb6 | pbrook | |
420 | b26eefb6 | pbrook | /* Set N and Z flags from var. */
|
421 | b26eefb6 | pbrook | static inline void gen_logic_CC(TCGv var) |
422 | b26eefb6 | pbrook | { |
423 | b26eefb6 | pbrook | tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, NZF)); |
424 | b26eefb6 | pbrook | } |
425 | b26eefb6 | pbrook | |
426 | b26eefb6 | pbrook | /* T0 += T1 + CF. */
|
427 | b26eefb6 | pbrook | static void gen_adc_T0_T1(void) |
428 | b26eefb6 | pbrook | { |
429 | d9ba4830 | pbrook | TCGv tmp; |
430 | b26eefb6 | pbrook | gen_op_addl_T0_T1(); |
431 | d9ba4830 | pbrook | tmp = load_cpu_field(CF); |
432 | b26eefb6 | pbrook | tcg_gen_add_i32(cpu_T[0], cpu_T[0], tmp); |
433 | b26eefb6 | pbrook | dead_tmp(tmp); |
434 | b26eefb6 | pbrook | } |
435 | b26eefb6 | pbrook | |
436 | 3670669c | pbrook | /* dest = T0 - T1 + CF - 1. */
|
437 | 3670669c | pbrook | static void gen_sub_carry(TCGv dest, TCGv t0, TCGv t1) |
438 | 3670669c | pbrook | { |
439 | d9ba4830 | pbrook | TCGv tmp; |
440 | 3670669c | pbrook | tcg_gen_sub_i32(dest, t0, t1); |
441 | d9ba4830 | pbrook | tmp = load_cpu_field(CF); |
442 | 3670669c | pbrook | tcg_gen_add_i32(dest, dest, tmp); |
443 | 3670669c | pbrook | tcg_gen_subi_i32(dest, dest, 1);
|
444 | 3670669c | pbrook | dead_tmp(tmp); |
445 | 3670669c | pbrook | } |
446 | 3670669c | pbrook | |
447 | 3670669c | pbrook | #define gen_sbc_T0_T1() gen_sub_carry(cpu_T[0], cpu_T[0], cpu_T[1]) |
448 | 3670669c | pbrook | #define gen_rsc_T0_T1() gen_sub_carry(cpu_T[0], cpu_T[1], cpu_T[0]) |
449 | 3670669c | pbrook | |
450 | b26eefb6 | pbrook | /* FIXME: Implement this natively. */
|
451 | b26eefb6 | pbrook | static inline void tcg_gen_not_i32(TCGv t0, TCGv t1) |
452 | b26eefb6 | pbrook | { |
453 | b26eefb6 | pbrook | tcg_gen_xori_i32(t0, t1, ~0);
|
454 | b26eefb6 | pbrook | } |
455 | b26eefb6 | pbrook | |
456 | b26eefb6 | pbrook | /* T0 &= ~T1. Clobbers T1. */
|
457 | b26eefb6 | pbrook | /* FIXME: Implement bic natively. */
|
458 | 8f8e3aa4 | pbrook | static inline void tcg_gen_bic_i32(TCGv dest, TCGv t0, TCGv t1) |
459 | 8f8e3aa4 | pbrook | { |
460 | 8f8e3aa4 | pbrook | TCGv tmp = new_tmp(); |
461 | 8f8e3aa4 | pbrook | tcg_gen_not_i32(tmp, t1); |
462 | 8f8e3aa4 | pbrook | tcg_gen_and_i32(dest, t0, tmp); |
463 | 8f8e3aa4 | pbrook | dead_tmp(tmp); |
464 | 8f8e3aa4 | pbrook | } |
465 | b26eefb6 | pbrook | static inline void gen_op_bicl_T0_T1(void) |
466 | b26eefb6 | pbrook | { |
467 | b26eefb6 | pbrook | gen_op_notl_T1(); |
468 | b26eefb6 | pbrook | gen_op_andl_T0_T1(); |
469 | b26eefb6 | pbrook | } |
470 | b26eefb6 | pbrook | |
471 | b26eefb6 | pbrook | /* FIXME: Implement this natively. */
|
472 | b26eefb6 | pbrook | static void tcg_gen_rori_i32(TCGv t0, TCGv t1, int i) |
473 | b26eefb6 | pbrook | { |
474 | b26eefb6 | pbrook | TCGv tmp; |
475 | b26eefb6 | pbrook | |
476 | b26eefb6 | pbrook | if (i == 0) |
477 | b26eefb6 | pbrook | return;
|
478 | b26eefb6 | pbrook | |
479 | b26eefb6 | pbrook | tmp = new_tmp(); |
480 | b26eefb6 | pbrook | tcg_gen_shri_i32(tmp, t1, i); |
481 | b26eefb6 | pbrook | tcg_gen_shli_i32(t1, t1, 32 - i);
|
482 | b26eefb6 | pbrook | tcg_gen_or_i32(t0, t1, tmp); |
483 | b26eefb6 | pbrook | dead_tmp(tmp); |
484 | b26eefb6 | pbrook | } |
485 | b26eefb6 | pbrook | |
486 | 9a119ff6 | pbrook | static void shifter_out_im(TCGv var, int shift) |
487 | b26eefb6 | pbrook | { |
488 | 9a119ff6 | pbrook | TCGv tmp = new_tmp(); |
489 | 9a119ff6 | pbrook | if (shift == 0) { |
490 | 9a119ff6 | pbrook | tcg_gen_andi_i32(tmp, var, 1);
|
491 | b26eefb6 | pbrook | } else {
|
492 | 9a119ff6 | pbrook | tcg_gen_shri_i32(tmp, var, shift); |
493 | 9a119ff6 | pbrook | if (shift != 31); |
494 | 9a119ff6 | pbrook | tcg_gen_andi_i32(tmp, tmp, 1);
|
495 | 9a119ff6 | pbrook | } |
496 | 9a119ff6 | pbrook | gen_set_CF(tmp); |
497 | 9a119ff6 | pbrook | dead_tmp(tmp); |
498 | 9a119ff6 | pbrook | } |
499 | b26eefb6 | pbrook | |
500 | 9a119ff6 | pbrook | /* Shift by immediate. Includes special handling for shift == 0. */
|
501 | 9a119ff6 | pbrook | static inline void gen_arm_shift_im(TCGv var, int shiftop, int shift, int flags) |
502 | 9a119ff6 | pbrook | { |
503 | 9a119ff6 | pbrook | switch (shiftop) {
|
504 | 9a119ff6 | pbrook | case 0: /* LSL */ |
505 | 9a119ff6 | pbrook | if (shift != 0) { |
506 | 9a119ff6 | pbrook | if (flags)
|
507 | 9a119ff6 | pbrook | shifter_out_im(var, 32 - shift);
|
508 | 9a119ff6 | pbrook | tcg_gen_shli_i32(var, var, shift); |
509 | 9a119ff6 | pbrook | } |
510 | 9a119ff6 | pbrook | break;
|
511 | 9a119ff6 | pbrook | case 1: /* LSR */ |
512 | 9a119ff6 | pbrook | if (shift == 0) { |
513 | 9a119ff6 | pbrook | if (flags) {
|
514 | 9a119ff6 | pbrook | tcg_gen_shri_i32(var, var, 31);
|
515 | 9a119ff6 | pbrook | gen_set_CF(var); |
516 | 9a119ff6 | pbrook | } |
517 | 9a119ff6 | pbrook | tcg_gen_movi_i32(var, 0);
|
518 | 9a119ff6 | pbrook | } else {
|
519 | 9a119ff6 | pbrook | if (flags)
|
520 | 9a119ff6 | pbrook | shifter_out_im(var, shift - 1);
|
521 | 9a119ff6 | pbrook | tcg_gen_shri_i32(var, var, shift); |
522 | 9a119ff6 | pbrook | } |
523 | 9a119ff6 | pbrook | break;
|
524 | 9a119ff6 | pbrook | case 2: /* ASR */ |
525 | 9a119ff6 | pbrook | if (shift == 0) |
526 | 9a119ff6 | pbrook | shift = 32;
|
527 | 9a119ff6 | pbrook | if (flags)
|
528 | 9a119ff6 | pbrook | shifter_out_im(var, shift - 1);
|
529 | 9a119ff6 | pbrook | if (shift == 32) |
530 | 9a119ff6 | pbrook | shift = 31;
|
531 | 9a119ff6 | pbrook | tcg_gen_sari_i32(var, var, shift); |
532 | 9a119ff6 | pbrook | break;
|
533 | 9a119ff6 | pbrook | case 3: /* ROR/RRX */ |
534 | 9a119ff6 | pbrook | if (shift != 0) { |
535 | 9a119ff6 | pbrook | if (flags)
|
536 | 9a119ff6 | pbrook | shifter_out_im(var, shift - 1);
|
537 | 9a119ff6 | pbrook | tcg_gen_rori_i32(var, var, shift); break;
|
538 | 9a119ff6 | pbrook | } else {
|
539 | d9ba4830 | pbrook | TCGv tmp = load_cpu_field(CF); |
540 | 9a119ff6 | pbrook | if (flags)
|
541 | 9a119ff6 | pbrook | shifter_out_im(var, 0);
|
542 | 9a119ff6 | pbrook | tcg_gen_shri_i32(var, var, 1);
|
543 | b26eefb6 | pbrook | tcg_gen_shli_i32(tmp, tmp, 31);
|
544 | b26eefb6 | pbrook | tcg_gen_or_i32(var, var, tmp); |
545 | b26eefb6 | pbrook | dead_tmp(tmp); |
546 | b26eefb6 | pbrook | } |
547 | b26eefb6 | pbrook | } |
548 | b26eefb6 | pbrook | }; |
549 | b26eefb6 | pbrook | |
550 | 8984bd2e | pbrook | static inline void gen_arm_shift_reg(TCGv var, int shiftop, |
551 | 8984bd2e | pbrook | TCGv shift, int flags)
|
552 | 8984bd2e | pbrook | { |
553 | 8984bd2e | pbrook | if (flags) {
|
554 | 8984bd2e | pbrook | switch (shiftop) {
|
555 | 8984bd2e | pbrook | case 0: gen_helper_shl_cc(var, var, shift); break; |
556 | 8984bd2e | pbrook | case 1: gen_helper_shr_cc(var, var, shift); break; |
557 | 8984bd2e | pbrook | case 2: gen_helper_sar_cc(var, var, shift); break; |
558 | 8984bd2e | pbrook | case 3: gen_helper_ror_cc(var, var, shift); break; |
559 | 8984bd2e | pbrook | } |
560 | 8984bd2e | pbrook | } else {
|
561 | 8984bd2e | pbrook | switch (shiftop) {
|
562 | 8984bd2e | pbrook | case 0: gen_helper_shl(var, var, shift); break; |
563 | 8984bd2e | pbrook | case 1: gen_helper_shr(var, var, shift); break; |
564 | 8984bd2e | pbrook | case 2: gen_helper_sar(var, var, shift); break; |
565 | 8984bd2e | pbrook | case 3: gen_helper_ror(var, var, shift); break; |
566 | 8984bd2e | pbrook | } |
567 | 8984bd2e | pbrook | } |
568 | 8984bd2e | pbrook | dead_tmp(shift); |
569 | 8984bd2e | pbrook | } |
570 | 8984bd2e | pbrook | |
571 | 6ddbc6e4 | pbrook | #define PAS_OP(pfx) \
|
572 | 6ddbc6e4 | pbrook | switch (op2) { \
|
573 | 6ddbc6e4 | pbrook | case 0: gen_pas_helper(glue(pfx,add16)); break; \ |
574 | 6ddbc6e4 | pbrook | case 1: gen_pas_helper(glue(pfx,addsubx)); break; \ |
575 | 6ddbc6e4 | pbrook | case 2: gen_pas_helper(glue(pfx,subaddx)); break; \ |
576 | 6ddbc6e4 | pbrook | case 3: gen_pas_helper(glue(pfx,sub16)); break; \ |
577 | 6ddbc6e4 | pbrook | case 4: gen_pas_helper(glue(pfx,add8)); break; \ |
578 | 6ddbc6e4 | pbrook | case 7: gen_pas_helper(glue(pfx,sub8)); break; \ |
579 | 6ddbc6e4 | pbrook | } |
580 | d9ba4830 | pbrook | static void gen_arm_parallel_addsub(int op1, int op2, TCGv a, TCGv b) |
581 | 6ddbc6e4 | pbrook | { |
582 | 6ddbc6e4 | pbrook | TCGv tmp; |
583 | 6ddbc6e4 | pbrook | |
584 | 6ddbc6e4 | pbrook | switch (op1) {
|
585 | 6ddbc6e4 | pbrook | #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
|
586 | 6ddbc6e4 | pbrook | case 1: |
587 | 6ddbc6e4 | pbrook | tmp = tcg_temp_new(TCG_TYPE_PTR); |
588 | 6ddbc6e4 | pbrook | tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE)); |
589 | 6ddbc6e4 | pbrook | PAS_OP(s) |
590 | 6ddbc6e4 | pbrook | break;
|
591 | 6ddbc6e4 | pbrook | case 5: |
592 | 6ddbc6e4 | pbrook | tmp = tcg_temp_new(TCG_TYPE_PTR); |
593 | 6ddbc6e4 | pbrook | tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE)); |
594 | 6ddbc6e4 | pbrook | PAS_OP(u) |
595 | 6ddbc6e4 | pbrook | break;
|
596 | 6ddbc6e4 | pbrook | #undef gen_pas_helper
|
597 | 6ddbc6e4 | pbrook | #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
|
598 | 6ddbc6e4 | pbrook | case 2: |
599 | 6ddbc6e4 | pbrook | PAS_OP(q); |
600 | 6ddbc6e4 | pbrook | break;
|
601 | 6ddbc6e4 | pbrook | case 3: |
602 | 6ddbc6e4 | pbrook | PAS_OP(sh); |
603 | 6ddbc6e4 | pbrook | break;
|
604 | 6ddbc6e4 | pbrook | case 6: |
605 | 6ddbc6e4 | pbrook | PAS_OP(uq); |
606 | 6ddbc6e4 | pbrook | break;
|
607 | 6ddbc6e4 | pbrook | case 7: |
608 | 6ddbc6e4 | pbrook | PAS_OP(uh); |
609 | 6ddbc6e4 | pbrook | break;
|
610 | 6ddbc6e4 | pbrook | #undef gen_pas_helper
|
611 | 6ddbc6e4 | pbrook | } |
612 | 6ddbc6e4 | pbrook | } |
613 | 9ee6e8bb | pbrook | #undef PAS_OP
|
614 | 9ee6e8bb | pbrook | |
615 | 6ddbc6e4 | pbrook | /* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings. */
|
616 | 6ddbc6e4 | pbrook | #define PAS_OP(pfx) \
|
617 | 6ddbc6e4 | pbrook | switch (op2) { \
|
618 | 6ddbc6e4 | pbrook | case 0: gen_pas_helper(glue(pfx,add8)); break; \ |
619 | 6ddbc6e4 | pbrook | case 1: gen_pas_helper(glue(pfx,add16)); break; \ |
620 | 6ddbc6e4 | pbrook | case 2: gen_pas_helper(glue(pfx,addsubx)); break; \ |
621 | 6ddbc6e4 | pbrook | case 4: gen_pas_helper(glue(pfx,sub8)); break; \ |
622 | 6ddbc6e4 | pbrook | case 5: gen_pas_helper(glue(pfx,sub16)); break; \ |
623 | 6ddbc6e4 | pbrook | case 6: gen_pas_helper(glue(pfx,subaddx)); break; \ |
624 | 6ddbc6e4 | pbrook | } |
625 | d9ba4830 | pbrook | static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv a, TCGv b) |
626 | 6ddbc6e4 | pbrook | { |
627 | 6ddbc6e4 | pbrook | TCGv tmp; |
628 | 6ddbc6e4 | pbrook | |
629 | 6ddbc6e4 | pbrook | switch (op1) {
|
630 | 6ddbc6e4 | pbrook | #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
|
631 | 6ddbc6e4 | pbrook | case 0: |
632 | 6ddbc6e4 | pbrook | tmp = tcg_temp_new(TCG_TYPE_PTR); |
633 | 6ddbc6e4 | pbrook | tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE)); |
634 | 6ddbc6e4 | pbrook | PAS_OP(s) |
635 | 6ddbc6e4 | pbrook | break;
|
636 | 6ddbc6e4 | pbrook | case 4: |
637 | 6ddbc6e4 | pbrook | tmp = tcg_temp_new(TCG_TYPE_PTR); |
638 | 6ddbc6e4 | pbrook | tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE)); |
639 | 6ddbc6e4 | pbrook | PAS_OP(u) |
640 | 6ddbc6e4 | pbrook | break;
|
641 | 6ddbc6e4 | pbrook | #undef gen_pas_helper
|
642 | 6ddbc6e4 | pbrook | #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
|
643 | 6ddbc6e4 | pbrook | case 1: |
644 | 6ddbc6e4 | pbrook | PAS_OP(q); |
645 | 6ddbc6e4 | pbrook | break;
|
646 | 6ddbc6e4 | pbrook | case 2: |
647 | 6ddbc6e4 | pbrook | PAS_OP(sh); |
648 | 6ddbc6e4 | pbrook | break;
|
649 | 6ddbc6e4 | pbrook | case 5: |
650 | 6ddbc6e4 | pbrook | PAS_OP(uq); |
651 | 6ddbc6e4 | pbrook | break;
|
652 | 6ddbc6e4 | pbrook | case 6: |
653 | 6ddbc6e4 | pbrook | PAS_OP(uh); |
654 | 6ddbc6e4 | pbrook | break;
|
655 | 6ddbc6e4 | pbrook | #undef gen_pas_helper
|
656 | 6ddbc6e4 | pbrook | } |
657 | 6ddbc6e4 | pbrook | } |
658 | 9ee6e8bb | pbrook | #undef PAS_OP
|
659 | 9ee6e8bb | pbrook | |
660 | d9ba4830 | pbrook | static void gen_test_cc(int cc, int label) |
661 | d9ba4830 | pbrook | { |
662 | d9ba4830 | pbrook | TCGv tmp; |
663 | d9ba4830 | pbrook | TCGv tmp2; |
664 | d9ba4830 | pbrook | TCGv zero; |
665 | d9ba4830 | pbrook | int inv;
|
666 | d9ba4830 | pbrook | |
667 | d9ba4830 | pbrook | zero = tcg_const_i32(0);
|
668 | d9ba4830 | pbrook | switch (cc) {
|
669 | d9ba4830 | pbrook | case 0: /* eq: Z */ |
670 | d9ba4830 | pbrook | tmp = load_cpu_field(NZF); |
671 | d9ba4830 | pbrook | tcg_gen_brcond_i32(TCG_COND_EQ, tmp, zero, label); |
672 | d9ba4830 | pbrook | break;
|
673 | d9ba4830 | pbrook | case 1: /* ne: !Z */ |
674 | d9ba4830 | pbrook | tmp = load_cpu_field(NZF); |
675 | d9ba4830 | pbrook | tcg_gen_brcond_i32(TCG_COND_NE, tmp, zero, label); |
676 | d9ba4830 | pbrook | break;
|
677 | d9ba4830 | pbrook | case 2: /* cs: C */ |
678 | d9ba4830 | pbrook | tmp = load_cpu_field(CF); |
679 | d9ba4830 | pbrook | tcg_gen_brcond_i32(TCG_COND_NE, tmp, zero, label); |
680 | d9ba4830 | pbrook | break;
|
681 | d9ba4830 | pbrook | case 3: /* cc: !C */ |
682 | d9ba4830 | pbrook | tmp = load_cpu_field(CF); |
683 | d9ba4830 | pbrook | tcg_gen_brcond_i32(TCG_COND_EQ, tmp, zero, label); |
684 | d9ba4830 | pbrook | break;
|
685 | d9ba4830 | pbrook | case 4: /* mi: N */ |
686 | d9ba4830 | pbrook | tmp = load_cpu_field(NZF); |
687 | d9ba4830 | pbrook | tcg_gen_brcond_i32(TCG_COND_LT, tmp, zero, label); |
688 | d9ba4830 | pbrook | break;
|
689 | d9ba4830 | pbrook | case 5: /* pl: !N */ |
690 | d9ba4830 | pbrook | tmp = load_cpu_field(NZF); |
691 | d9ba4830 | pbrook | tcg_gen_brcond_i32(TCG_COND_GE, tmp, zero, label); |
692 | d9ba4830 | pbrook | break;
|
693 | d9ba4830 | pbrook | case 6: /* vs: V */ |
694 | d9ba4830 | pbrook | tmp = load_cpu_field(VF); |
695 | d9ba4830 | pbrook | tcg_gen_brcond_i32(TCG_COND_LT, tmp, zero, label); |
696 | d9ba4830 | pbrook | break;
|
697 | d9ba4830 | pbrook | case 7: /* vc: !V */ |
698 | d9ba4830 | pbrook | tmp = load_cpu_field(VF); |
699 | d9ba4830 | pbrook | tcg_gen_brcond_i32(TCG_COND_GE, tmp, zero, label); |
700 | d9ba4830 | pbrook | break;
|
701 | d9ba4830 | pbrook | case 8: /* hi: C && !Z */ |
702 | d9ba4830 | pbrook | inv = gen_new_label(); |
703 | d9ba4830 | pbrook | tmp = load_cpu_field(CF); |
704 | d9ba4830 | pbrook | tcg_gen_brcond_i32(TCG_COND_EQ, tmp, zero, inv); |
705 | d9ba4830 | pbrook | dead_tmp(tmp); |
706 | d9ba4830 | pbrook | tmp = load_cpu_field(NZF); |
707 | d9ba4830 | pbrook | tcg_gen_brcond_i32(TCG_COND_NE, tmp, zero, label); |
708 | d9ba4830 | pbrook | gen_set_label(inv); |
709 | d9ba4830 | pbrook | break;
|
710 | d9ba4830 | pbrook | case 9: /* ls: !C || Z */ |
711 | d9ba4830 | pbrook | tmp = load_cpu_field(CF); |
712 | d9ba4830 | pbrook | tcg_gen_brcond_i32(TCG_COND_EQ, tmp, zero, label); |
713 | d9ba4830 | pbrook | dead_tmp(tmp); |
714 | d9ba4830 | pbrook | tmp = load_cpu_field(NZF); |
715 | d9ba4830 | pbrook | tcg_gen_brcond_i32(TCG_COND_EQ, tmp, zero, label); |
716 | d9ba4830 | pbrook | break;
|
717 | d9ba4830 | pbrook | case 10: /* ge: N == V -> N ^ V == 0 */ |
718 | d9ba4830 | pbrook | tmp = load_cpu_field(VF); |
719 | d9ba4830 | pbrook | tmp2 = load_cpu_field(NZF); |
720 | d9ba4830 | pbrook | tcg_gen_xor_i32(tmp, tmp, tmp2); |
721 | d9ba4830 | pbrook | dead_tmp(tmp2); |
722 | d9ba4830 | pbrook | tcg_gen_brcond_i32(TCG_COND_GE, tmp, zero, label); |
723 | d9ba4830 | pbrook | break;
|
724 | d9ba4830 | pbrook | case 11: /* lt: N != V -> N ^ V != 0 */ |
725 | d9ba4830 | pbrook | tmp = load_cpu_field(VF); |
726 | d9ba4830 | pbrook | tmp2 = load_cpu_field(NZF); |
727 | d9ba4830 | pbrook | tcg_gen_xor_i32(tmp, tmp, tmp2); |
728 | d9ba4830 | pbrook | dead_tmp(tmp2); |
729 | d9ba4830 | pbrook | tcg_gen_brcond_i32(TCG_COND_LT, tmp, zero, label); |
730 | d9ba4830 | pbrook | break;
|
731 | d9ba4830 | pbrook | case 12: /* gt: !Z && N == V */ |
732 | d9ba4830 | pbrook | inv = gen_new_label(); |
733 | d9ba4830 | pbrook | tmp = load_cpu_field(NZF); |
734 | d9ba4830 | pbrook | tcg_gen_brcond_i32(TCG_COND_EQ, tmp, zero, inv); |
735 | d9ba4830 | pbrook | dead_tmp(tmp); |
736 | d9ba4830 | pbrook | tmp = load_cpu_field(VF); |
737 | d9ba4830 | pbrook | tmp2 = load_cpu_field(NZF); |
738 | d9ba4830 | pbrook | tcg_gen_xor_i32(tmp, tmp, tmp2); |
739 | d9ba4830 | pbrook | dead_tmp(tmp2); |
740 | d9ba4830 | pbrook | tcg_gen_brcond_i32(TCG_COND_GE, tmp, zero, label); |
741 | d9ba4830 | pbrook | gen_set_label(inv); |
742 | d9ba4830 | pbrook | break;
|
743 | d9ba4830 | pbrook | case 13: /* le: Z || N != V */ |
744 | d9ba4830 | pbrook | tmp = load_cpu_field(NZF); |
745 | d9ba4830 | pbrook | tcg_gen_brcond_i32(TCG_COND_EQ, tmp, zero, label); |
746 | d9ba4830 | pbrook | dead_tmp(tmp); |
747 | d9ba4830 | pbrook | tmp = load_cpu_field(VF); |
748 | d9ba4830 | pbrook | tmp2 = load_cpu_field(NZF); |
749 | d9ba4830 | pbrook | tcg_gen_xor_i32(tmp, tmp, tmp2); |
750 | d9ba4830 | pbrook | dead_tmp(tmp2); |
751 | d9ba4830 | pbrook | tcg_gen_brcond_i32(TCG_COND_LT, tmp, zero, label); |
752 | d9ba4830 | pbrook | break;
|
753 | d9ba4830 | pbrook | default:
|
754 | d9ba4830 | pbrook | fprintf(stderr, "Bad condition code 0x%x\n", cc);
|
755 | d9ba4830 | pbrook | abort(); |
756 | d9ba4830 | pbrook | } |
757 | d9ba4830 | pbrook | dead_tmp(tmp); |
758 | d9ba4830 | pbrook | } |
759 | 2c0262af | bellard | |
760 | 2c0262af | bellard | const uint8_t table_logic_cc[16] = { |
761 | 2c0262af | bellard | 1, /* and */ |
762 | 2c0262af | bellard | 1, /* xor */ |
763 | 2c0262af | bellard | 0, /* sub */ |
764 | 2c0262af | bellard | 0, /* rsb */ |
765 | 2c0262af | bellard | 0, /* add */ |
766 | 2c0262af | bellard | 0, /* adc */ |
767 | 2c0262af | bellard | 0, /* sbc */ |
768 | 2c0262af | bellard | 0, /* rsc */ |
769 | 2c0262af | bellard | 1, /* andl */ |
770 | 2c0262af | bellard | 1, /* xorl */ |
771 | 2c0262af | bellard | 0, /* cmp */ |
772 | 2c0262af | bellard | 0, /* cmn */ |
773 | 2c0262af | bellard | 1, /* orr */ |
774 | 2c0262af | bellard | 1, /* mov */ |
775 | 2c0262af | bellard | 1, /* bic */ |
776 | 2c0262af | bellard | 1, /* mvn */ |
777 | 2c0262af | bellard | }; |
778 | 3b46e624 | ths | |
779 | d9ba4830 | pbrook | /* Set PC and Thumb state from an immediate address. */
|
780 | d9ba4830 | pbrook | static inline void gen_bx_im(DisasContext *s, uint32_t addr) |
781 | 99c475ab | bellard | { |
782 | b26eefb6 | pbrook | TCGv tmp; |
783 | 99c475ab | bellard | |
784 | b26eefb6 | pbrook | s->is_jmp = DISAS_UPDATE; |
785 | b26eefb6 | pbrook | tmp = new_tmp(); |
786 | d9ba4830 | pbrook | if (s->thumb != (addr & 1)) { |
787 | d9ba4830 | pbrook | tcg_gen_movi_i32(tmp, addr & 1);
|
788 | d9ba4830 | pbrook | tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, thumb)); |
789 | d9ba4830 | pbrook | } |
790 | d9ba4830 | pbrook | tcg_gen_movi_i32(tmp, addr & ~1);
|
791 | d9ba4830 | pbrook | tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, regs[15]));
|
792 | b26eefb6 | pbrook | dead_tmp(tmp); |
793 | d9ba4830 | pbrook | } |
794 | d9ba4830 | pbrook | |
795 | d9ba4830 | pbrook | /* Set PC and Thumb state from var. var is marked as dead. */
|
796 | d9ba4830 | pbrook | static inline void gen_bx(DisasContext *s, TCGv var) |
797 | d9ba4830 | pbrook | { |
798 | d9ba4830 | pbrook | TCGv tmp; |
799 | d9ba4830 | pbrook | |
800 | d9ba4830 | pbrook | s->is_jmp = DISAS_UPDATE; |
801 | d9ba4830 | pbrook | tmp = new_tmp(); |
802 | d9ba4830 | pbrook | tcg_gen_andi_i32(tmp, var, 1);
|
803 | d9ba4830 | pbrook | store_cpu_field(tmp, thumb); |
804 | d9ba4830 | pbrook | tcg_gen_andi_i32(var, var, ~1);
|
805 | d9ba4830 | pbrook | store_cpu_field(var, regs[15]);
|
806 | d9ba4830 | pbrook | } |
807 | d9ba4830 | pbrook | |
808 | d9ba4830 | pbrook | /* TODO: This should be removed. Use gen_bx instead. */
|
809 | d9ba4830 | pbrook | static inline void gen_bx_T0(DisasContext *s) |
810 | d9ba4830 | pbrook | { |
811 | d9ba4830 | pbrook | TCGv tmp = new_tmp(); |
812 | d9ba4830 | pbrook | tcg_gen_mov_i32(tmp, cpu_T[0]);
|
813 | d9ba4830 | pbrook | gen_bx(s, tmp); |
814 | b26eefb6 | pbrook | } |
815 | b5ff1b31 | bellard | |
816 | b5ff1b31 | bellard | #if defined(CONFIG_USER_ONLY)
|
817 | b5ff1b31 | bellard | #define gen_ldst(name, s) gen_op_##name##_raw() |
818 | b5ff1b31 | bellard | #else
|
819 | b5ff1b31 | bellard | #define gen_ldst(name, s) do { \ |
820 | 6658ffb8 | pbrook | s->is_mem = 1; \
|
821 | b5ff1b31 | bellard | if (IS_USER(s)) \
|
822 | b5ff1b31 | bellard | gen_op_##name##_user(); \ |
823 | b5ff1b31 | bellard | else \
|
824 | b5ff1b31 | bellard | gen_op_##name##_kernel(); \ |
825 | b5ff1b31 | bellard | } while (0) |
826 | b5ff1b31 | bellard | #endif
|
827 | b0109805 | pbrook | static inline TCGv gen_ld8s(TCGv addr, int index) |
828 | b0109805 | pbrook | { |
829 | b0109805 | pbrook | TCGv tmp = new_tmp(); |
830 | b0109805 | pbrook | tcg_gen_qemu_ld8s(tmp, addr, index); |
831 | b0109805 | pbrook | return tmp;
|
832 | b0109805 | pbrook | } |
833 | b0109805 | pbrook | static inline TCGv gen_ld8u(TCGv addr, int index) |
834 | b0109805 | pbrook | { |
835 | b0109805 | pbrook | TCGv tmp = new_tmp(); |
836 | b0109805 | pbrook | tcg_gen_qemu_ld8u(tmp, addr, index); |
837 | b0109805 | pbrook | return tmp;
|
838 | b0109805 | pbrook | } |
839 | b0109805 | pbrook | static inline TCGv gen_ld16s(TCGv addr, int index) |
840 | b0109805 | pbrook | { |
841 | b0109805 | pbrook | TCGv tmp = new_tmp(); |
842 | b0109805 | pbrook | tcg_gen_qemu_ld16s(tmp, addr, index); |
843 | b0109805 | pbrook | return tmp;
|
844 | b0109805 | pbrook | } |
845 | b0109805 | pbrook | static inline TCGv gen_ld16u(TCGv addr, int index) |
846 | b0109805 | pbrook | { |
847 | b0109805 | pbrook | TCGv tmp = new_tmp(); |
848 | b0109805 | pbrook | tcg_gen_qemu_ld16u(tmp, addr, index); |
849 | b0109805 | pbrook | return tmp;
|
850 | b0109805 | pbrook | } |
851 | b0109805 | pbrook | static inline TCGv gen_ld32(TCGv addr, int index) |
852 | b0109805 | pbrook | { |
853 | b0109805 | pbrook | TCGv tmp = new_tmp(); |
854 | b0109805 | pbrook | tcg_gen_qemu_ld32u(tmp, addr, index); |
855 | b0109805 | pbrook | return tmp;
|
856 | b0109805 | pbrook | } |
857 | b0109805 | pbrook | static inline void gen_st8(TCGv val, TCGv addr, int index) |
858 | b0109805 | pbrook | { |
859 | b0109805 | pbrook | tcg_gen_qemu_st8(val, addr, index); |
860 | b0109805 | pbrook | dead_tmp(val); |
861 | b0109805 | pbrook | } |
862 | b0109805 | pbrook | static inline void gen_st16(TCGv val, TCGv addr, int index) |
863 | b0109805 | pbrook | { |
864 | b0109805 | pbrook | tcg_gen_qemu_st16(val, addr, index); |
865 | b0109805 | pbrook | dead_tmp(val); |
866 | b0109805 | pbrook | } |
867 | b0109805 | pbrook | static inline void gen_st32(TCGv val, TCGv addr, int index) |
868 | b0109805 | pbrook | { |
869 | b0109805 | pbrook | tcg_gen_qemu_st32(val, addr, index); |
870 | b0109805 | pbrook | dead_tmp(val); |
871 | b0109805 | pbrook | } |
872 | b5ff1b31 | bellard | |
873 | 2c0262af | bellard | static inline void gen_movl_T0_reg(DisasContext *s, int reg) |
874 | 2c0262af | bellard | { |
875 | b26eefb6 | pbrook | load_reg_var(s, cpu_T[0], reg);
|
876 | 2c0262af | bellard | } |
877 | 2c0262af | bellard | |
878 | 2c0262af | bellard | static inline void gen_movl_T1_reg(DisasContext *s, int reg) |
879 | 2c0262af | bellard | { |
880 | b26eefb6 | pbrook | load_reg_var(s, cpu_T[1], reg);
|
881 | 2c0262af | bellard | } |
882 | 2c0262af | bellard | |
883 | 2c0262af | bellard | static inline void gen_movl_T2_reg(DisasContext *s, int reg) |
884 | 2c0262af | bellard | { |
885 | b26eefb6 | pbrook | load_reg_var(s, cpu_T[2], reg);
|
886 | b26eefb6 | pbrook | } |
887 | b26eefb6 | pbrook | |
888 | 5e3f878a | pbrook | static inline void gen_set_pc_im(uint32_t val) |
889 | 5e3f878a | pbrook | { |
890 | 5e3f878a | pbrook | TCGv tmp = new_tmp(); |
891 | 5e3f878a | pbrook | tcg_gen_movi_i32(tmp, val); |
892 | 5e3f878a | pbrook | store_cpu_field(tmp, regs[15]);
|
893 | 5e3f878a | pbrook | } |
894 | 5e3f878a | pbrook | |
895 | b26eefb6 | pbrook | static inline void gen_set_pc_T0(void) |
896 | b26eefb6 | pbrook | { |
897 | b26eefb6 | pbrook | tcg_gen_st_i32(cpu_T[0], cpu_env, offsetof(CPUState, regs[15])); |
898 | 2c0262af | bellard | } |
899 | 2c0262af | bellard | |
900 | 2c0262af | bellard | static inline void gen_movl_reg_TN(DisasContext *s, int reg, int t) |
901 | 2c0262af | bellard | { |
902 | b26eefb6 | pbrook | TCGv tmp; |
903 | b26eefb6 | pbrook | if (reg == 15) { |
904 | b26eefb6 | pbrook | tmp = new_tmp(); |
905 | b26eefb6 | pbrook | tcg_gen_andi_i32(tmp, cpu_T[t], ~1);
|
906 | b26eefb6 | pbrook | } else {
|
907 | b26eefb6 | pbrook | tmp = cpu_T[t]; |
908 | b26eefb6 | pbrook | } |
909 | b26eefb6 | pbrook | tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, regs[reg])); |
910 | 2c0262af | bellard | if (reg == 15) { |
911 | b26eefb6 | pbrook | dead_tmp(tmp); |
912 | 2c0262af | bellard | s->is_jmp = DISAS_JUMP; |
913 | 2c0262af | bellard | } |
914 | 2c0262af | bellard | } |
915 | 2c0262af | bellard | |
916 | 2c0262af | bellard | static inline void gen_movl_reg_T0(DisasContext *s, int reg) |
917 | 2c0262af | bellard | { |
918 | 2c0262af | bellard | gen_movl_reg_TN(s, reg, 0);
|
919 | 2c0262af | bellard | } |
920 | 2c0262af | bellard | |
921 | 2c0262af | bellard | static inline void gen_movl_reg_T1(DisasContext *s, int reg) |
922 | 2c0262af | bellard | { |
923 | 2c0262af | bellard | gen_movl_reg_TN(s, reg, 1);
|
924 | 2c0262af | bellard | } |
925 | 2c0262af | bellard | |
926 | b5ff1b31 | bellard | /* Force a TB lookup after an instruction that changes the CPU state. */
|
927 | b5ff1b31 | bellard | static inline void gen_lookup_tb(DisasContext *s) |
928 | b5ff1b31 | bellard | { |
929 | b5ff1b31 | bellard | gen_op_movl_T0_im(s->pc); |
930 | b5ff1b31 | bellard | gen_movl_reg_T0(s, 15);
|
931 | b5ff1b31 | bellard | s->is_jmp = DISAS_UPDATE; |
932 | b5ff1b31 | bellard | } |
933 | b5ff1b31 | bellard | |
934 | b0109805 | pbrook | static inline void gen_add_data_offset(DisasContext *s, unsigned int insn, |
935 | b0109805 | pbrook | TCGv var) |
936 | 2c0262af | bellard | { |
937 | 1e8d4eec | bellard | int val, rm, shift, shiftop;
|
938 | b26eefb6 | pbrook | TCGv offset; |
939 | 2c0262af | bellard | |
940 | 2c0262af | bellard | if (!(insn & (1 << 25))) { |
941 | 2c0262af | bellard | /* immediate */
|
942 | 2c0262af | bellard | val = insn & 0xfff;
|
943 | 2c0262af | bellard | if (!(insn & (1 << 23))) |
944 | 2c0262af | bellard | val = -val; |
945 | 537730b9 | bellard | if (val != 0) |
946 | b0109805 | pbrook | tcg_gen_addi_i32(var, var, val); |
947 | 2c0262af | bellard | } else {
|
948 | 2c0262af | bellard | /* shift/register */
|
949 | 2c0262af | bellard | rm = (insn) & 0xf;
|
950 | 2c0262af | bellard | shift = (insn >> 7) & 0x1f; |
951 | 1e8d4eec | bellard | shiftop = (insn >> 5) & 3; |
952 | b26eefb6 | pbrook | offset = load_reg(s, rm); |
953 | 9a119ff6 | pbrook | gen_arm_shift_im(offset, shiftop, shift, 0);
|
954 | 2c0262af | bellard | if (!(insn & (1 << 23))) |
955 | b0109805 | pbrook | tcg_gen_sub_i32(var, var, offset); |
956 | 2c0262af | bellard | else
|
957 | b0109805 | pbrook | tcg_gen_add_i32(var, var, offset); |
958 | b26eefb6 | pbrook | dead_tmp(offset); |
959 | 2c0262af | bellard | } |
960 | 2c0262af | bellard | } |
961 | 2c0262af | bellard | |
962 | 191f9a93 | pbrook | static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn, |
963 | b0109805 | pbrook | int extra, TCGv var)
|
964 | 2c0262af | bellard | { |
965 | 2c0262af | bellard | int val, rm;
|
966 | b26eefb6 | pbrook | TCGv offset; |
967 | 3b46e624 | ths | |
968 | 2c0262af | bellard | if (insn & (1 << 22)) { |
969 | 2c0262af | bellard | /* immediate */
|
970 | 2c0262af | bellard | val = (insn & 0xf) | ((insn >> 4) & 0xf0); |
971 | 2c0262af | bellard | if (!(insn & (1 << 23))) |
972 | 2c0262af | bellard | val = -val; |
973 | 18acad92 | pbrook | val += extra; |
974 | 537730b9 | bellard | if (val != 0) |
975 | b0109805 | pbrook | tcg_gen_addi_i32(var, var, val); |
976 | 2c0262af | bellard | } else {
|
977 | 2c0262af | bellard | /* register */
|
978 | 191f9a93 | pbrook | if (extra)
|
979 | b0109805 | pbrook | tcg_gen_addi_i32(var, var, extra); |
980 | 2c0262af | bellard | rm = (insn) & 0xf;
|
981 | b26eefb6 | pbrook | offset = load_reg(s, rm); |
982 | 2c0262af | bellard | if (!(insn & (1 << 23))) |
983 | b0109805 | pbrook | tcg_gen_sub_i32(var, var, offset); |
984 | 2c0262af | bellard | else
|
985 | b0109805 | pbrook | tcg_gen_add_i32(var, var, offset); |
986 | b26eefb6 | pbrook | dead_tmp(offset); |
987 | 2c0262af | bellard | } |
988 | 2c0262af | bellard | } |
989 | 2c0262af | bellard | |
990 | 4373f3ce | pbrook | #define VFP_OP2(name) \
|
991 | 4373f3ce | pbrook | static inline void gen_vfp_##name(int dp) \ |
992 | 4373f3ce | pbrook | { \ |
993 | 4373f3ce | pbrook | if (dp) \
|
994 | 4373f3ce | pbrook | gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, cpu_F1d, cpu_env); \ |
995 | 4373f3ce | pbrook | else \
|
996 | 4373f3ce | pbrook | gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, cpu_F1s, cpu_env); \ |
997 | b7bcbe95 | bellard | } |
998 | b7bcbe95 | bellard | |
999 | 4373f3ce | pbrook | #define VFP_OP1i(name) \
|
1000 | 9ee6e8bb | pbrook | static inline void gen_vfp_##name(int dp, int arg) \ |
1001 | 9ee6e8bb | pbrook | { \ |
1002 | 9ee6e8bb | pbrook | if (dp) \
|
1003 | 9ee6e8bb | pbrook | gen_op_vfp_##name##d(arg); \ |
1004 | 9ee6e8bb | pbrook | else \
|
1005 | 9ee6e8bb | pbrook | gen_op_vfp_##name##s(arg); \ |
1006 | 9ee6e8bb | pbrook | } |
1007 | 9ee6e8bb | pbrook | |
1008 | 4373f3ce | pbrook | VFP_OP2(add) |
1009 | 4373f3ce | pbrook | VFP_OP2(sub) |
1010 | 4373f3ce | pbrook | VFP_OP2(mul) |
1011 | 4373f3ce | pbrook | VFP_OP2(div) |
1012 | 4373f3ce | pbrook | |
1013 | 4373f3ce | pbrook | #undef VFP_OP2
|
1014 | 4373f3ce | pbrook | |
1015 | 4373f3ce | pbrook | static inline void gen_vfp_abs(int dp) |
1016 | 4373f3ce | pbrook | { |
1017 | 4373f3ce | pbrook | if (dp)
|
1018 | 4373f3ce | pbrook | gen_helper_vfp_absd(cpu_F0d, cpu_F0d); |
1019 | 4373f3ce | pbrook | else
|
1020 | 4373f3ce | pbrook | gen_helper_vfp_abss(cpu_F0s, cpu_F0s); |
1021 | 4373f3ce | pbrook | } |
1022 | 4373f3ce | pbrook | |
1023 | 4373f3ce | pbrook | static inline void gen_vfp_neg(int dp) |
1024 | 4373f3ce | pbrook | { |
1025 | 4373f3ce | pbrook | if (dp)
|
1026 | 4373f3ce | pbrook | gen_helper_vfp_negd(cpu_F0d, cpu_F0d); |
1027 | 4373f3ce | pbrook | else
|
1028 | 4373f3ce | pbrook | gen_helper_vfp_negs(cpu_F0s, cpu_F0s); |
1029 | 4373f3ce | pbrook | } |
1030 | 4373f3ce | pbrook | |
1031 | 4373f3ce | pbrook | static inline void gen_vfp_sqrt(int dp) |
1032 | 4373f3ce | pbrook | { |
1033 | 4373f3ce | pbrook | if (dp)
|
1034 | 4373f3ce | pbrook | gen_helper_vfp_sqrtd(cpu_F0d, cpu_F0d, cpu_env); |
1035 | 4373f3ce | pbrook | else
|
1036 | 4373f3ce | pbrook | gen_helper_vfp_sqrts(cpu_F0s, cpu_F0s, cpu_env); |
1037 | 4373f3ce | pbrook | } |
1038 | 4373f3ce | pbrook | |
1039 | 4373f3ce | pbrook | static inline void gen_vfp_cmp(int dp) |
1040 | 4373f3ce | pbrook | { |
1041 | 4373f3ce | pbrook | if (dp)
|
1042 | 4373f3ce | pbrook | gen_helper_vfp_cmpd(cpu_F0d, cpu_F1d, cpu_env); |
1043 | 4373f3ce | pbrook | else
|
1044 | 4373f3ce | pbrook | gen_helper_vfp_cmps(cpu_F0s, cpu_F1s, cpu_env); |
1045 | 4373f3ce | pbrook | } |
1046 | 4373f3ce | pbrook | |
1047 | 4373f3ce | pbrook | static inline void gen_vfp_cmpe(int dp) |
1048 | 4373f3ce | pbrook | { |
1049 | 4373f3ce | pbrook | if (dp)
|
1050 | 4373f3ce | pbrook | gen_helper_vfp_cmped(cpu_F0d, cpu_F1d, cpu_env); |
1051 | 4373f3ce | pbrook | else
|
1052 | 4373f3ce | pbrook | gen_helper_vfp_cmpes(cpu_F0s, cpu_F1s, cpu_env); |
1053 | 4373f3ce | pbrook | } |
1054 | 4373f3ce | pbrook | |
1055 | 4373f3ce | pbrook | static inline void gen_vfp_F1_ld0(int dp) |
1056 | 4373f3ce | pbrook | { |
1057 | 4373f3ce | pbrook | if (dp)
|
1058 | 4373f3ce | pbrook | tcg_gen_movi_i64(cpu_F0d, 0);
|
1059 | 4373f3ce | pbrook | else
|
1060 | 4373f3ce | pbrook | tcg_gen_movi_i32(cpu_F0s, 0);
|
1061 | 4373f3ce | pbrook | } |
1062 | 4373f3ce | pbrook | |
1063 | 4373f3ce | pbrook | static inline void gen_vfp_uito(int dp) |
1064 | 4373f3ce | pbrook | { |
1065 | 4373f3ce | pbrook | if (dp)
|
1066 | 4373f3ce | pbrook | gen_helper_vfp_uitod(cpu_F0d, cpu_F0s, cpu_env); |
1067 | 4373f3ce | pbrook | else
|
1068 | 4373f3ce | pbrook | gen_helper_vfp_uitos(cpu_F0s, cpu_F0s, cpu_env); |
1069 | 4373f3ce | pbrook | } |
1070 | 4373f3ce | pbrook | |
1071 | 4373f3ce | pbrook | static inline void gen_vfp_sito(int dp) |
1072 | 4373f3ce | pbrook | { |
1073 | 4373f3ce | pbrook | if (dp)
|
1074 | 4373f3ce | pbrook | gen_helper_vfp_uitod(cpu_F0d, cpu_F0s, cpu_env); |
1075 | 4373f3ce | pbrook | else
|
1076 | 4373f3ce | pbrook | gen_helper_vfp_uitos(cpu_F0s, cpu_F0s, cpu_env); |
1077 | 4373f3ce | pbrook | } |
1078 | 4373f3ce | pbrook | |
1079 | 4373f3ce | pbrook | static inline void gen_vfp_toui(int dp) |
1080 | 4373f3ce | pbrook | { |
1081 | 4373f3ce | pbrook | if (dp)
|
1082 | 4373f3ce | pbrook | gen_helper_vfp_touid(cpu_F0s, cpu_F0d, cpu_env); |
1083 | 4373f3ce | pbrook | else
|
1084 | 4373f3ce | pbrook | gen_helper_vfp_touis(cpu_F0s, cpu_F0s, cpu_env); |
1085 | 4373f3ce | pbrook | } |
1086 | 4373f3ce | pbrook | |
1087 | 4373f3ce | pbrook | static inline void gen_vfp_touiz(int dp) |
1088 | 4373f3ce | pbrook | { |
1089 | 4373f3ce | pbrook | if (dp)
|
1090 | 4373f3ce | pbrook | gen_helper_vfp_touizd(cpu_F0s, cpu_F0d, cpu_env); |
1091 | 4373f3ce | pbrook | else
|
1092 | 4373f3ce | pbrook | gen_helper_vfp_touizs(cpu_F0s, cpu_F0s, cpu_env); |
1093 | 4373f3ce | pbrook | } |
1094 | 4373f3ce | pbrook | |
1095 | 4373f3ce | pbrook | static inline void gen_vfp_tosi(int dp) |
1096 | 4373f3ce | pbrook | { |
1097 | 4373f3ce | pbrook | if (dp)
|
1098 | 4373f3ce | pbrook | gen_helper_vfp_tosid(cpu_F0s, cpu_F0d, cpu_env); |
1099 | 4373f3ce | pbrook | else
|
1100 | 4373f3ce | pbrook | gen_helper_vfp_tosis(cpu_F0s, cpu_F0s, cpu_env); |
1101 | 4373f3ce | pbrook | } |
1102 | 4373f3ce | pbrook | |
1103 | 4373f3ce | pbrook | static inline void gen_vfp_tosiz(int dp) |
1104 | 9ee6e8bb | pbrook | { |
1105 | 9ee6e8bb | pbrook | if (dp)
|
1106 | 4373f3ce | pbrook | gen_helper_vfp_tosizd(cpu_F0s, cpu_F0d, cpu_env); |
1107 | 9ee6e8bb | pbrook | else
|
1108 | 4373f3ce | pbrook | gen_helper_vfp_tosizs(cpu_F0s, cpu_F0s, cpu_env); |
1109 | 4373f3ce | pbrook | } |
1110 | 4373f3ce | pbrook | |
1111 | 4373f3ce | pbrook | #define VFP_GEN_FIX(name) \
|
1112 | 4373f3ce | pbrook | static inline void gen_vfp_##name(int dp, int shift) \ |
1113 | 4373f3ce | pbrook | { \ |
1114 | 4373f3ce | pbrook | if (dp) \
|
1115 | 4373f3ce | pbrook | gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, tcg_const_i32(shift), cpu_env);\ |
1116 | 4373f3ce | pbrook | else \
|
1117 | 4373f3ce | pbrook | gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, tcg_const_i32(shift), cpu_env);\ |
1118 | 9ee6e8bb | pbrook | } |
1119 | 4373f3ce | pbrook | VFP_GEN_FIX(tosh) |
1120 | 4373f3ce | pbrook | VFP_GEN_FIX(tosl) |
1121 | 4373f3ce | pbrook | VFP_GEN_FIX(touh) |
1122 | 4373f3ce | pbrook | VFP_GEN_FIX(toul) |
1123 | 4373f3ce | pbrook | VFP_GEN_FIX(shto) |
1124 | 4373f3ce | pbrook | VFP_GEN_FIX(slto) |
1125 | 4373f3ce | pbrook | VFP_GEN_FIX(uhto) |
1126 | 4373f3ce | pbrook | VFP_GEN_FIX(ulto) |
1127 | 4373f3ce | pbrook | #undef VFP_GEN_FIX
|
1128 | 9ee6e8bb | pbrook | |
1129 | b5ff1b31 | bellard | static inline void gen_vfp_ld(DisasContext *s, int dp) |
1130 | b5ff1b31 | bellard | { |
1131 | b5ff1b31 | bellard | if (dp)
|
1132 | 4373f3ce | pbrook | tcg_gen_qemu_ld64(cpu_F0d, cpu_T[1], IS_USER(s));
|
1133 | b5ff1b31 | bellard | else
|
1134 | 4373f3ce | pbrook | tcg_gen_qemu_ld32u(cpu_F0s, cpu_T[1], IS_USER(s));
|
1135 | b5ff1b31 | bellard | } |
1136 | b5ff1b31 | bellard | |
1137 | b5ff1b31 | bellard | static inline void gen_vfp_st(DisasContext *s, int dp) |
1138 | b5ff1b31 | bellard | { |
1139 | b5ff1b31 | bellard | if (dp)
|
1140 | 4373f3ce | pbrook | tcg_gen_qemu_st64(cpu_F0d, cpu_T[1], IS_USER(s));
|
1141 | b5ff1b31 | bellard | else
|
1142 | 4373f3ce | pbrook | tcg_gen_qemu_st32(cpu_F0s, cpu_T[1], IS_USER(s));
|
1143 | b5ff1b31 | bellard | } |
1144 | b5ff1b31 | bellard | |
1145 | 8e96005d | bellard | static inline long |
1146 | 8e96005d | bellard | vfp_reg_offset (int dp, int reg) |
1147 | 8e96005d | bellard | { |
1148 | 8e96005d | bellard | if (dp)
|
1149 | 8e96005d | bellard | return offsetof(CPUARMState, vfp.regs[reg]);
|
1150 | 8e96005d | bellard | else if (reg & 1) { |
1151 | 8e96005d | bellard | return offsetof(CPUARMState, vfp.regs[reg >> 1]) |
1152 | 8e96005d | bellard | + offsetof(CPU_DoubleU, l.upper); |
1153 | 8e96005d | bellard | } else {
|
1154 | 8e96005d | bellard | return offsetof(CPUARMState, vfp.regs[reg >> 1]) |
1155 | 8e96005d | bellard | + offsetof(CPU_DoubleU, l.lower); |
1156 | 8e96005d | bellard | } |
1157 | 8e96005d | bellard | } |
1158 | 9ee6e8bb | pbrook | |
1159 | 9ee6e8bb | pbrook | /* Return the offset of a 32-bit piece of a NEON register.
|
1160 | 9ee6e8bb | pbrook | zero is the least significant end of the register. */
|
1161 | 9ee6e8bb | pbrook | static inline long |
1162 | 9ee6e8bb | pbrook | neon_reg_offset (int reg, int n) |
1163 | 9ee6e8bb | pbrook | { |
1164 | 9ee6e8bb | pbrook | int sreg;
|
1165 | 9ee6e8bb | pbrook | sreg = reg * 2 + n;
|
1166 | 9ee6e8bb | pbrook | return vfp_reg_offset(0, sreg); |
1167 | 9ee6e8bb | pbrook | } |
1168 | 9ee6e8bb | pbrook | |
1169 | 9ee6e8bb | pbrook | #define NEON_GET_REG(T, reg, n) gen_op_neon_getreg_##T(neon_reg_offset(reg, n)) |
1170 | 9ee6e8bb | pbrook | #define NEON_SET_REG(T, reg, n) gen_op_neon_setreg_##T(neon_reg_offset(reg, n)) |
1171 | 9ee6e8bb | pbrook | |
1172 | 8f8e3aa4 | pbrook | static TCGv neon_load_reg(int reg, int pass) |
1173 | 8f8e3aa4 | pbrook | { |
1174 | 8f8e3aa4 | pbrook | TCGv tmp = new_tmp(); |
1175 | 8f8e3aa4 | pbrook | tcg_gen_ld_i32(tmp, cpu_env, neon_reg_offset(reg, pass)); |
1176 | 8f8e3aa4 | pbrook | return tmp;
|
1177 | 8f8e3aa4 | pbrook | } |
1178 | 8f8e3aa4 | pbrook | |
1179 | 8f8e3aa4 | pbrook | static void neon_store_reg(int reg, int pass, TCGv var) |
1180 | 8f8e3aa4 | pbrook | { |
1181 | 8f8e3aa4 | pbrook | tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass)); |
1182 | 8f8e3aa4 | pbrook | dead_tmp(var); |
1183 | 8f8e3aa4 | pbrook | } |
1184 | 8f8e3aa4 | pbrook | |
1185 | 4373f3ce | pbrook | #define tcg_gen_ld_f32 tcg_gen_ld_i32
|
1186 | 4373f3ce | pbrook | #define tcg_gen_ld_f64 tcg_gen_ld_i64
|
1187 | 4373f3ce | pbrook | #define tcg_gen_st_f32 tcg_gen_st_i32
|
1188 | 4373f3ce | pbrook | #define tcg_gen_st_f64 tcg_gen_st_i64
|
1189 | 4373f3ce | pbrook | |
1190 | b7bcbe95 | bellard | static inline void gen_mov_F0_vreg(int dp, int reg) |
1191 | b7bcbe95 | bellard | { |
1192 | b7bcbe95 | bellard | if (dp)
|
1193 | 4373f3ce | pbrook | tcg_gen_ld_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg)); |
1194 | b7bcbe95 | bellard | else
|
1195 | 4373f3ce | pbrook | tcg_gen_ld_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg)); |
1196 | b7bcbe95 | bellard | } |
1197 | b7bcbe95 | bellard | |
1198 | b7bcbe95 | bellard | static inline void gen_mov_F1_vreg(int dp, int reg) |
1199 | b7bcbe95 | bellard | { |
1200 | b7bcbe95 | bellard | if (dp)
|
1201 | 4373f3ce | pbrook | tcg_gen_ld_f64(cpu_F1d, cpu_env, vfp_reg_offset(dp, reg)); |
1202 | b7bcbe95 | bellard | else
|
1203 | 4373f3ce | pbrook | tcg_gen_ld_f32(cpu_F1s, cpu_env, vfp_reg_offset(dp, reg)); |
1204 | b7bcbe95 | bellard | } |
1205 | b7bcbe95 | bellard | |
1206 | b7bcbe95 | bellard | static inline void gen_mov_vreg_F0(int dp, int reg) |
1207 | b7bcbe95 | bellard | { |
1208 | b7bcbe95 | bellard | if (dp)
|
1209 | 4373f3ce | pbrook | tcg_gen_st_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg)); |
1210 | b7bcbe95 | bellard | else
|
1211 | 4373f3ce | pbrook | tcg_gen_st_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg)); |
1212 | b7bcbe95 | bellard | } |
1213 | b7bcbe95 | bellard | |
1214 | 18c9b560 | balrog | #define ARM_CP_RW_BIT (1 << 20) |
1215 | 18c9b560 | balrog | |
1216 | 18c9b560 | balrog | static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn) |
1217 | 18c9b560 | balrog | { |
1218 | 18c9b560 | balrog | int rd;
|
1219 | 18c9b560 | balrog | uint32_t offset; |
1220 | 18c9b560 | balrog | |
1221 | 18c9b560 | balrog | rd = (insn >> 16) & 0xf; |
1222 | 18c9b560 | balrog | gen_movl_T1_reg(s, rd); |
1223 | 18c9b560 | balrog | |
1224 | 18c9b560 | balrog | offset = (insn & 0xff) << ((insn >> 7) & 2); |
1225 | 18c9b560 | balrog | if (insn & (1 << 24)) { |
1226 | 18c9b560 | balrog | /* Pre indexed */
|
1227 | 18c9b560 | balrog | if (insn & (1 << 23)) |
1228 | 18c9b560 | balrog | gen_op_addl_T1_im(offset); |
1229 | 18c9b560 | balrog | else
|
1230 | 18c9b560 | balrog | gen_op_addl_T1_im(-offset); |
1231 | 18c9b560 | balrog | |
1232 | 18c9b560 | balrog | if (insn & (1 << 21)) |
1233 | 18c9b560 | balrog | gen_movl_reg_T1(s, rd); |
1234 | 18c9b560 | balrog | } else if (insn & (1 << 21)) { |
1235 | 18c9b560 | balrog | /* Post indexed */
|
1236 | 18c9b560 | balrog | if (insn & (1 << 23)) |
1237 | 18c9b560 | balrog | gen_op_movl_T0_im(offset); |
1238 | 18c9b560 | balrog | else
|
1239 | 18c9b560 | balrog | gen_op_movl_T0_im(- offset); |
1240 | 18c9b560 | balrog | gen_op_addl_T0_T1(); |
1241 | 18c9b560 | balrog | gen_movl_reg_T0(s, rd); |
1242 | 18c9b560 | balrog | } else if (!(insn & (1 << 23))) |
1243 | 18c9b560 | balrog | return 1; |
1244 | 18c9b560 | balrog | return 0; |
1245 | 18c9b560 | balrog | } |
1246 | 18c9b560 | balrog | |
1247 | 18c9b560 | balrog | static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask) |
1248 | 18c9b560 | balrog | { |
1249 | 18c9b560 | balrog | int rd = (insn >> 0) & 0xf; |
1250 | 18c9b560 | balrog | |
1251 | 18c9b560 | balrog | if (insn & (1 << 8)) |
1252 | 18c9b560 | balrog | if (rd < ARM_IWMMXT_wCGR0 || rd > ARM_IWMMXT_wCGR3)
|
1253 | 18c9b560 | balrog | return 1; |
1254 | 18c9b560 | balrog | else
|
1255 | 18c9b560 | balrog | gen_op_iwmmxt_movl_T0_wCx(rd); |
1256 | 18c9b560 | balrog | else
|
1257 | 18c9b560 | balrog | gen_op_iwmmxt_movl_T0_T1_wRn(rd); |
1258 | 18c9b560 | balrog | |
1259 | 18c9b560 | balrog | gen_op_movl_T1_im(mask); |
1260 | 18c9b560 | balrog | gen_op_andl_T0_T1(); |
1261 | 18c9b560 | balrog | return 0; |
1262 | 18c9b560 | balrog | } |
1263 | 18c9b560 | balrog | |
1264 | 18c9b560 | balrog | /* Disassemble an iwMMXt instruction. Returns nonzero if an error occured
|
1265 | 18c9b560 | balrog | (ie. an undefined instruction). */
|
1266 | 18c9b560 | balrog | static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn) |
1267 | 18c9b560 | balrog | { |
1268 | 18c9b560 | balrog | int rd, wrd;
|
1269 | 18c9b560 | balrog | int rdhi, rdlo, rd0, rd1, i;
|
1270 | b0109805 | pbrook | TCGv tmp; |
1271 | 18c9b560 | balrog | |
1272 | 18c9b560 | balrog | if ((insn & 0x0e000e00) == 0x0c000000) { |
1273 | 18c9b560 | balrog | if ((insn & 0x0fe00ff0) == 0x0c400000) { |
1274 | 18c9b560 | balrog | wrd = insn & 0xf;
|
1275 | 18c9b560 | balrog | rdlo = (insn >> 12) & 0xf; |
1276 | 18c9b560 | balrog | rdhi = (insn >> 16) & 0xf; |
1277 | 18c9b560 | balrog | if (insn & ARM_CP_RW_BIT) { /* TMRRC */ |
1278 | 18c9b560 | balrog | gen_op_iwmmxt_movl_T0_T1_wRn(wrd); |
1279 | 18c9b560 | balrog | gen_movl_reg_T0(s, rdlo); |
1280 | 18c9b560 | balrog | gen_movl_reg_T1(s, rdhi); |
1281 | 18c9b560 | balrog | } else { /* TMCRR */ |
1282 | 18c9b560 | balrog | gen_movl_T0_reg(s, rdlo); |
1283 | 18c9b560 | balrog | gen_movl_T1_reg(s, rdhi); |
1284 | 18c9b560 | balrog | gen_op_iwmmxt_movl_wRn_T0_T1(wrd); |
1285 | 18c9b560 | balrog | gen_op_iwmmxt_set_mup(); |
1286 | 18c9b560 | balrog | } |
1287 | 18c9b560 | balrog | return 0; |
1288 | 18c9b560 | balrog | } |
1289 | 18c9b560 | balrog | |
1290 | 18c9b560 | balrog | wrd = (insn >> 12) & 0xf; |
1291 | 18c9b560 | balrog | if (gen_iwmmxt_address(s, insn))
|
1292 | 18c9b560 | balrog | return 1; |
1293 | 18c9b560 | balrog | if (insn & ARM_CP_RW_BIT) {
|
1294 | 18c9b560 | balrog | if ((insn >> 28) == 0xf) { /* WLDRW wCx */ |
1295 | b0109805 | pbrook | tmp = gen_ld32(cpu_T[1], IS_USER(s));
|
1296 | b0109805 | pbrook | tcg_gen_mov_i32(cpu_T[0], tmp);
|
1297 | b0109805 | pbrook | dead_tmp(tmp); |
1298 | 18c9b560 | balrog | gen_op_iwmmxt_movl_wCx_T0(wrd); |
1299 | 18c9b560 | balrog | } else {
|
1300 | 18c9b560 | balrog | if (insn & (1 << 8)) |
1301 | 18c9b560 | balrog | if (insn & (1 << 22)) /* WLDRD */ |
1302 | 18c9b560 | balrog | gen_ldst(iwmmxt_ldq, s); |
1303 | 18c9b560 | balrog | else /* WLDRW wRd */ |
1304 | 18c9b560 | balrog | gen_ldst(iwmmxt_ldl, s); |
1305 | 18c9b560 | balrog | else
|
1306 | 18c9b560 | balrog | if (insn & (1 << 22)) /* WLDRH */ |
1307 | 18c9b560 | balrog | gen_ldst(iwmmxt_ldw, s); |
1308 | 18c9b560 | balrog | else /* WLDRB */ |
1309 | 18c9b560 | balrog | gen_ldst(iwmmxt_ldb, s); |
1310 | 18c9b560 | balrog | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1311 | 18c9b560 | balrog | } |
1312 | 18c9b560 | balrog | } else {
|
1313 | 18c9b560 | balrog | if ((insn >> 28) == 0xf) { /* WSTRW wCx */ |
1314 | 18c9b560 | balrog | gen_op_iwmmxt_movl_T0_wCx(wrd); |
1315 | b0109805 | pbrook | tmp = new_tmp(); |
1316 | b0109805 | pbrook | tcg_gen_mov_i32(tmp, cpu_T[0]);
|
1317 | b0109805 | pbrook | gen_st32(tmp, cpu_T[1], IS_USER(s));
|
1318 | 18c9b560 | balrog | } else {
|
1319 | 18c9b560 | balrog | gen_op_iwmmxt_movq_M0_wRn(wrd); |
1320 | 18c9b560 | balrog | if (insn & (1 << 8)) |
1321 | 18c9b560 | balrog | if (insn & (1 << 22)) /* WSTRD */ |
1322 | 18c9b560 | balrog | gen_ldst(iwmmxt_stq, s); |
1323 | 18c9b560 | balrog | else /* WSTRW wRd */ |
1324 | 18c9b560 | balrog | gen_ldst(iwmmxt_stl, s); |
1325 | 18c9b560 | balrog | else
|
1326 | 18c9b560 | balrog | if (insn & (1 << 22)) /* WSTRH */ |
1327 | 18c9b560 | balrog | gen_ldst(iwmmxt_ldw, s); |
1328 | 18c9b560 | balrog | else /* WSTRB */ |
1329 | 18c9b560 | balrog | gen_ldst(iwmmxt_stb, s); |
1330 | 18c9b560 | balrog | } |
1331 | 18c9b560 | balrog | } |
1332 | 18c9b560 | balrog | return 0; |
1333 | 18c9b560 | balrog | } |
1334 | 18c9b560 | balrog | |
1335 | 18c9b560 | balrog | if ((insn & 0x0f000000) != 0x0e000000) |
1336 | 18c9b560 | balrog | return 1; |
1337 | 18c9b560 | balrog | |
1338 | 18c9b560 | balrog | switch (((insn >> 12) & 0xf00) | ((insn >> 4) & 0xff)) { |
1339 | 18c9b560 | balrog | case 0x000: /* WOR */ |
1340 | 18c9b560 | balrog | wrd = (insn >> 12) & 0xf; |
1341 | 18c9b560 | balrog | rd0 = (insn >> 0) & 0xf; |
1342 | 18c9b560 | balrog | rd1 = (insn >> 16) & 0xf; |
1343 | 18c9b560 | balrog | gen_op_iwmmxt_movq_M0_wRn(rd0); |
1344 | 18c9b560 | balrog | gen_op_iwmmxt_orq_M0_wRn(rd1); |
1345 | 18c9b560 | balrog | gen_op_iwmmxt_setpsr_nz(); |
1346 | 18c9b560 | balrog | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1347 | 18c9b560 | balrog | gen_op_iwmmxt_set_mup(); |
1348 | 18c9b560 | balrog | gen_op_iwmmxt_set_cup(); |
1349 | 18c9b560 | balrog | break;
|
1350 | 18c9b560 | balrog | case 0x011: /* TMCR */ |
1351 | 18c9b560 | balrog | if (insn & 0xf) |
1352 | 18c9b560 | balrog | return 1; |
1353 | 18c9b560 | balrog | rd = (insn >> 12) & 0xf; |
1354 | 18c9b560 | balrog | wrd = (insn >> 16) & 0xf; |
1355 | 18c9b560 | balrog | switch (wrd) {
|
1356 | 18c9b560 | balrog | case ARM_IWMMXT_wCID:
|
1357 | 18c9b560 | balrog | case ARM_IWMMXT_wCASF:
|
1358 | 18c9b560 | balrog | break;
|
1359 | 18c9b560 | balrog | case ARM_IWMMXT_wCon:
|
1360 | 18c9b560 | balrog | gen_op_iwmmxt_set_cup(); |
1361 | 18c9b560 | balrog | /* Fall through. */
|
1362 | 18c9b560 | balrog | case ARM_IWMMXT_wCSSF:
|
1363 | 18c9b560 | balrog | gen_op_iwmmxt_movl_T0_wCx(wrd); |
1364 | 18c9b560 | balrog | gen_movl_T1_reg(s, rd); |
1365 | 18c9b560 | balrog | gen_op_bicl_T0_T1(); |
1366 | 18c9b560 | balrog | gen_op_iwmmxt_movl_wCx_T0(wrd); |
1367 | 18c9b560 | balrog | break;
|
1368 | 18c9b560 | balrog | case ARM_IWMMXT_wCGR0:
|
1369 | 18c9b560 | balrog | case ARM_IWMMXT_wCGR1:
|
1370 | 18c9b560 | balrog | case ARM_IWMMXT_wCGR2:
|
1371 | 18c9b560 | balrog | case ARM_IWMMXT_wCGR3:
|
1372 | 18c9b560 | balrog | gen_op_iwmmxt_set_cup(); |
1373 | 18c9b560 | balrog | gen_movl_reg_T0(s, rd); |
1374 | 18c9b560 | balrog | gen_op_iwmmxt_movl_wCx_T0(wrd); |
1375 | 18c9b560 | balrog | break;
|
1376 | 18c9b560 | balrog | default:
|
1377 | 18c9b560 | balrog | return 1; |
1378 | 18c9b560 | balrog | } |
1379 | 18c9b560 | balrog | break;
|
1380 | 18c9b560 | balrog | case 0x100: /* WXOR */ |
1381 | 18c9b560 | balrog | wrd = (insn >> 12) & 0xf; |
1382 | 18c9b560 | balrog | rd0 = (insn >> 0) & 0xf; |
1383 | 18c9b560 | balrog | rd1 = (insn >> 16) & 0xf; |
1384 | 18c9b560 | balrog | gen_op_iwmmxt_movq_M0_wRn(rd0); |
1385 | 18c9b560 | balrog | gen_op_iwmmxt_xorq_M0_wRn(rd1); |
1386 | 18c9b560 | balrog | gen_op_iwmmxt_setpsr_nz(); |
1387 | 18c9b560 | balrog | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1388 | 18c9b560 | balrog | gen_op_iwmmxt_set_mup(); |
1389 | 18c9b560 | balrog | gen_op_iwmmxt_set_cup(); |
1390 | 18c9b560 | balrog | break;
|
1391 | 18c9b560 | balrog | case 0x111: /* TMRC */ |
1392 | 18c9b560 | balrog | if (insn & 0xf) |
1393 | 18c9b560 | balrog | return 1; |
1394 | 18c9b560 | balrog | rd = (insn >> 12) & 0xf; |
1395 | 18c9b560 | balrog | wrd = (insn >> 16) & 0xf; |
1396 | 18c9b560 | balrog | gen_op_iwmmxt_movl_T0_wCx(wrd); |
1397 | 18c9b560 | balrog | gen_movl_reg_T0(s, rd); |
1398 | 18c9b560 | balrog | break;
|
1399 | 18c9b560 | balrog | case 0x300: /* WANDN */ |
1400 | 18c9b560 | balrog | wrd = (insn >> 12) & 0xf; |
1401 | 18c9b560 | balrog | rd0 = (insn >> 0) & 0xf; |
1402 | 18c9b560 | balrog | rd1 = (insn >> 16) & 0xf; |
1403 | 18c9b560 | balrog | gen_op_iwmmxt_movq_M0_wRn(rd0); |
1404 | 18c9b560 | balrog | gen_op_iwmmxt_negq_M0(); |
1405 | 18c9b560 | balrog | gen_op_iwmmxt_andq_M0_wRn(rd1); |
1406 | 18c9b560 | balrog | gen_op_iwmmxt_setpsr_nz(); |
1407 | 18c9b560 | balrog | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1408 | 18c9b560 | balrog | gen_op_iwmmxt_set_mup(); |
1409 | 18c9b560 | balrog | gen_op_iwmmxt_set_cup(); |
1410 | 18c9b560 | balrog | break;
|
1411 | 18c9b560 | balrog | case 0x200: /* WAND */ |
1412 | 18c9b560 | balrog | wrd = (insn >> 12) & 0xf; |
1413 | 18c9b560 | balrog | rd0 = (insn >> 0) & 0xf; |
1414 | 18c9b560 | balrog | rd1 = (insn >> 16) & 0xf; |
1415 | 18c9b560 | balrog | gen_op_iwmmxt_movq_M0_wRn(rd0); |
1416 | 18c9b560 | balrog | gen_op_iwmmxt_andq_M0_wRn(rd1); |
1417 | 18c9b560 | balrog | gen_op_iwmmxt_setpsr_nz(); |
1418 | 18c9b560 | balrog | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1419 | 18c9b560 | balrog | gen_op_iwmmxt_set_mup(); |
1420 | 18c9b560 | balrog | gen_op_iwmmxt_set_cup(); |
1421 | 18c9b560 | balrog | break;
|
1422 | 18c9b560 | balrog | case 0x810: case 0xa10: /* WMADD */ |
1423 | 18c9b560 | balrog | wrd = (insn >> 12) & 0xf; |
1424 | 18c9b560 | balrog | rd0 = (insn >> 0) & 0xf; |
1425 | 18c9b560 | balrog | rd1 = (insn >> 16) & 0xf; |
1426 | 18c9b560 | balrog | gen_op_iwmmxt_movq_M0_wRn(rd0); |
1427 | 18c9b560 | balrog | if (insn & (1 << 21)) |
1428 | 18c9b560 | balrog | gen_op_iwmmxt_maddsq_M0_wRn(rd1); |
1429 | 18c9b560 | balrog | else
|
1430 | 18c9b560 | balrog | gen_op_iwmmxt_madduq_M0_wRn(rd1); |
1431 | 18c9b560 | balrog | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1432 | 18c9b560 | balrog | gen_op_iwmmxt_set_mup(); |
1433 | 18c9b560 | balrog | break;
|
1434 | 18c9b560 | balrog | case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */ |
1435 | 18c9b560 | balrog | wrd = (insn >> 12) & 0xf; |
1436 | 18c9b560 | balrog | rd0 = (insn >> 16) & 0xf; |
1437 | 18c9b560 | balrog | rd1 = (insn >> 0) & 0xf; |
1438 | 18c9b560 | balrog | gen_op_iwmmxt_movq_M0_wRn(rd0); |
1439 | 18c9b560 | balrog | switch ((insn >> 22) & 3) { |
1440 | 18c9b560 | balrog | case 0: |
1441 | 18c9b560 | balrog | gen_op_iwmmxt_unpacklb_M0_wRn(rd1); |
1442 | 18c9b560 | balrog | break;
|
1443 | 18c9b560 | balrog | case 1: |
1444 | 18c9b560 | balrog | gen_op_iwmmxt_unpacklw_M0_wRn(rd1); |
1445 | 18c9b560 | balrog | break;
|
1446 | 18c9b560 | balrog | case 2: |
1447 | 18c9b560 | balrog | gen_op_iwmmxt_unpackll_M0_wRn(rd1); |
1448 | 18c9b560 | balrog | break;
|
1449 | 18c9b560 | balrog | case 3: |
1450 | 18c9b560 | balrog | return 1; |
1451 | 18c9b560 | balrog | } |
1452 | 18c9b560 | balrog | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1453 | 18c9b560 | balrog | gen_op_iwmmxt_set_mup(); |
1454 | 18c9b560 | balrog | gen_op_iwmmxt_set_cup(); |
1455 | 18c9b560 | balrog | break;
|
1456 | 18c9b560 | balrog | case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */ |
1457 | 18c9b560 | balrog | wrd = (insn >> 12) & 0xf; |
1458 | 18c9b560 | balrog | rd0 = (insn >> 16) & 0xf; |
1459 | 18c9b560 | balrog | rd1 = (insn >> 0) & 0xf; |
1460 | 18c9b560 | balrog | gen_op_iwmmxt_movq_M0_wRn(rd0); |
1461 | 18c9b560 | balrog | switch ((insn >> 22) & 3) { |
1462 | 18c9b560 | balrog | case 0: |
1463 | 18c9b560 | balrog | gen_op_iwmmxt_unpackhb_M0_wRn(rd1); |
1464 | 18c9b560 | balrog | break;
|
1465 | 18c9b560 | balrog | case 1: |
1466 | 18c9b560 | balrog | gen_op_iwmmxt_unpackhw_M0_wRn(rd1); |
1467 | 18c9b560 | balrog | break;
|
1468 | 18c9b560 | balrog | case 2: |
1469 | 18c9b560 | balrog | gen_op_iwmmxt_unpackhl_M0_wRn(rd1); |
1470 | 18c9b560 | balrog | break;
|
1471 | 18c9b560 | balrog | case 3: |
1472 | 18c9b560 | balrog | return 1; |
1473 | 18c9b560 | balrog | } |
1474 | 18c9b560 | balrog | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1475 | 18c9b560 | balrog | gen_op_iwmmxt_set_mup(); |
1476 | 18c9b560 | balrog | gen_op_iwmmxt_set_cup(); |
1477 | 18c9b560 | balrog | break;
|
1478 | 18c9b560 | balrog | case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */ |
1479 | 18c9b560 | balrog | wrd = (insn >> 12) & 0xf; |
1480 | 18c9b560 | balrog | rd0 = (insn >> 16) & 0xf; |
1481 | 18c9b560 | balrog | rd1 = (insn >> 0) & 0xf; |
1482 | 18c9b560 | balrog | gen_op_iwmmxt_movq_M0_wRn(rd0); |
1483 | 18c9b560 | balrog | if (insn & (1 << 22)) |
1484 | 18c9b560 | balrog | gen_op_iwmmxt_sadw_M0_wRn(rd1); |
1485 | 18c9b560 | balrog | else
|
1486 | 18c9b560 | balrog | gen_op_iwmmxt_sadb_M0_wRn(rd1); |
1487 | 18c9b560 | balrog | if (!(insn & (1 << 20))) |
1488 | 18c9b560 | balrog | gen_op_iwmmxt_addl_M0_wRn(wrd); |
1489 | 18c9b560 | balrog | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1490 | 18c9b560 | balrog | gen_op_iwmmxt_set_mup(); |
1491 | 18c9b560 | balrog | break;
|
1492 | 18c9b560 | balrog | case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */ |
1493 | 18c9b560 | balrog | wrd = (insn >> 12) & 0xf; |
1494 | 18c9b560 | balrog | rd0 = (insn >> 16) & 0xf; |
1495 | 18c9b560 | balrog | rd1 = (insn >> 0) & 0xf; |
1496 | 18c9b560 | balrog | gen_op_iwmmxt_movq_M0_wRn(rd0); |
1497 | 18c9b560 | balrog | if (insn & (1 << 21)) |
1498 | 18c9b560 | balrog | gen_op_iwmmxt_mulsw_M0_wRn(rd1, (insn & (1 << 20)) ? 16 : 0); |
1499 | 18c9b560 | balrog | else
|
1500 | 18c9b560 | balrog | gen_op_iwmmxt_muluw_M0_wRn(rd1, (insn & (1 << 20)) ? 16 : 0); |
1501 | 18c9b560 | balrog | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1502 | 18c9b560 | balrog | gen_op_iwmmxt_set_mup(); |
1503 | 18c9b560 | balrog | break;
|
1504 | 18c9b560 | balrog | case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */ |
1505 | 18c9b560 | balrog | wrd = (insn >> 12) & 0xf; |
1506 | 18c9b560 | balrog | rd0 = (insn >> 16) & 0xf; |
1507 | 18c9b560 | balrog | rd1 = (insn >> 0) & 0xf; |
1508 | 18c9b560 | balrog | gen_op_iwmmxt_movq_M0_wRn(rd0); |
1509 | 18c9b560 | balrog | if (insn & (1 << 21)) |
1510 | 18c9b560 | balrog | gen_op_iwmmxt_macsw_M0_wRn(rd1); |
1511 | 18c9b560 | balrog | else
|
1512 | 18c9b560 | balrog | gen_op_iwmmxt_macuw_M0_wRn(rd1); |
1513 | 18c9b560 | balrog | if (!(insn & (1 << 20))) { |
1514 | 18c9b560 | balrog | if (insn & (1 << 21)) |
1515 | 18c9b560 | balrog | gen_op_iwmmxt_addsq_M0_wRn(wrd); |
1516 | 18c9b560 | balrog | else
|
1517 | 18c9b560 | balrog | gen_op_iwmmxt_adduq_M0_wRn(wrd); |
1518 | 18c9b560 | balrog | } |
1519 | 18c9b560 | balrog | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1520 | 18c9b560 | balrog | gen_op_iwmmxt_set_mup(); |
1521 | 18c9b560 | balrog | break;
|
1522 | 18c9b560 | balrog | case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */ |
1523 | 18c9b560 | balrog | wrd = (insn >> 12) & 0xf; |
1524 | 18c9b560 | balrog | rd0 = (insn >> 16) & 0xf; |
1525 | 18c9b560 | balrog | rd1 = (insn >> 0) & 0xf; |
1526 | 18c9b560 | balrog | gen_op_iwmmxt_movq_M0_wRn(rd0); |
1527 | 18c9b560 | balrog | switch ((insn >> 22) & 3) { |
1528 | 18c9b560 | balrog | case 0: |
1529 | 18c9b560 | balrog | gen_op_iwmmxt_cmpeqb_M0_wRn(rd1); |
1530 | 18c9b560 | balrog | break;
|
1531 | 18c9b560 | balrog | case 1: |
1532 | 18c9b560 | balrog | gen_op_iwmmxt_cmpeqw_M0_wRn(rd1); |
1533 | 18c9b560 | balrog | break;
|
1534 | 18c9b560 | balrog | case 2: |
1535 | 18c9b560 | balrog | gen_op_iwmmxt_cmpeql_M0_wRn(rd1); |
1536 | 18c9b560 | balrog | break;
|
1537 | 18c9b560 | balrog | case 3: |
1538 | 18c9b560 | balrog | return 1; |
1539 | 18c9b560 | balrog | } |
1540 | 18c9b560 | balrog | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1541 | 18c9b560 | balrog | gen_op_iwmmxt_set_mup(); |
1542 | 18c9b560 | balrog | gen_op_iwmmxt_set_cup(); |
1543 | 18c9b560 | balrog | break;
|
1544 | 18c9b560 | balrog | case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */ |
1545 | 18c9b560 | balrog | wrd = (insn >> 12) & 0xf; |
1546 | 18c9b560 | balrog | rd0 = (insn >> 16) & 0xf; |
1547 | 18c9b560 | balrog | rd1 = (insn >> 0) & 0xf; |
1548 | 18c9b560 | balrog | gen_op_iwmmxt_movq_M0_wRn(rd0); |
1549 | 18c9b560 | balrog | if (insn & (1 << 22)) |
1550 | 18c9b560 | balrog | gen_op_iwmmxt_avgw_M0_wRn(rd1, (insn >> 20) & 1); |
1551 | 18c9b560 | balrog | else
|
1552 | 18c9b560 | balrog | gen_op_iwmmxt_avgb_M0_wRn(rd1, (insn >> 20) & 1); |
1553 | 18c9b560 | balrog | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1554 | 18c9b560 | balrog | gen_op_iwmmxt_set_mup(); |
1555 | 18c9b560 | balrog | gen_op_iwmmxt_set_cup(); |
1556 | 18c9b560 | balrog | break;
|
1557 | 18c9b560 | balrog | case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */ |
1558 | 18c9b560 | balrog | wrd = (insn >> 12) & 0xf; |
1559 | 18c9b560 | balrog | rd0 = (insn >> 16) & 0xf; |
1560 | 18c9b560 | balrog | rd1 = (insn >> 0) & 0xf; |
1561 | 18c9b560 | balrog | gen_op_iwmmxt_movq_M0_wRn(rd0); |
1562 | 18c9b560 | balrog | gen_op_iwmmxt_movl_T0_wCx(ARM_IWMMXT_wCGR0 + ((insn >> 20) & 3)); |
1563 | 18c9b560 | balrog | gen_op_movl_T1_im(7);
|
1564 | 18c9b560 | balrog | gen_op_andl_T0_T1(); |
1565 | 18c9b560 | balrog | gen_op_iwmmxt_align_M0_T0_wRn(rd1); |
1566 | 18c9b560 | balrog | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1567 | 18c9b560 | balrog | gen_op_iwmmxt_set_mup(); |
1568 | 18c9b560 | balrog | break;
|
1569 | 18c9b560 | balrog | case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */ |
1570 | 18c9b560 | balrog | rd = (insn >> 12) & 0xf; |
1571 | 18c9b560 | balrog | wrd = (insn >> 16) & 0xf; |
1572 | 18c9b560 | balrog | gen_movl_T0_reg(s, rd); |
1573 | 18c9b560 | balrog | gen_op_iwmmxt_movq_M0_wRn(wrd); |
1574 | 18c9b560 | balrog | switch ((insn >> 6) & 3) { |
1575 | 18c9b560 | balrog | case 0: |
1576 | 18c9b560 | balrog | gen_op_movl_T1_im(0xff);
|
1577 | 18c9b560 | balrog | gen_op_iwmmxt_insr_M0_T0_T1((insn & 7) << 3); |
1578 | 18c9b560 | balrog | break;
|
1579 | 18c9b560 | balrog | case 1: |
1580 | 18c9b560 | balrog | gen_op_movl_T1_im(0xffff);
|
1581 | 18c9b560 | balrog | gen_op_iwmmxt_insr_M0_T0_T1((insn & 3) << 4); |
1582 | 18c9b560 | balrog | break;
|
1583 | 18c9b560 | balrog | case 2: |
1584 | 18c9b560 | balrog | gen_op_movl_T1_im(0xffffffff);
|
1585 | 18c9b560 | balrog | gen_op_iwmmxt_insr_M0_T0_T1((insn & 1) << 5); |
1586 | 18c9b560 | balrog | break;
|
1587 | 18c9b560 | balrog | case 3: |
1588 | 18c9b560 | balrog | return 1; |
1589 | 18c9b560 | balrog | } |
1590 | 18c9b560 | balrog | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1591 | 18c9b560 | balrog | gen_op_iwmmxt_set_mup(); |
1592 | 18c9b560 | balrog | break;
|
1593 | 18c9b560 | balrog | case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */ |
1594 | 18c9b560 | balrog | rd = (insn >> 12) & 0xf; |
1595 | 18c9b560 | balrog | wrd = (insn >> 16) & 0xf; |
1596 | 18c9b560 | balrog | if (rd == 15) |
1597 | 18c9b560 | balrog | return 1; |
1598 | 18c9b560 | balrog | gen_op_iwmmxt_movq_M0_wRn(wrd); |
1599 | 18c9b560 | balrog | switch ((insn >> 22) & 3) { |
1600 | 18c9b560 | balrog | case 0: |
1601 | 18c9b560 | balrog | if (insn & 8) |
1602 | 18c9b560 | balrog | gen_op_iwmmxt_extrsb_T0_M0((insn & 7) << 3); |
1603 | 18c9b560 | balrog | else {
|
1604 | 18c9b560 | balrog | gen_op_movl_T1_im(0xff);
|
1605 | 18c9b560 | balrog | gen_op_iwmmxt_extru_T0_M0_T1((insn & 7) << 3); |
1606 | 18c9b560 | balrog | } |
1607 | 18c9b560 | balrog | break;
|
1608 | 18c9b560 | balrog | case 1: |
1609 | 18c9b560 | balrog | if (insn & 8) |
1610 | 18c9b560 | balrog | gen_op_iwmmxt_extrsw_T0_M0((insn & 3) << 4); |
1611 | 18c9b560 | balrog | else {
|
1612 | 18c9b560 | balrog | gen_op_movl_T1_im(0xffff);
|
1613 | 18c9b560 | balrog | gen_op_iwmmxt_extru_T0_M0_T1((insn & 3) << 4); |
1614 | 18c9b560 | balrog | } |
1615 | 18c9b560 | balrog | break;
|
1616 | 18c9b560 | balrog | case 2: |
1617 | 18c9b560 | balrog | gen_op_movl_T1_im(0xffffffff);
|
1618 | 18c9b560 | balrog | gen_op_iwmmxt_extru_T0_M0_T1((insn & 1) << 5); |
1619 | 18c9b560 | balrog | break;
|
1620 | 18c9b560 | balrog | case 3: |
1621 | 18c9b560 | balrog | return 1; |
1622 | 18c9b560 | balrog | } |
1623 | b26eefb6 | pbrook | gen_movl_reg_T0(s, rd); |
1624 | 18c9b560 | balrog | break;
|
1625 | 18c9b560 | balrog | case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */ |
1626 | 18c9b560 | balrog | if ((insn & 0x000ff008) != 0x0003f000) |
1627 | 18c9b560 | balrog | return 1; |
1628 | 18c9b560 | balrog | gen_op_iwmmxt_movl_T1_wCx(ARM_IWMMXT_wCASF); |
1629 | 18c9b560 | balrog | switch ((insn >> 22) & 3) { |
1630 | 18c9b560 | balrog | case 0: |
1631 | 18c9b560 | balrog | gen_op_shrl_T1_im(((insn & 7) << 2) + 0); |
1632 | 18c9b560 | balrog | break;
|
1633 | 18c9b560 | balrog | case 1: |
1634 | 18c9b560 | balrog | gen_op_shrl_T1_im(((insn & 3) << 3) + 4); |
1635 | 18c9b560 | balrog | break;
|
1636 | 18c9b560 | balrog | case 2: |
1637 | 18c9b560 | balrog | gen_op_shrl_T1_im(((insn & 1) << 4) + 12); |
1638 | 18c9b560 | balrog | break;
|
1639 | 18c9b560 | balrog | case 3: |
1640 | 18c9b560 | balrog | return 1; |
1641 | 18c9b560 | balrog | } |
1642 | 18c9b560 | balrog | gen_op_shll_T1_im(28);
|
1643 | d9ba4830 | pbrook | gen_set_nzcv(cpu_T[1]);
|
1644 | 18c9b560 | balrog | break;
|
1645 | 18c9b560 | balrog | case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */ |
1646 | 18c9b560 | balrog | rd = (insn >> 12) & 0xf; |
1647 | 18c9b560 | balrog | wrd = (insn >> 16) & 0xf; |
1648 | 18c9b560 | balrog | gen_movl_T0_reg(s, rd); |
1649 | 18c9b560 | balrog | switch ((insn >> 6) & 3) { |
1650 | 18c9b560 | balrog | case 0: |
1651 | 18c9b560 | balrog | gen_op_iwmmxt_bcstb_M0_T0(); |
1652 | 18c9b560 | balrog | break;
|
1653 | 18c9b560 | balrog | case 1: |
1654 | 18c9b560 | balrog | gen_op_iwmmxt_bcstw_M0_T0(); |
1655 | 18c9b560 | balrog | break;
|
1656 | 18c9b560 | balrog | case 2: |
1657 | 18c9b560 | balrog | gen_op_iwmmxt_bcstl_M0_T0(); |
1658 | 18c9b560 | balrog | break;
|
1659 | 18c9b560 | balrog | case 3: |
1660 | 18c9b560 | balrog | return 1; |
1661 | 18c9b560 | balrog | } |
1662 | 18c9b560 | balrog | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1663 | 18c9b560 | balrog | gen_op_iwmmxt_set_mup(); |
1664 | 18c9b560 | balrog | break;
|
1665 | 18c9b560 | balrog | case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */ |
1666 | 18c9b560 | balrog | if ((insn & 0x000ff00f) != 0x0003f000) |
1667 | 18c9b560 | balrog | return 1; |
1668 | 18c9b560 | balrog | gen_op_iwmmxt_movl_T1_wCx(ARM_IWMMXT_wCASF); |
1669 | 18c9b560 | balrog | switch ((insn >> 22) & 3) { |
1670 | 18c9b560 | balrog | case 0: |
1671 | 18c9b560 | balrog | for (i = 0; i < 7; i ++) { |
1672 | 18c9b560 | balrog | gen_op_shll_T1_im(4);
|
1673 | 18c9b560 | balrog | gen_op_andl_T0_T1(); |
1674 | 18c9b560 | balrog | } |
1675 | 18c9b560 | balrog | break;
|
1676 | 18c9b560 | balrog | case 1: |
1677 | 18c9b560 | balrog | for (i = 0; i < 3; i ++) { |
1678 | 18c9b560 | balrog | gen_op_shll_T1_im(8);
|
1679 | 18c9b560 | balrog | gen_op_andl_T0_T1(); |
1680 | 18c9b560 | balrog | } |
1681 | 18c9b560 | balrog | break;
|
1682 | 18c9b560 | balrog | case 2: |
1683 | 18c9b560 | balrog | gen_op_shll_T1_im(16);
|
1684 | 18c9b560 | balrog | gen_op_andl_T0_T1(); |
1685 | 18c9b560 | balrog | break;
|
1686 | 18c9b560 | balrog | case 3: |
1687 | 18c9b560 | balrog | return 1; |
1688 | 18c9b560 | balrog | } |
1689 | d9ba4830 | pbrook | gen_set_nzcv(cpu_T[0]);
|
1690 | 18c9b560 | balrog | break;
|
1691 | 18c9b560 | balrog | case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */ |
1692 | 18c9b560 | balrog | wrd = (insn >> 12) & 0xf; |
1693 | 18c9b560 | balrog | rd0 = (insn >> 16) & 0xf; |
1694 | 18c9b560 | balrog | gen_op_iwmmxt_movq_M0_wRn(rd0); |
1695 | 18c9b560 | balrog | switch ((insn >> 22) & 3) { |
1696 | 18c9b560 | balrog | case 0: |
1697 | 18c9b560 | balrog | gen_op_iwmmxt_addcb_M0(); |
1698 | 18c9b560 | balrog | break;
|
1699 | 18c9b560 | balrog | case 1: |
1700 | 18c9b560 | balrog | gen_op_iwmmxt_addcw_M0(); |
1701 | 18c9b560 | balrog | break;
|
1702 | 18c9b560 | balrog | case 2: |
1703 | 18c9b560 | balrog | gen_op_iwmmxt_addcl_M0(); |
1704 | 18c9b560 | balrog | break;
|
1705 | 18c9b560 | balrog | case 3: |
1706 | 18c9b560 | balrog | return 1; |
1707 | 18c9b560 | balrog | } |
1708 | 18c9b560 | balrog | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1709 | 18c9b560 | balrog | gen_op_iwmmxt_set_mup(); |
1710 | 18c9b560 | balrog | break;
|
1711 | 18c9b560 | balrog | case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */ |
1712 | 18c9b560 | balrog | if ((insn & 0x000ff00f) != 0x0003f000) |
1713 | 18c9b560 | balrog | return 1; |
1714 | 18c9b560 | balrog | gen_op_iwmmxt_movl_T1_wCx(ARM_IWMMXT_wCASF); |
1715 | 18c9b560 | balrog | switch ((insn >> 22) & 3) { |
1716 | 18c9b560 | balrog | case 0: |
1717 | 18c9b560 | balrog | for (i = 0; i < 7; i ++) { |
1718 | 18c9b560 | balrog | gen_op_shll_T1_im(4);
|
1719 | 18c9b560 | balrog | gen_op_orl_T0_T1(); |
1720 | 18c9b560 | balrog | } |
1721 | 18c9b560 | balrog | break;
|
1722 | 18c9b560 | balrog | case 1: |
1723 | 18c9b560 | balrog | for (i = 0; i < 3; i ++) { |
1724 | 18c9b560 | balrog | gen_op_shll_T1_im(8);
|
1725 | 18c9b560 | balrog | gen_op_orl_T0_T1(); |
1726 | 18c9b560 | balrog | } |
1727 | 18c9b560 | balrog | break;
|
1728 | 18c9b560 | balrog | case 2: |
1729 | 18c9b560 | balrog | gen_op_shll_T1_im(16);
|
1730 | 18c9b560 | balrog | gen_op_orl_T0_T1(); |
1731 | 18c9b560 | balrog | break;
|
1732 | 18c9b560 | balrog | case 3: |
1733 | 18c9b560 | balrog | return 1; |
1734 | 18c9b560 | balrog | } |
1735 | d9ba4830 | pbrook | gen_set_nzcv(cpu_T[0]);
|
1736 | 18c9b560 | balrog | break;
|
1737 | 18c9b560 | balrog | case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */ |
1738 | 18c9b560 | balrog | rd = (insn >> 12) & 0xf; |
1739 | 18c9b560 | balrog | rd0 = (insn >> 16) & 0xf; |
1740 | 18c9b560 | balrog | if ((insn & 0xf) != 0) |
1741 | 18c9b560 | balrog | return 1; |
1742 | 18c9b560 | balrog | gen_op_iwmmxt_movq_M0_wRn(rd0); |
1743 | 18c9b560 | balrog | switch ((insn >> 22) & 3) { |
1744 | 18c9b560 | balrog | case 0: |
1745 | 18c9b560 | balrog | gen_op_iwmmxt_msbb_T0_M0(); |
1746 | 18c9b560 | balrog | break;
|
1747 | 18c9b560 | balrog | case 1: |
1748 | 18c9b560 | balrog | gen_op_iwmmxt_msbw_T0_M0(); |
1749 | 18c9b560 | balrog | break;
|
1750 | 18c9b560 | balrog | case 2: |
1751 | 18c9b560 | balrog | gen_op_iwmmxt_msbl_T0_M0(); |
1752 | 18c9b560 | balrog | break;
|
1753 | 18c9b560 | balrog | case 3: |
1754 | 18c9b560 | balrog | return 1; |
1755 | 18c9b560 | balrog | } |
1756 | 18c9b560 | balrog | gen_movl_reg_T0(s, rd); |
1757 | 18c9b560 | balrog | break;
|
1758 | 18c9b560 | balrog | case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */ |
1759 | 18c9b560 | balrog | case 0x906: case 0xb06: case 0xd06: case 0xf06: |
1760 | 18c9b560 | balrog | wrd = (insn >> 12) & 0xf; |
1761 | 18c9b560 | balrog | rd0 = (insn >> 16) & 0xf; |
1762 | 18c9b560 | balrog | rd1 = (insn >> 0) & 0xf; |
1763 | 18c9b560 | balrog | gen_op_iwmmxt_movq_M0_wRn(rd0); |
1764 | 18c9b560 | balrog | switch ((insn >> 22) & 3) { |
1765 | 18c9b560 | balrog | case 0: |
1766 | 18c9b560 | balrog | if (insn & (1 << 21)) |
1767 | 18c9b560 | balrog | gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1); |
1768 | 18c9b560 | balrog | else
|
1769 | 18c9b560 | balrog | gen_op_iwmmxt_cmpgtub_M0_wRn(rd1); |
1770 | 18c9b560 | balrog | break;
|
1771 | 18c9b560 | balrog | case 1: |
1772 | 18c9b560 | balrog | if (insn & (1 << 21)) |
1773 | 18c9b560 | balrog | gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1); |
1774 | 18c9b560 | balrog | else
|
1775 | 18c9b560 | balrog | gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1); |
1776 | 18c9b560 | balrog | break;
|
1777 | 18c9b560 | balrog | case 2: |
1778 | 18c9b560 | balrog | if (insn & (1 << 21)) |
1779 | 18c9b560 | balrog | gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1); |
1780 | 18c9b560 | balrog | else
|
1781 | 18c9b560 | balrog | gen_op_iwmmxt_cmpgtul_M0_wRn(rd1); |
1782 | 18c9b560 | balrog | break;
|
1783 | 18c9b560 | balrog | case 3: |
1784 | 18c9b560 | balrog | return 1; |
1785 | 18c9b560 | balrog | } |
1786 | 18c9b560 | balrog | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1787 | 18c9b560 | balrog | gen_op_iwmmxt_set_mup(); |
1788 | 18c9b560 | balrog | gen_op_iwmmxt_set_cup(); |
1789 | 18c9b560 | balrog | break;
|
1790 | 18c9b560 | balrog | case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */ |
1791 | 18c9b560 | balrog | case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e: |
1792 | 18c9b560 | balrog | wrd = (insn >> 12) & 0xf; |
1793 | 18c9b560 | balrog | rd0 = (insn >> 16) & 0xf; |
1794 | 18c9b560 | balrog | gen_op_iwmmxt_movq_M0_wRn(rd0); |
1795 | 18c9b560 | balrog | switch ((insn >> 22) & 3) { |
1796 | 18c9b560 | balrog | case 0: |
1797 | 18c9b560 | balrog | if (insn & (1 << 21)) |
1798 | 18c9b560 | balrog | gen_op_iwmmxt_unpacklsb_M0(); |
1799 | 18c9b560 | balrog | else
|
1800 | 18c9b560 | balrog | gen_op_iwmmxt_unpacklub_M0(); |
1801 | 18c9b560 | balrog | break;
|
1802 | 18c9b560 | balrog | case 1: |
1803 | 18c9b560 | balrog | if (insn & (1 << 21)) |
1804 | 18c9b560 | balrog | gen_op_iwmmxt_unpacklsw_M0(); |
1805 | 18c9b560 | balrog | else
|
1806 | 18c9b560 | balrog | gen_op_iwmmxt_unpackluw_M0(); |
1807 | 18c9b560 | balrog | break;
|
1808 | 18c9b560 | balrog | case 2: |
1809 | 18c9b560 | balrog | if (insn & (1 << 21)) |
1810 | 18c9b560 | balrog | gen_op_iwmmxt_unpacklsl_M0(); |
1811 | 18c9b560 | balrog | else
|
1812 | 18c9b560 | balrog | gen_op_iwmmxt_unpacklul_M0(); |
1813 | 18c9b560 | balrog | break;
|
1814 | 18c9b560 | balrog | case 3: |
1815 | 18c9b560 | balrog | return 1; |
1816 | 18c9b560 | balrog | } |
1817 | 18c9b560 | balrog | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1818 | 18c9b560 | balrog | gen_op_iwmmxt_set_mup(); |
1819 | 18c9b560 | balrog | gen_op_iwmmxt_set_cup(); |
1820 | 18c9b560 | balrog | break;
|
1821 | 18c9b560 | balrog | case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */ |
1822 | 18c9b560 | balrog | case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c: |
1823 | 18c9b560 | balrog | wrd = (insn >> 12) & 0xf; |
1824 | 18c9b560 | balrog | rd0 = (insn >> 16) & 0xf; |
1825 | 18c9b560 | balrog | gen_op_iwmmxt_movq_M0_wRn(rd0); |
1826 | 18c9b560 | balrog | switch ((insn >> 22) & 3) { |
1827 | 18c9b560 | balrog | case 0: |
1828 | 18c9b560 | balrog | if (insn & (1 << 21)) |
1829 | 18c9b560 | balrog | gen_op_iwmmxt_unpackhsb_M0(); |
1830 | 18c9b560 | balrog | else
|
1831 | 18c9b560 | balrog | gen_op_iwmmxt_unpackhub_M0(); |
1832 | 18c9b560 | balrog | break;
|
1833 | 18c9b560 | balrog | case 1: |
1834 | 18c9b560 | balrog | if (insn & (1 << 21)) |
1835 | 18c9b560 | balrog | gen_op_iwmmxt_unpackhsw_M0(); |
1836 | 18c9b560 | balrog | else
|
1837 | 18c9b560 | balrog | gen_op_iwmmxt_unpackhuw_M0(); |
1838 | 18c9b560 | balrog | break;
|
1839 | 18c9b560 | balrog | case 2: |
1840 | 18c9b560 | balrog | if (insn & (1 << 21)) |
1841 | 18c9b560 | balrog | gen_op_iwmmxt_unpackhsl_M0(); |
1842 | 18c9b560 | balrog | else
|
1843 | 18c9b560 | balrog | gen_op_iwmmxt_unpackhul_M0(); |
1844 | 18c9b560 | balrog | break;
|
1845 | 18c9b560 | balrog | case 3: |
1846 | 18c9b560 | balrog | return 1; |
1847 | 18c9b560 | balrog | } |
1848 | 18c9b560 | balrog | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1849 | 18c9b560 | balrog | gen_op_iwmmxt_set_mup(); |
1850 | 18c9b560 | balrog | gen_op_iwmmxt_set_cup(); |
1851 | 18c9b560 | balrog | break;
|
1852 | 18c9b560 | balrog | case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */ |
1853 | 18c9b560 | balrog | case 0x214: case 0x614: case 0xa14: case 0xe14: |
1854 | 18c9b560 | balrog | wrd = (insn >> 12) & 0xf; |
1855 | 18c9b560 | balrog | rd0 = (insn >> 16) & 0xf; |
1856 | 18c9b560 | balrog | gen_op_iwmmxt_movq_M0_wRn(rd0); |
1857 | 18c9b560 | balrog | if (gen_iwmmxt_shift(insn, 0xff)) |
1858 | 18c9b560 | balrog | return 1; |
1859 | 18c9b560 | balrog | switch ((insn >> 22) & 3) { |
1860 | 18c9b560 | balrog | case 0: |
1861 | 18c9b560 | balrog | return 1; |
1862 | 18c9b560 | balrog | case 1: |
1863 | 18c9b560 | balrog | gen_op_iwmmxt_srlw_M0_T0(); |
1864 | 18c9b560 | balrog | break;
|
1865 | 18c9b560 | balrog | case 2: |
1866 | 18c9b560 | balrog | gen_op_iwmmxt_srll_M0_T0(); |
1867 | 18c9b560 | balrog | break;
|
1868 | 18c9b560 | balrog | case 3: |
1869 | 18c9b560 | balrog | gen_op_iwmmxt_srlq_M0_T0(); |
1870 | 18c9b560 | balrog | break;
|
1871 | 18c9b560 | balrog | } |
1872 | 18c9b560 | balrog | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1873 | 18c9b560 | balrog | gen_op_iwmmxt_set_mup(); |
1874 | 18c9b560 | balrog | gen_op_iwmmxt_set_cup(); |
1875 | 18c9b560 | balrog | break;
|
1876 | 18c9b560 | balrog | case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */ |
1877 | 18c9b560 | balrog | case 0x014: case 0x414: case 0x814: case 0xc14: |
1878 | 18c9b560 | balrog | wrd = (insn >> 12) & 0xf; |
1879 | 18c9b560 | balrog | rd0 = (insn >> 16) & 0xf; |
1880 | 18c9b560 | balrog | gen_op_iwmmxt_movq_M0_wRn(rd0); |
1881 | 18c9b560 | balrog | if (gen_iwmmxt_shift(insn, 0xff)) |
1882 | 18c9b560 | balrog | return 1; |
1883 | 18c9b560 | balrog | switch ((insn >> 22) & 3) { |
1884 | 18c9b560 | balrog | case 0: |
1885 | 18c9b560 | balrog | return 1; |
1886 | 18c9b560 | balrog | case 1: |
1887 | 18c9b560 | balrog | gen_op_iwmmxt_sraw_M0_T0(); |
1888 | 18c9b560 | balrog | break;
|
1889 | 18c9b560 | balrog | case 2: |
1890 | 18c9b560 | balrog | gen_op_iwmmxt_sral_M0_T0(); |
1891 | 18c9b560 | balrog | break;
|
1892 | 18c9b560 | balrog | case 3: |
1893 | 18c9b560 | balrog | gen_op_iwmmxt_sraq_M0_T0(); |
1894 | 18c9b560 | balrog | break;
|
1895 | 18c9b560 | balrog | } |
1896 | 18c9b560 | balrog | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1897 | 18c9b560 | balrog | gen_op_iwmmxt_set_mup(); |
1898 | 18c9b560 | balrog | gen_op_iwmmxt_set_cup(); |
1899 | 18c9b560 | balrog | break;
|
1900 | 18c9b560 | balrog | case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */ |
1901 | 18c9b560 | balrog | case 0x114: case 0x514: case 0x914: case 0xd14: |
1902 | 18c9b560 | balrog | wrd = (insn >> 12) & 0xf; |
1903 | 18c9b560 | balrog | rd0 = (insn >> 16) & 0xf; |
1904 | 18c9b560 | balrog | gen_op_iwmmxt_movq_M0_wRn(rd0); |
1905 | 18c9b560 | balrog | if (gen_iwmmxt_shift(insn, 0xff)) |
1906 | 18c9b560 | balrog | return 1; |
1907 | 18c9b560 | balrog | switch ((insn >> 22) & 3) { |
1908 | 18c9b560 | balrog | case 0: |
1909 | 18c9b560 | balrog | return 1; |
1910 | 18c9b560 | balrog | case 1: |
1911 | 18c9b560 | balrog | gen_op_iwmmxt_sllw_M0_T0(); |
1912 | 18c9b560 | balrog | break;
|
1913 | 18c9b560 | balrog | case 2: |
1914 | 18c9b560 | balrog | gen_op_iwmmxt_slll_M0_T0(); |
1915 | 18c9b560 | balrog | break;
|
1916 | 18c9b560 | balrog | case 3: |
1917 | 18c9b560 | balrog | gen_op_iwmmxt_sllq_M0_T0(); |
1918 | 18c9b560 | balrog | break;
|
1919 | 18c9b560 | balrog | } |
1920 | 18c9b560 | balrog | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1921 | 18c9b560 | balrog | gen_op_iwmmxt_set_mup(); |
1922 | 18c9b560 | balrog | gen_op_iwmmxt_set_cup(); |
1923 | 18c9b560 | balrog | break;
|
1924 | 18c9b560 | balrog | case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */ |
1925 | 18c9b560 | balrog | case 0x314: case 0x714: case 0xb14: case 0xf14: |
1926 | 18c9b560 | balrog | wrd = (insn >> 12) & 0xf; |
1927 | 18c9b560 | balrog | rd0 = (insn >> 16) & 0xf; |
1928 | 18c9b560 | balrog | gen_op_iwmmxt_movq_M0_wRn(rd0); |
1929 | 18c9b560 | balrog | switch ((insn >> 22) & 3) { |
1930 | 18c9b560 | balrog | case 0: |
1931 | 18c9b560 | balrog | return 1; |
1932 | 18c9b560 | balrog | case 1: |
1933 | 18c9b560 | balrog | if (gen_iwmmxt_shift(insn, 0xf)) |
1934 | 18c9b560 | balrog | return 1; |
1935 | 18c9b560 | balrog | gen_op_iwmmxt_rorw_M0_T0(); |
1936 | 18c9b560 | balrog | break;
|
1937 | 18c9b560 | balrog | case 2: |
1938 | 18c9b560 | balrog | if (gen_iwmmxt_shift(insn, 0x1f)) |
1939 | 18c9b560 | balrog | return 1; |
1940 | 18c9b560 | balrog | gen_op_iwmmxt_rorl_M0_T0(); |
1941 | 18c9b560 | balrog | break;
|
1942 | 18c9b560 | balrog | case 3: |
1943 | 18c9b560 | balrog | if (gen_iwmmxt_shift(insn, 0x3f)) |
1944 | 18c9b560 | balrog | return 1; |
1945 | 18c9b560 | balrog | gen_op_iwmmxt_rorq_M0_T0(); |
1946 | 18c9b560 | balrog | break;
|
1947 | 18c9b560 | balrog | } |
1948 | 18c9b560 | balrog | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1949 | 18c9b560 | balrog | gen_op_iwmmxt_set_mup(); |
1950 | 18c9b560 | balrog | gen_op_iwmmxt_set_cup(); |
1951 | 18c9b560 | balrog | break;
|
1952 | 18c9b560 | balrog | case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */ |
1953 | 18c9b560 | balrog | case 0x916: case 0xb16: case 0xd16: case 0xf16: |
1954 | 18c9b560 | balrog | wrd = (insn >> 12) & 0xf; |
1955 | 18c9b560 | balrog | rd0 = (insn >> 16) & 0xf; |
1956 | 18c9b560 | balrog | rd1 = (insn >> 0) & 0xf; |
1957 | 18c9b560 | balrog | gen_op_iwmmxt_movq_M0_wRn(rd0); |
1958 | 18c9b560 | balrog | switch ((insn >> 22) & 3) { |
1959 | 18c9b560 | balrog | case 0: |
1960 | 18c9b560 | balrog | if (insn & (1 << 21)) |
1961 | 18c9b560 | balrog | gen_op_iwmmxt_minsb_M0_wRn(rd1); |
1962 | 18c9b560 | balrog | else
|
1963 | 18c9b560 | balrog | gen_op_iwmmxt_minub_M0_wRn(rd1); |
1964 | 18c9b560 | balrog | break;
|
1965 | 18c9b560 | balrog | case 1: |
1966 | 18c9b560 | balrog | if (insn & (1 << 21)) |
1967 | 18c9b560 | balrog | gen_op_iwmmxt_minsw_M0_wRn(rd1); |
1968 | 18c9b560 | balrog | else
|
1969 | 18c9b560 | balrog | gen_op_iwmmxt_minuw_M0_wRn(rd1); |
1970 | 18c9b560 | balrog | break;
|
1971 | 18c9b560 | balrog | case 2: |
1972 | 18c9b560 | balrog | if (insn & (1 << 21)) |
1973 | 18c9b560 | balrog | gen_op_iwmmxt_minsl_M0_wRn(rd1); |
1974 | 18c9b560 | balrog | else
|
1975 | 18c9b560 | balrog | gen_op_iwmmxt_minul_M0_wRn(rd1); |
1976 | 18c9b560 | balrog | break;
|
1977 | 18c9b560 | balrog | case 3: |
1978 | 18c9b560 | balrog | return 1; |
1979 | 18c9b560 | balrog | } |
1980 | 18c9b560 | balrog | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1981 | 18c9b560 | balrog | gen_op_iwmmxt_set_mup(); |
1982 | 18c9b560 | balrog | break;
|
1983 | 18c9b560 | balrog | case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */ |
1984 | 18c9b560 | balrog | case 0x816: case 0xa16: case 0xc16: case 0xe16: |
1985 | 18c9b560 | balrog | wrd = (insn >> 12) & 0xf; |
1986 | 18c9b560 | balrog | rd0 = (insn >> 16) & 0xf; |
1987 | 18c9b560 | balrog | rd1 = (insn >> 0) & 0xf; |
1988 | 18c9b560 | balrog | gen_op_iwmmxt_movq_M0_wRn(rd0); |
1989 | 18c9b560 | balrog | switch ((insn >> 22) & 3) { |
1990 | 18c9b560 | balrog | case 0: |
1991 | 18c9b560 | balrog | if (insn & (1 << 21)) |
1992 | 18c9b560 | balrog | gen_op_iwmmxt_maxsb_M0_wRn(rd1); |
1993 | 18c9b560 | balrog | else
|
1994 | 18c9b560 | balrog | gen_op_iwmmxt_maxub_M0_wRn(rd1); |
1995 | 18c9b560 | balrog | break;
|
1996 | 18c9b560 | balrog | case 1: |
1997 | 18c9b560 | balrog | if (insn & (1 << 21)) |
1998 | 18c9b560 | balrog | gen_op_iwmmxt_maxsw_M0_wRn(rd1); |
1999 | 18c9b560 | balrog | else
|
2000 | 18c9b560 | balrog | gen_op_iwmmxt_maxuw_M0_wRn(rd1); |
2001 | 18c9b560 | balrog | break;
|
2002 | 18c9b560 | balrog | case 2: |
2003 | 18c9b560 | balrog | if (insn & (1 << 21)) |
2004 | 18c9b560 | balrog | gen_op_iwmmxt_maxsl_M0_wRn(rd1); |
2005 | 18c9b560 | balrog | else
|
2006 | 18c9b560 | balrog | gen_op_iwmmxt_maxul_M0_wRn(rd1); |
2007 | 18c9b560 | balrog | break;
|
2008 | 18c9b560 | balrog | case 3: |
2009 | 18c9b560 | balrog | return 1; |
2010 | 18c9b560 | balrog | } |
2011 | 18c9b560 | balrog | gen_op_iwmmxt_movq_wRn_M0(wrd); |
2012 | 18c9b560 | balrog | gen_op_iwmmxt_set_mup(); |
2013 | 18c9b560 | balrog | break;
|
2014 | 18c9b560 | balrog | case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */ |
2015 | 18c9b560 | balrog | case 0x402: case 0x502: case 0x602: case 0x702: |
2016 | 18c9b560 | balrog | wrd = (insn >> 12) & 0xf; |
2017 | 18c9b560 | balrog | rd0 = (insn >> 16) & 0xf; |
2018 | 18c9b560 | balrog | rd1 = (insn >> 0) & 0xf; |
2019 | 18c9b560 | balrog | gen_op_iwmmxt_movq_M0_wRn(rd0); |
2020 | 18c9b560 | balrog | gen_op_movl_T0_im((insn >> 20) & 3); |
2021 | 18c9b560 | balrog | gen_op_iwmmxt_align_M0_T0_wRn(rd1); |
2022 | 18c9b560 | balrog | gen_op_iwmmxt_movq_wRn_M0(wrd); |
2023 | 18c9b560 | balrog | gen_op_iwmmxt_set_mup(); |
2024 | 18c9b560 | balrog | break;
|
2025 | 18c9b560 | balrog | case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */ |
2026 | 18c9b560 | balrog | case 0x41a: case 0x51a: case 0x61a: case 0x71a: |
2027 | 18c9b560 | balrog | case 0x81a: case 0x91a: case 0xa1a: case 0xb1a: |
2028 | 18c9b560 | balrog | case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a: |
2029 | 18c9b560 | balrog | wrd = (insn >> 12) & 0xf; |
2030 | 18c9b560 | balrog | rd0 = (insn >> 16) & 0xf; |
2031 | 18c9b560 | balrog | rd1 = (insn >> 0) & 0xf; |
2032 | 18c9b560 | balrog | gen_op_iwmmxt_movq_M0_wRn(rd0); |
2033 | 18c9b560 | balrog | switch ((insn >> 20) & 0xf) { |
2034 | 18c9b560 | balrog | case 0x0: |
2035 | 18c9b560 | balrog | gen_op_iwmmxt_subnb_M0_wRn(rd1); |
2036 | 18c9b560 | balrog | break;
|
2037 | 18c9b560 | balrog | case 0x1: |
2038 | 18c9b560 | balrog | gen_op_iwmmxt_subub_M0_wRn(rd1); |
2039 | 18c9b560 | balrog | break;
|
2040 | 18c9b560 | balrog | case 0x3: |
2041 | 18c9b560 | balrog | gen_op_iwmmxt_subsb_M0_wRn(rd1); |
2042 | 18c9b560 | balrog | break;
|
2043 | 18c9b560 | balrog | case 0x4: |
2044 | 18c9b560 | balrog | gen_op_iwmmxt_subnw_M0_wRn(rd1); |
2045 | 18c9b560 | balrog | break;
|
2046 | 18c9b560 | balrog | case 0x5: |
2047 | 18c9b560 | balrog | gen_op_iwmmxt_subuw_M0_wRn(rd1); |
2048 | 18c9b560 | balrog | break;
|
2049 | 18c9b560 | balrog | case 0x7: |
2050 | 18c9b560 | balrog | gen_op_iwmmxt_subsw_M0_wRn(rd1); |
2051 | 18c9b560 | balrog | break;
|
2052 | 18c9b560 | balrog | case 0x8: |
2053 | 18c9b560 | balrog | gen_op_iwmmxt_subnl_M0_wRn(rd1); |
2054 | 18c9b560 | balrog | break;
|
2055 | 18c9b560 | balrog | case 0x9: |
2056 | 18c9b560 | balrog | gen_op_iwmmxt_subul_M0_wRn(rd1); |
2057 | 18c9b560 | balrog | break;
|
2058 | 18c9b560 | balrog | case 0xb: |
2059 | 18c9b560 | balrog | gen_op_iwmmxt_subsl_M0_wRn(rd1); |
2060 | 18c9b560 | balrog | break;
|
2061 | 18c9b560 | balrog | default:
|
2062 | 18c9b560 | balrog | return 1; |
2063 | 18c9b560 | balrog | } |
2064 | 18c9b560 | balrog | gen_op_iwmmxt_movq_wRn_M0(wrd); |
2065 | 18c9b560 | balrog | gen_op_iwmmxt_set_mup(); |
2066 | 18c9b560 | balrog | gen_op_iwmmxt_set_cup(); |
2067 | 18c9b560 | balrog | break;
|
2068 | 18c9b560 | balrog | case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */ |
2069 | 18c9b560 | balrog | case 0x41e: case 0x51e: case 0x61e: case 0x71e: |
2070 | 18c9b560 | balrog | case 0x81e: case 0x91e: case 0xa1e: case 0xb1e: |
2071 | 18c9b560 | balrog | case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e: |
2072 | 18c9b560 | balrog | wrd = (insn >> 12) & 0xf; |
2073 | 18c9b560 | balrog | rd0 = (insn >> 16) & 0xf; |
2074 | 18c9b560 | balrog | gen_op_iwmmxt_movq_M0_wRn(rd0); |
2075 | 18c9b560 | balrog | gen_op_movl_T0_im(((insn >> 16) & 0xf0) | (insn & 0x0f)); |
2076 | 18c9b560 | balrog | gen_op_iwmmxt_shufh_M0_T0(); |
2077 | 18c9b560 | balrog | gen_op_iwmmxt_movq_wRn_M0(wrd); |
2078 | 18c9b560 | balrog | gen_op_iwmmxt_set_mup(); |
2079 | 18c9b560 | balrog | gen_op_iwmmxt_set_cup(); |
2080 | 18c9b560 | balrog | break;
|
2081 | 18c9b560 | balrog | case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */ |
2082 | 18c9b560 | balrog | case 0x418: case 0x518: case 0x618: case 0x718: |
2083 | 18c9b560 | balrog | case 0x818: case 0x918: case 0xa18: case 0xb18: |
2084 | 18c9b560 | balrog | case 0xc18: case 0xd18: case 0xe18: case 0xf18: |
2085 | 18c9b560 | balrog | wrd = (insn >> 12) & 0xf; |
2086 | 18c9b560 | balrog | rd0 = (insn >> 16) & 0xf; |
2087 | 18c9b560 | balrog | rd1 = (insn >> 0) & 0xf; |
2088 | 18c9b560 | balrog | gen_op_iwmmxt_movq_M0_wRn(rd0); |
2089 | 18c9b560 | balrog | switch ((insn >> 20) & 0xf) { |
2090 | 18c9b560 | balrog | case 0x0: |
2091 | 18c9b560 | balrog | gen_op_iwmmxt_addnb_M0_wRn(rd1); |
2092 | 18c9b560 | balrog | break;
|
2093 | 18c9b560 | balrog | case 0x1: |
2094 | 18c9b560 | balrog | gen_op_iwmmxt_addub_M0_wRn(rd1); |
2095 | 18c9b560 | balrog | break;
|
2096 | 18c9b560 | balrog | case 0x3: |
2097 | 18c9b560 | balrog | gen_op_iwmmxt_addsb_M0_wRn(rd1); |
2098 | 18c9b560 | balrog | break;
|
2099 | 18c9b560 | balrog | case 0x4: |
2100 | 18c9b560 | balrog | gen_op_iwmmxt_addnw_M0_wRn(rd1); |
2101 | 18c9b560 | balrog | break;
|
2102 | 18c9b560 | balrog | case 0x5: |
2103 | 18c9b560 | balrog | gen_op_iwmmxt_adduw_M0_wRn(rd1); |
2104 | 18c9b560 | balrog | break;
|
2105 | 18c9b560 | balrog | case 0x7: |
2106 | 18c9b560 | balrog | gen_op_iwmmxt_addsw_M0_wRn(rd1); |
2107 | 18c9b560 | balrog | break;
|
2108 | 18c9b560 | balrog | case 0x8: |
2109 | 18c9b560 | balrog | gen_op_iwmmxt_addnl_M0_wRn(rd1); |
2110 | 18c9b560 | balrog | break;
|
2111 | 18c9b560 | balrog | case 0x9: |
2112 | 18c9b560 | balrog | gen_op_iwmmxt_addul_M0_wRn(rd1); |
2113 | 18c9b560 | balrog | break;
|
2114 | 18c9b560 | balrog | case 0xb: |
2115 | 18c9b560 | balrog | gen_op_iwmmxt_addsl_M0_wRn(rd1); |
2116 | 18c9b560 | balrog | break;
|
2117 | 18c9b560 | balrog | default:
|
2118 | 18c9b560 | balrog | return 1; |
2119 | 18c9b560 | balrog | } |
2120 | 18c9b560 | balrog | gen_op_iwmmxt_movq_wRn_M0(wrd); |
2121 | 18c9b560 | balrog | gen_op_iwmmxt_set_mup(); |
2122 | 18c9b560 | balrog | gen_op_iwmmxt_set_cup(); |
2123 | 18c9b560 | balrog | break;
|
2124 | 18c9b560 | balrog | case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */ |
2125 | 18c9b560 | balrog | case 0x408: case 0x508: case 0x608: case 0x708: |
2126 | 18c9b560 | balrog | case 0x808: case 0x908: case 0xa08: case 0xb08: |
2127 | 18c9b560 | balrog | case 0xc08: case 0xd08: case 0xe08: case 0xf08: |
2128 | 18c9b560 | balrog | wrd = (insn >> 12) & 0xf; |
2129 | 18c9b560 | balrog | rd0 = (insn >> 16) & 0xf; |
2130 | 18c9b560 | balrog | rd1 = (insn >> 0) & 0xf; |
2131 | 18c9b560 | balrog | gen_op_iwmmxt_movq_M0_wRn(rd0); |
2132 | 18c9b560 | balrog | if (!(insn & (1 << 20))) |
2133 | 18c9b560 | balrog | return 1; |
2134 | 18c9b560 | balrog | switch ((insn >> 22) & 3) { |
2135 | 18c9b560 | balrog | case 0: |
2136 | 18c9b560 | balrog | return 1; |
2137 | 18c9b560 | balrog | case 1: |
2138 | 18c9b560 | balrog | if (insn & (1 << 21)) |
2139 | 18c9b560 | balrog | gen_op_iwmmxt_packsw_M0_wRn(rd1); |
2140 | 18c9b560 | balrog | else
|
2141 | 18c9b560 | balrog | gen_op_iwmmxt_packuw_M0_wRn(rd1); |
2142 | 18c9b560 | balrog | break;
|
2143 | 18c9b560 | balrog | case 2: |
2144 | 18c9b560 | balrog | if (insn & (1 << 21)) |
2145 | 18c9b560 | balrog | gen_op_iwmmxt_packsl_M0_wRn(rd1); |
2146 | 18c9b560 | balrog | else
|
2147 | 18c9b560 | balrog | gen_op_iwmmxt_packul_M0_wRn(rd1); |
2148 | 18c9b560 | balrog | break;
|
2149 | 18c9b560 | balrog | case 3: |
2150 | 18c9b560 | balrog | if (insn & (1 << 21)) |
2151 | 18c9b560 | balrog | gen_op_iwmmxt_packsq_M0_wRn(rd1); |
2152 | 18c9b560 | balrog | else
|
2153 | 18c9b560 | balrog | gen_op_iwmmxt_packuq_M0_wRn(rd1); |
2154 | 18c9b560 | balrog | break;
|
2155 | 18c9b560 | balrog | } |
2156 | 18c9b560 | balrog | gen_op_iwmmxt_movq_wRn_M0(wrd); |
2157 | 18c9b560 | balrog | gen_op_iwmmxt_set_mup(); |
2158 | 18c9b560 | balrog | gen_op_iwmmxt_set_cup(); |
2159 | 18c9b560 | balrog | break;
|
2160 | 18c9b560 | balrog | case 0x201: case 0x203: case 0x205: case 0x207: |
2161 | 18c9b560 | balrog | case 0x209: case 0x20b: case 0x20d: case 0x20f: |
2162 | 18c9b560 | balrog | case 0x211: case 0x213: case 0x215: case 0x217: |
2163 | 18c9b560 | balrog | case 0x219: case 0x21b: case 0x21d: case 0x21f: |
2164 | 18c9b560 | balrog | wrd = (insn >> 5) & 0xf; |
2165 | 18c9b560 | balrog | rd0 = (insn >> 12) & 0xf; |
2166 | 18c9b560 | balrog | rd1 = (insn >> 0) & 0xf; |
2167 | 18c9b560 | balrog | if (rd0 == 0xf || rd1 == 0xf) |
2168 | 18c9b560 | balrog | return 1; |
2169 | 18c9b560 | balrog | gen_op_iwmmxt_movq_M0_wRn(wrd); |
2170 | 18c9b560 | balrog | switch ((insn >> 16) & 0xf) { |
2171 | 18c9b560 | balrog | case 0x0: /* TMIA */ |
2172 | b26eefb6 | pbrook | gen_movl_T0_reg(s, rd0); |
2173 | b26eefb6 | pbrook | gen_movl_T1_reg(s, rd1); |
2174 | 18c9b560 | balrog | gen_op_iwmmxt_muladdsl_M0_T0_T1(); |
2175 | 18c9b560 | balrog | break;
|
2176 | 18c9b560 | balrog | case 0x8: /* TMIAPH */ |
2177 | b26eefb6 | pbrook | gen_movl_T0_reg(s, rd0); |
2178 | b26eefb6 | pbrook | gen_movl_T1_reg(s, rd1); |
2179 | 18c9b560 | balrog | gen_op_iwmmxt_muladdsw_M0_T0_T1(); |
2180 | 18c9b560 | balrog | break;
|
2181 | 18c9b560 | balrog | case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */ |
2182 | b26eefb6 | pbrook | gen_movl_T1_reg(s, rd0); |
2183 | 18c9b560 | balrog | if (insn & (1 << 16)) |
2184 | 18c9b560 | balrog | gen_op_shrl_T1_im(16);
|
2185 | 18c9b560 | balrog | gen_op_movl_T0_T1(); |
2186 | b26eefb6 | pbrook | gen_movl_T1_reg(s, rd1); |
2187 | 18c9b560 | balrog | if (insn & (1 << 17)) |
2188 | 18c9b560 | balrog | gen_op_shrl_T1_im(16);
|
2189 | 18c9b560 | balrog | gen_op_iwmmxt_muladdswl_M0_T0_T1(); |
2190 | 18c9b560 | balrog | break;
|
2191 | 18c9b560 | balrog | default:
|
2192 | 18c9b560 | balrog | return 1; |
2193 | 18c9b560 | balrog | } |
2194 | 18c9b560 | balrog | gen_op_iwmmxt_movq_wRn_M0(wrd); |
2195 | 18c9b560 | balrog | gen_op_iwmmxt_set_mup(); |
2196 | 18c9b560 | balrog | break;
|
2197 | 18c9b560 | balrog | default:
|
2198 | 18c9b560 | balrog | return 1; |
2199 | 18c9b560 | balrog | } |
2200 | 18c9b560 | balrog | |
2201 | 18c9b560 | balrog | return 0; |
2202 | 18c9b560 | balrog | } |
2203 | 18c9b560 | balrog | |
2204 | 18c9b560 | balrog | /* Disassemble an XScale DSP instruction. Returns nonzero if an error occured
|
2205 | 18c9b560 | balrog | (ie. an undefined instruction). */
|
2206 | 18c9b560 | balrog | static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn) |
2207 | 18c9b560 | balrog | { |
2208 | 18c9b560 | balrog | int acc, rd0, rd1, rdhi, rdlo;
|
2209 | 18c9b560 | balrog | |
2210 | 18c9b560 | balrog | if ((insn & 0x0ff00f10) == 0x0e200010) { |
2211 | 18c9b560 | balrog | /* Multiply with Internal Accumulate Format */
|
2212 | 18c9b560 | balrog | rd0 = (insn >> 12) & 0xf; |
2213 | 18c9b560 | balrog | rd1 = insn & 0xf;
|
2214 | 18c9b560 | balrog | acc = (insn >> 5) & 7; |
2215 | 18c9b560 | balrog | |
2216 | 18c9b560 | balrog | if (acc != 0) |
2217 | 18c9b560 | balrog | return 1; |
2218 | 18c9b560 | balrog | |
2219 | 18c9b560 | balrog | switch ((insn >> 16) & 0xf) { |
2220 | 18c9b560 | balrog | case 0x0: /* MIA */ |
2221 | b26eefb6 | pbrook | gen_movl_T0_reg(s, rd0); |
2222 | b26eefb6 | pbrook | gen_movl_T1_reg(s, rd1); |
2223 | 18c9b560 | balrog | gen_op_iwmmxt_muladdsl_M0_T0_T1(); |
2224 | 18c9b560 | balrog | break;
|
2225 | 18c9b560 | balrog | case 0x8: /* MIAPH */ |
2226 | b26eefb6 | pbrook | gen_movl_T0_reg(s, rd0); |
2227 | b26eefb6 | pbrook | gen_movl_T1_reg(s, rd1); |
2228 | 18c9b560 | balrog | gen_op_iwmmxt_muladdsw_M0_T0_T1(); |
2229 | 18c9b560 | balrog | break;
|
2230 | 18c9b560 | balrog | case 0xc: /* MIABB */ |
2231 | 18c9b560 | balrog | case 0xd: /* MIABT */ |
2232 | 18c9b560 | balrog | case 0xe: /* MIATB */ |
2233 | 18c9b560 | balrog | case 0xf: /* MIATT */ |
2234 | b26eefb6 | pbrook | gen_movl_T1_reg(s, rd0); |
2235 | 18c9b560 | balrog | if (insn & (1 << 16)) |
2236 | 18c9b560 | balrog | gen_op_shrl_T1_im(16);
|
2237 | 18c9b560 | balrog | gen_op_movl_T0_T1(); |
2238 | b26eefb6 | pbrook | gen_movl_T1_reg(s, rd1); |
2239 | 18c9b560 | balrog | if (insn & (1 << 17)) |
2240 | 18c9b560 | balrog | gen_op_shrl_T1_im(16);
|
2241 | 18c9b560 | balrog | gen_op_iwmmxt_muladdswl_M0_T0_T1(); |
2242 | 18c9b560 | balrog | break;
|
2243 | 18c9b560 | balrog | default:
|
2244 | 18c9b560 | balrog | return 1; |
2245 | 18c9b560 | balrog | } |
2246 | 18c9b560 | balrog | |
2247 | 18c9b560 | balrog | gen_op_iwmmxt_movq_wRn_M0(acc); |
2248 | 18c9b560 | balrog | return 0; |
2249 | 18c9b560 | balrog | } |
2250 | 18c9b560 | balrog | |
2251 | 18c9b560 | balrog | if ((insn & 0x0fe00ff8) == 0x0c400000) { |
2252 | 18c9b560 | balrog | /* Internal Accumulator Access Format */
|
2253 | 18c9b560 | balrog | rdhi = (insn >> 16) & 0xf; |
2254 | 18c9b560 | balrog | rdlo = (insn >> 12) & 0xf; |
2255 | 18c9b560 | balrog | acc = insn & 7;
|
2256 | 18c9b560 | balrog | |
2257 | 18c9b560 | balrog | if (acc != 0) |
2258 | 18c9b560 | balrog | return 1; |
2259 | 18c9b560 | balrog | |
2260 | 18c9b560 | balrog | if (insn & ARM_CP_RW_BIT) { /* MRA */ |
2261 | 18c9b560 | balrog | gen_op_iwmmxt_movl_T0_T1_wRn(acc); |
2262 | b26eefb6 | pbrook | gen_movl_reg_T0(s, rdlo); |
2263 | 18c9b560 | balrog | gen_op_movl_T0_im((1 << (40 - 32)) - 1); |
2264 | 18c9b560 | balrog | gen_op_andl_T0_T1(); |
2265 | b26eefb6 | pbrook | gen_movl_reg_T0(s, rdhi); |
2266 | 18c9b560 | balrog | } else { /* MAR */ |
2267 | b26eefb6 | pbrook | gen_movl_T0_reg(s, rdlo); |
2268 | b26eefb6 | pbrook | gen_movl_T1_reg(s, rdhi); |
2269 | 18c9b560 | balrog | gen_op_iwmmxt_movl_wRn_T0_T1(acc); |
2270 | 18c9b560 | balrog | } |
2271 | 18c9b560 | balrog | return 0; |
2272 | 18c9b560 | balrog | } |
2273 | 18c9b560 | balrog | |
2274 | 18c9b560 | balrog | return 1; |
2275 | 18c9b560 | balrog | } |
2276 | 18c9b560 | balrog | |
2277 | c1713132 | balrog | /* Disassemble system coprocessor instruction. Return nonzero if
|
2278 | c1713132 | balrog | instruction is not defined. */
|
2279 | c1713132 | balrog | static int disas_cp_insn(CPUState *env, DisasContext *s, uint32_t insn) |
2280 | c1713132 | balrog | { |
2281 | 8984bd2e | pbrook | TCGv tmp; |
2282 | c1713132 | balrog | uint32_t rd = (insn >> 12) & 0xf; |
2283 | c1713132 | balrog | uint32_t cp = (insn >> 8) & 0xf; |
2284 | c1713132 | balrog | if (IS_USER(s)) {
|
2285 | c1713132 | balrog | return 1; |
2286 | c1713132 | balrog | } |
2287 | c1713132 | balrog | |
2288 | 18c9b560 | balrog | if (insn & ARM_CP_RW_BIT) {
|
2289 | c1713132 | balrog | if (!env->cp[cp].cp_read)
|
2290 | c1713132 | balrog | return 1; |
2291 | 8984bd2e | pbrook | gen_set_pc_im(s->pc); |
2292 | 8984bd2e | pbrook | tmp = new_tmp(); |
2293 | 8984bd2e | pbrook | gen_helper_get_cp(tmp, cpu_env, tcg_const_i32(insn)); |
2294 | 8984bd2e | pbrook | store_reg(s, rd, tmp); |
2295 | c1713132 | balrog | } else {
|
2296 | c1713132 | balrog | if (!env->cp[cp].cp_write)
|
2297 | c1713132 | balrog | return 1; |
2298 | 8984bd2e | pbrook | gen_set_pc_im(s->pc); |
2299 | 8984bd2e | pbrook | tmp = load_reg(s, rd); |
2300 | 8984bd2e | pbrook | gen_helper_set_cp(cpu_env, tcg_const_i32(insn), tmp); |
2301 | c1713132 | balrog | } |
2302 | c1713132 | balrog | return 0; |
2303 | c1713132 | balrog | } |
2304 | c1713132 | balrog | |
2305 | 9ee6e8bb | pbrook | static int cp15_user_ok(uint32_t insn) |
2306 | 9ee6e8bb | pbrook | { |
2307 | 9ee6e8bb | pbrook | int cpn = (insn >> 16) & 0xf; |
2308 | 9ee6e8bb | pbrook | int cpm = insn & 0xf; |
2309 | 9ee6e8bb | pbrook | int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38); |
2310 | 9ee6e8bb | pbrook | |
2311 | 9ee6e8bb | pbrook | if (cpn == 13 && cpm == 0) { |
2312 | 9ee6e8bb | pbrook | /* TLS register. */
|
2313 | 9ee6e8bb | pbrook | if (op == 2 || (op == 3 && (insn & ARM_CP_RW_BIT))) |
2314 | 9ee6e8bb | pbrook | return 1; |
2315 | 9ee6e8bb | pbrook | } |
2316 | 9ee6e8bb | pbrook | if (cpn == 7) { |
2317 | 9ee6e8bb | pbrook | /* ISB, DSB, DMB. */
|
2318 | 9ee6e8bb | pbrook | if ((cpm == 5 && op == 4) |
2319 | 9ee6e8bb | pbrook | || (cpm == 10 && (op == 4 || op == 5))) |
2320 | 9ee6e8bb | pbrook | return 1; |
2321 | 9ee6e8bb | pbrook | } |
2322 | 9ee6e8bb | pbrook | return 0; |
2323 | 9ee6e8bb | pbrook | } |
2324 | 9ee6e8bb | pbrook | |
2325 | b5ff1b31 | bellard | /* Disassemble system coprocessor (cp15) instruction. Return nonzero if
|
2326 | b5ff1b31 | bellard | instruction is not defined. */
|
2327 | a90b7318 | balrog | static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn) |
2328 | b5ff1b31 | bellard | { |
2329 | b5ff1b31 | bellard | uint32_t rd; |
2330 | 8984bd2e | pbrook | TCGv tmp; |
2331 | b5ff1b31 | bellard | |
2332 | 9ee6e8bb | pbrook | /* M profile cores use memory mapped registers instead of cp15. */
|
2333 | 9ee6e8bb | pbrook | if (arm_feature(env, ARM_FEATURE_M))
|
2334 | 9ee6e8bb | pbrook | return 1; |
2335 | 9ee6e8bb | pbrook | |
2336 | 9ee6e8bb | pbrook | if ((insn & (1 << 25)) == 0) { |
2337 | 9ee6e8bb | pbrook | if (insn & (1 << 20)) { |
2338 | 9ee6e8bb | pbrook | /* mrrc */
|
2339 | 9ee6e8bb | pbrook | return 1; |
2340 | 9ee6e8bb | pbrook | } |
2341 | 9ee6e8bb | pbrook | /* mcrr. Used for block cache operations, so implement as no-op. */
|
2342 | 9ee6e8bb | pbrook | return 0; |
2343 | 9ee6e8bb | pbrook | } |
2344 | 9ee6e8bb | pbrook | if ((insn & (1 << 4)) == 0) { |
2345 | 9ee6e8bb | pbrook | /* cdp */
|
2346 | 9ee6e8bb | pbrook | return 1; |
2347 | 9ee6e8bb | pbrook | } |
2348 | 9ee6e8bb | pbrook | if (IS_USER(s) && !cp15_user_ok(insn)) {
|
2349 | b5ff1b31 | bellard | return 1; |
2350 | b5ff1b31 | bellard | } |
2351 | 9332f9da | bellard | if ((insn & 0x0fff0fff) == 0x0e070f90 |
2352 | 9332f9da | bellard | || (insn & 0x0fff0fff) == 0x0e070f58) { |
2353 | 9332f9da | bellard | /* Wait for interrupt. */
|
2354 | 8984bd2e | pbrook | gen_set_pc_im(s->pc); |
2355 | 9ee6e8bb | pbrook | s->is_jmp = DISAS_WFI; |
2356 | 9332f9da | bellard | return 0; |
2357 | 9332f9da | bellard | } |
2358 | b5ff1b31 | bellard | rd = (insn >> 12) & 0xf; |
2359 | 18c9b560 | balrog | if (insn & ARM_CP_RW_BIT) {
|
2360 | 8984bd2e | pbrook | tmp = new_tmp(); |
2361 | 8984bd2e | pbrook | gen_helper_get_cp15(tmp, cpu_env, tcg_const_i32(insn)); |
2362 | b5ff1b31 | bellard | /* If the destination register is r15 then sets condition codes. */
|
2363 | b5ff1b31 | bellard | if (rd != 15) |
2364 | 8984bd2e | pbrook | store_reg(s, rd, tmp); |
2365 | 8984bd2e | pbrook | else
|
2366 | 8984bd2e | pbrook | dead_tmp(tmp); |
2367 | b5ff1b31 | bellard | } else {
|
2368 | 8984bd2e | pbrook | tmp = load_reg(s, rd); |
2369 | 8984bd2e | pbrook | gen_helper_set_cp15(cpu_env, tcg_const_i32(insn), tmp); |
2370 | 8984bd2e | pbrook | dead_tmp(tmp); |
2371 | a90b7318 | balrog | /* Normally we would always end the TB here, but Linux
|
2372 | a90b7318 | balrog | * arch/arm/mach-pxa/sleep.S expects two instructions following
|
2373 | a90b7318 | balrog | * an MMU enable to execute from cache. Imitate this behaviour. */
|
2374 | a90b7318 | balrog | if (!arm_feature(env, ARM_FEATURE_XSCALE) ||
|
2375 | a90b7318 | balrog | (insn & 0x0fff0fff) != 0x0e010f10) |
2376 | a90b7318 | balrog | gen_lookup_tb(s); |
2377 | b5ff1b31 | bellard | } |
2378 | b5ff1b31 | bellard | return 0; |
2379 | b5ff1b31 | bellard | } |
2380 | b5ff1b31 | bellard | |
2381 | 9ee6e8bb | pbrook | #define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n)) |
2382 | 9ee6e8bb | pbrook | #define VFP_SREG(insn, bigbit, smallbit) \
|
2383 | 9ee6e8bb | pbrook | ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1)) |
2384 | 9ee6e8bb | pbrook | #define VFP_DREG(reg, insn, bigbit, smallbit) do { \ |
2385 | 9ee6e8bb | pbrook | if (arm_feature(env, ARM_FEATURE_VFP3)) { \
|
2386 | 9ee6e8bb | pbrook | reg = (((insn) >> (bigbit)) & 0x0f) \
|
2387 | 9ee6e8bb | pbrook | | (((insn) >> ((smallbit) - 4)) & 0x10); \ |
2388 | 9ee6e8bb | pbrook | } else { \
|
2389 | 9ee6e8bb | pbrook | if (insn & (1 << (smallbit))) \ |
2390 | 9ee6e8bb | pbrook | return 1; \ |
2391 | 9ee6e8bb | pbrook | reg = ((insn) >> (bigbit)) & 0x0f; \
|
2392 | 9ee6e8bb | pbrook | }} while (0) |
2393 | 9ee6e8bb | pbrook | |
2394 | 9ee6e8bb | pbrook | #define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22) |
2395 | 9ee6e8bb | pbrook | #define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22) |
2396 | 9ee6e8bb | pbrook | #define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7) |
2397 | 9ee6e8bb | pbrook | #define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7) |
2398 | 9ee6e8bb | pbrook | #define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5) |
2399 | 9ee6e8bb | pbrook | #define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5) |
2400 | 9ee6e8bb | pbrook | |
2401 | 4373f3ce | pbrook | /* Move between integer and VFP cores. */
|
2402 | 4373f3ce | pbrook | static TCGv gen_vfp_mrs(void) |
2403 | 4373f3ce | pbrook | { |
2404 | 4373f3ce | pbrook | TCGv tmp = new_tmp(); |
2405 | 4373f3ce | pbrook | tcg_gen_mov_i32(tmp, cpu_F0s); |
2406 | 4373f3ce | pbrook | return tmp;
|
2407 | 4373f3ce | pbrook | } |
2408 | 4373f3ce | pbrook | |
2409 | 4373f3ce | pbrook | static void gen_vfp_msr(TCGv tmp) |
2410 | 4373f3ce | pbrook | { |
2411 | 4373f3ce | pbrook | tcg_gen_mov_i32(cpu_F0s, tmp); |
2412 | 4373f3ce | pbrook | dead_tmp(tmp); |
2413 | 4373f3ce | pbrook | } |
2414 | 4373f3ce | pbrook | |
2415 | 9ee6e8bb | pbrook | static inline int |
2416 | 9ee6e8bb | pbrook | vfp_enabled(CPUState * env) |
2417 | 9ee6e8bb | pbrook | { |
2418 | 9ee6e8bb | pbrook | return ((env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) != 0); |
2419 | 9ee6e8bb | pbrook | } |
2420 | 9ee6e8bb | pbrook | |
2421 | b7bcbe95 | bellard | /* Disassemble a VFP instruction. Returns nonzero if an error occured
|
2422 | b7bcbe95 | bellard | (ie. an undefined instruction). */
|
2423 | b7bcbe95 | bellard | static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn) |
2424 | b7bcbe95 | bellard | { |
2425 | b7bcbe95 | bellard | uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask; |
2426 | b7bcbe95 | bellard | int dp, veclen;
|
2427 | 4373f3ce | pbrook | TCGv tmp; |
2428 | b7bcbe95 | bellard | |
2429 | 40f137e1 | pbrook | if (!arm_feature(env, ARM_FEATURE_VFP))
|
2430 | 40f137e1 | pbrook | return 1; |
2431 | 40f137e1 | pbrook | |
2432 | 9ee6e8bb | pbrook | if (!vfp_enabled(env)) {
|
2433 | 9ee6e8bb | pbrook | /* VFP disabled. Only allow fmxr/fmrx to/from some control regs. */
|
2434 | 40f137e1 | pbrook | if ((insn & 0x0fe00fff) != 0x0ee00a10) |
2435 | 40f137e1 | pbrook | return 1; |
2436 | 40f137e1 | pbrook | rn = (insn >> 16) & 0xf; |
2437 | 9ee6e8bb | pbrook | if (rn != ARM_VFP_FPSID && rn != ARM_VFP_FPEXC
|
2438 | 9ee6e8bb | pbrook | && rn != ARM_VFP_MVFR1 && rn != ARM_VFP_MVFR0) |
2439 | 40f137e1 | pbrook | return 1; |
2440 | 40f137e1 | pbrook | } |
2441 | b7bcbe95 | bellard | dp = ((insn & 0xf00) == 0xb00); |
2442 | b7bcbe95 | bellard | switch ((insn >> 24) & 0xf) { |
2443 | b7bcbe95 | bellard | case 0xe: |
2444 | b7bcbe95 | bellard | if (insn & (1 << 4)) { |
2445 | b7bcbe95 | bellard | /* single register transfer */
|
2446 | b7bcbe95 | bellard | rd = (insn >> 12) & 0xf; |
2447 | b7bcbe95 | bellard | if (dp) {
|
2448 | 9ee6e8bb | pbrook | int size;
|
2449 | 9ee6e8bb | pbrook | int pass;
|
2450 | 9ee6e8bb | pbrook | |
2451 | 9ee6e8bb | pbrook | VFP_DREG_N(rn, insn); |
2452 | 9ee6e8bb | pbrook | if (insn & 0xf) |
2453 | b7bcbe95 | bellard | return 1; |
2454 | 9ee6e8bb | pbrook | if (insn & 0x00c00060 |
2455 | 9ee6e8bb | pbrook | && !arm_feature(env, ARM_FEATURE_NEON)) |
2456 | 9ee6e8bb | pbrook | return 1; |
2457 | 9ee6e8bb | pbrook | |
2458 | 9ee6e8bb | pbrook | pass = (insn >> 21) & 1; |
2459 | 9ee6e8bb | pbrook | if (insn & (1 << 22)) { |
2460 | 9ee6e8bb | pbrook | size = 0;
|
2461 | 9ee6e8bb | pbrook | offset = ((insn >> 5) & 3) * 8; |
2462 | 9ee6e8bb | pbrook | } else if (insn & (1 << 5)) { |
2463 | 9ee6e8bb | pbrook | size = 1;
|
2464 | 9ee6e8bb | pbrook | offset = (insn & (1 << 6)) ? 16 : 0; |
2465 | 9ee6e8bb | pbrook | } else {
|
2466 | 9ee6e8bb | pbrook | size = 2;
|
2467 | 9ee6e8bb | pbrook | offset = 0;
|
2468 | 9ee6e8bb | pbrook | } |
2469 | 18c9b560 | balrog | if (insn & ARM_CP_RW_BIT) {
|
2470 | b7bcbe95 | bellard | /* vfp->arm */
|
2471 | 9ee6e8bb | pbrook | switch (size) {
|
2472 | 9ee6e8bb | pbrook | case 0: |
2473 | 9ee6e8bb | pbrook | NEON_GET_REG(T1, rn, pass); |
2474 | 9ee6e8bb | pbrook | if (offset)
|
2475 | 9ee6e8bb | pbrook | gen_op_shrl_T1_im(offset); |
2476 | 9ee6e8bb | pbrook | if (insn & (1 << 23)) |
2477 | b26eefb6 | pbrook | gen_uxtb(cpu_T[1]);
|
2478 | 9ee6e8bb | pbrook | else
|
2479 | b26eefb6 | pbrook | gen_sxtb(cpu_T[1]);
|
2480 | 9ee6e8bb | pbrook | break;
|
2481 | 9ee6e8bb | pbrook | case 1: |
2482 | 9ee6e8bb | pbrook | NEON_GET_REG(T1, rn, pass); |
2483 | 9ee6e8bb | pbrook | if (insn & (1 << 23)) { |
2484 | 9ee6e8bb | pbrook | if (offset) {
|
2485 | 9ee6e8bb | pbrook | gen_op_shrl_T1_im(16);
|
2486 | 9ee6e8bb | pbrook | } else {
|
2487 | b26eefb6 | pbrook | gen_uxth(cpu_T[1]);
|
2488 | 9ee6e8bb | pbrook | } |
2489 | 9ee6e8bb | pbrook | } else {
|
2490 | 9ee6e8bb | pbrook | if (offset) {
|
2491 | 9ee6e8bb | pbrook | gen_op_sarl_T1_im(16);
|
2492 | 9ee6e8bb | pbrook | } else {
|
2493 | b26eefb6 | pbrook | gen_sxth(cpu_T[1]);
|
2494 | 9ee6e8bb | pbrook | } |
2495 | 9ee6e8bb | pbrook | } |
2496 | 9ee6e8bb | pbrook | break;
|
2497 | 9ee6e8bb | pbrook | case 2: |
2498 | 9ee6e8bb | pbrook | NEON_GET_REG(T1, rn, pass); |
2499 | 9ee6e8bb | pbrook | break;
|
2500 | 9ee6e8bb | pbrook | } |
2501 | 9ee6e8bb | pbrook | gen_movl_reg_T1(s, rd); |
2502 | b7bcbe95 | bellard | } else {
|
2503 | b7bcbe95 | bellard | /* arm->vfp */
|
2504 | 9ee6e8bb | pbrook | gen_movl_T0_reg(s, rd); |
2505 | 9ee6e8bb | pbrook | if (insn & (1 << 23)) { |
2506 | 9ee6e8bb | pbrook | /* VDUP */
|
2507 | 9ee6e8bb | pbrook | if (size == 0) { |
2508 | 9ee6e8bb | pbrook | gen_op_neon_dup_u8(0);
|
2509 | 9ee6e8bb | pbrook | } else if (size == 1) { |
2510 | 9ee6e8bb | pbrook | gen_op_neon_dup_low16(); |
2511 | 9ee6e8bb | pbrook | } |
2512 | 9ee6e8bb | pbrook | NEON_SET_REG(T0, rn, 0);
|
2513 | 9ee6e8bb | pbrook | NEON_SET_REG(T0, rn, 1);
|
2514 | 9ee6e8bb | pbrook | } else {
|
2515 | 9ee6e8bb | pbrook | /* VMOV */
|
2516 | 9ee6e8bb | pbrook | switch (size) {
|
2517 | 9ee6e8bb | pbrook | case 0: |
2518 | 8f8e3aa4 | pbrook | tmp = neon_load_reg(rn, pass); |
2519 | 8f8e3aa4 | pbrook | gen_bfi(tmp, tmp, cpu_T[0], offset, 0xff); |
2520 | 8f8e3aa4 | pbrook | neon_store_reg(rn, pass, tmp); |
2521 | 9ee6e8bb | pbrook | break;
|
2522 | 9ee6e8bb | pbrook | case 1: |
2523 | 8f8e3aa4 | pbrook | tmp = neon_load_reg(rn, pass); |
2524 | 8f8e3aa4 | pbrook | gen_bfi(tmp, tmp, cpu_T[0], offset, 0xffff); |
2525 | 8f8e3aa4 | pbrook | neon_store_reg(rn, pass, tmp); |
2526 | 9ee6e8bb | pbrook | break;
|
2527 | 9ee6e8bb | pbrook | case 2: |
2528 | 9ee6e8bb | pbrook | NEON_SET_REG(T0, rn, pass); |
2529 | 9ee6e8bb | pbrook | break;
|
2530 | 9ee6e8bb | pbrook | } |
2531 | 9ee6e8bb | pbrook | } |
2532 | b7bcbe95 | bellard | } |
2533 | 9ee6e8bb | pbrook | } else { /* !dp */ |
2534 | 9ee6e8bb | pbrook | if ((insn & 0x6f) != 0x00) |
2535 | 9ee6e8bb | pbrook | return 1; |
2536 | 9ee6e8bb | pbrook | rn = VFP_SREG_N(insn); |
2537 | 18c9b560 | balrog | if (insn & ARM_CP_RW_BIT) {
|
2538 | b7bcbe95 | bellard | /* vfp->arm */
|
2539 | b7bcbe95 | bellard | if (insn & (1 << 21)) { |
2540 | b7bcbe95 | bellard | /* system register */
|
2541 | 40f137e1 | pbrook | rn >>= 1;
|
2542 | 9ee6e8bb | pbrook | |
2543 | b7bcbe95 | bellard | switch (rn) {
|
2544 | 40f137e1 | pbrook | case ARM_VFP_FPSID:
|
2545 | 4373f3ce | pbrook | /* VFP2 allows access to FSID from userspace.
|
2546 | 9ee6e8bb | pbrook | VFP3 restricts all id registers to privileged
|
2547 | 9ee6e8bb | pbrook | accesses. */
|
2548 | 9ee6e8bb | pbrook | if (IS_USER(s)
|
2549 | 9ee6e8bb | pbrook | && arm_feature(env, ARM_FEATURE_VFP3)) |
2550 | 9ee6e8bb | pbrook | return 1; |
2551 | 4373f3ce | pbrook | tmp = load_cpu_field(vfp.xregs[rn]); |
2552 | 9ee6e8bb | pbrook | break;
|
2553 | 40f137e1 | pbrook | case ARM_VFP_FPEXC:
|
2554 | 9ee6e8bb | pbrook | if (IS_USER(s))
|
2555 | 9ee6e8bb | pbrook | return 1; |
2556 | 4373f3ce | pbrook | tmp = load_cpu_field(vfp.xregs[rn]); |
2557 | 9ee6e8bb | pbrook | break;
|
2558 | 40f137e1 | pbrook | case ARM_VFP_FPINST:
|
2559 | 40f137e1 | pbrook | case ARM_VFP_FPINST2:
|
2560 | 9ee6e8bb | pbrook | /* Not present in VFP3. */
|
2561 | 9ee6e8bb | pbrook | if (IS_USER(s)
|
2562 | 9ee6e8bb | pbrook | || arm_feature(env, ARM_FEATURE_VFP3)) |
2563 | 9ee6e8bb | pbrook | return 1; |
2564 | 4373f3ce | pbrook | tmp = load_cpu_field(vfp.xregs[rn]); |
2565 | b7bcbe95 | bellard | break;
|
2566 | 40f137e1 | pbrook | case ARM_VFP_FPSCR:
|
2567 | 4373f3ce | pbrook | if (rd == 15) { |
2568 | 4373f3ce | pbrook | tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); |
2569 | 4373f3ce | pbrook | tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
|
2570 | 4373f3ce | pbrook | } else {
|
2571 | 4373f3ce | pbrook | tmp = new_tmp(); |
2572 | 4373f3ce | pbrook | gen_helper_vfp_get_fpscr(tmp, cpu_env); |
2573 | 4373f3ce | pbrook | } |
2574 | b7bcbe95 | bellard | break;
|
2575 | 9ee6e8bb | pbrook | case ARM_VFP_MVFR0:
|
2576 | 9ee6e8bb | pbrook | case ARM_VFP_MVFR1:
|
2577 | 9ee6e8bb | pbrook | if (IS_USER(s)
|
2578 | 9ee6e8bb | pbrook | || !arm_feature(env, ARM_FEATURE_VFP3)) |
2579 | 9ee6e8bb | pbrook | return 1; |
2580 | 4373f3ce | pbrook | tmp = load_cpu_field(vfp.xregs[rn]); |
2581 | 9ee6e8bb | pbrook | break;
|
2582 | b7bcbe95 | bellard | default:
|
2583 | b7bcbe95 | bellard | return 1; |
2584 | b7bcbe95 | bellard | } |
2585 | b7bcbe95 | bellard | } else {
|
2586 | b7bcbe95 | bellard | gen_mov_F0_vreg(0, rn);
|
2587 | 4373f3ce | pbrook | tmp = gen_vfp_mrs(); |
2588 | b7bcbe95 | bellard | } |
2589 | b7bcbe95 | bellard | if (rd == 15) { |
2590 | b5ff1b31 | bellard | /* Set the 4 flag bits in the CPSR. */
|
2591 | 4373f3ce | pbrook | gen_set_nzcv(tmp); |
2592 | 4373f3ce | pbrook | dead_tmp(tmp); |
2593 | 4373f3ce | pbrook | } else {
|
2594 | 4373f3ce | pbrook | store_reg(s, rd, tmp); |
2595 | 4373f3ce | pbrook | } |
2596 | b7bcbe95 | bellard | } else {
|
2597 | b7bcbe95 | bellard | /* arm->vfp */
|
2598 | 4373f3ce | pbrook | tmp = load_reg(s, rd); |
2599 | b7bcbe95 | bellard | if (insn & (1 << 21)) { |
2600 | 40f137e1 | pbrook | rn >>= 1;
|
2601 | b7bcbe95 | bellard | /* system register */
|
2602 | b7bcbe95 | bellard | switch (rn) {
|
2603 | 40f137e1 | pbrook | case ARM_VFP_FPSID:
|
2604 | 9ee6e8bb | pbrook | case ARM_VFP_MVFR0:
|
2605 | 9ee6e8bb | pbrook | case ARM_VFP_MVFR1:
|
2606 | b7bcbe95 | bellard | /* Writes are ignored. */
|
2607 | b7bcbe95 | bellard | break;
|
2608 | 40f137e1 | pbrook | case ARM_VFP_FPSCR:
|
2609 | 4373f3ce | pbrook | gen_helper_vfp_set_fpscr(cpu_env, tmp); |
2610 | 4373f3ce | pbrook | dead_tmp(tmp); |
2611 | b5ff1b31 | bellard | gen_lookup_tb(s); |
2612 | b7bcbe95 | bellard | break;
|
2613 | 40f137e1 | pbrook | case ARM_VFP_FPEXC:
|
2614 | 9ee6e8bb | pbrook | if (IS_USER(s))
|
2615 | 9ee6e8bb | pbrook | return 1; |
2616 | 4373f3ce | pbrook | store_cpu_field(tmp, vfp.xregs[rn]); |
2617 | 40f137e1 | pbrook | gen_lookup_tb(s); |
2618 | 40f137e1 | pbrook | break;
|
2619 | 40f137e1 | pbrook | case ARM_VFP_FPINST:
|
2620 | 40f137e1 | pbrook | case ARM_VFP_FPINST2:
|
2621 | 4373f3ce | pbrook | store_cpu_field(tmp, vfp.xregs[rn]); |
2622 | 40f137e1 | pbrook | break;
|
2623 | b7bcbe95 | bellard | default:
|
2624 | b7bcbe95 | bellard | return 1; |
2625 | b7bcbe95 | bellard | } |
2626 | b7bcbe95 | bellard | } else {
|
2627 | 4373f3ce | pbrook | gen_vfp_msr(tmp); |
2628 | b7bcbe95 | bellard | gen_mov_vreg_F0(0, rn);
|
2629 | b7bcbe95 | bellard | } |
2630 | b7bcbe95 | bellard | } |
2631 | b7bcbe95 | bellard | } |
2632 | b7bcbe95 | bellard | } else {
|
2633 | b7bcbe95 | bellard | /* data processing */
|
2634 | b7bcbe95 | bellard | /* The opcode is in bits 23, 21, 20 and 6. */
|
2635 | b7bcbe95 | bellard | op = ((insn >> 20) & 8) | ((insn >> 19) & 6) | ((insn >> 6) & 1); |
2636 | b7bcbe95 | bellard | if (dp) {
|
2637 | b7bcbe95 | bellard | if (op == 15) { |
2638 | b7bcbe95 | bellard | /* rn is opcode */
|
2639 | b7bcbe95 | bellard | rn = ((insn >> 15) & 0x1e) | ((insn >> 7) & 1); |
2640 | b7bcbe95 | bellard | } else {
|
2641 | b7bcbe95 | bellard | /* rn is register number */
|
2642 | 9ee6e8bb | pbrook | VFP_DREG_N(rn, insn); |
2643 | b7bcbe95 | bellard | } |
2644 | b7bcbe95 | bellard | |
2645 | b7bcbe95 | bellard | if (op == 15 && (rn == 15 || rn > 17)) { |
2646 | b7bcbe95 | bellard | /* Integer or single precision destination. */
|
2647 | 9ee6e8bb | pbrook | rd = VFP_SREG_D(insn); |
2648 | b7bcbe95 | bellard | } else {
|
2649 | 9ee6e8bb | pbrook | VFP_DREG_D(rd, insn); |
2650 | b7bcbe95 | bellard | } |
2651 | b7bcbe95 | bellard | |
2652 | b7bcbe95 | bellard | if (op == 15 && (rn == 16 || rn == 17)) { |
2653 | b7bcbe95 | bellard | /* Integer source. */
|
2654 | b7bcbe95 | bellard | rm = ((insn << 1) & 0x1e) | ((insn >> 5) & 1); |
2655 | b7bcbe95 | bellard | } else {
|
2656 | 9ee6e8bb | pbrook | VFP_DREG_M(rm, insn); |
2657 | b7bcbe95 | bellard | } |
2658 | b7bcbe95 | bellard | } else {
|
2659 | 9ee6e8bb | pbrook | rn = VFP_SREG_N(insn); |
2660 | b7bcbe95 | bellard | if (op == 15 && rn == 15) { |
2661 | b7bcbe95 | bellard | /* Double precision destination. */
|
2662 | 9ee6e8bb | pbrook | VFP_DREG_D(rd, insn); |
2663 | 9ee6e8bb | pbrook | } else {
|
2664 | 9ee6e8bb | pbrook | rd = VFP_SREG_D(insn); |
2665 | 9ee6e8bb | pbrook | } |
2666 | 9ee6e8bb | pbrook | rm = VFP_SREG_M(insn); |
2667 | b7bcbe95 | bellard | } |
2668 | b7bcbe95 | bellard | |
2669 | b7bcbe95 | bellard | veclen = env->vfp.vec_len; |
2670 | b7bcbe95 | bellard | if (op == 15 && rn > 3) |
2671 | b7bcbe95 | bellard | veclen = 0;
|
2672 | b7bcbe95 | bellard | |
2673 | b7bcbe95 | bellard | /* Shut up compiler warnings. */
|
2674 | b7bcbe95 | bellard | delta_m = 0;
|
2675 | b7bcbe95 | bellard | delta_d = 0;
|
2676 | b7bcbe95 | bellard | bank_mask = 0;
|
2677 | 3b46e624 | ths | |
2678 | b7bcbe95 | bellard | if (veclen > 0) { |
2679 | b7bcbe95 | bellard | if (dp)
|
2680 | b7bcbe95 | bellard | bank_mask = 0xc;
|
2681 | b7bcbe95 | bellard | else
|
2682 | b7bcbe95 | bellard | bank_mask = 0x18;
|
2683 | b7bcbe95 | bellard | |
2684 | b7bcbe95 | bellard | /* Figure out what type of vector operation this is. */
|
2685 | b7bcbe95 | bellard | if ((rd & bank_mask) == 0) { |
2686 | b7bcbe95 | bellard | /* scalar */
|
2687 | b7bcbe95 | bellard | veclen = 0;
|
2688 | b7bcbe95 | bellard | } else {
|
2689 | b7bcbe95 | bellard | if (dp)
|
2690 | b7bcbe95 | bellard | delta_d = (env->vfp.vec_stride >> 1) + 1; |
2691 | b7bcbe95 | bellard | else
|
2692 | b7bcbe95 | bellard | delta_d = env->vfp.vec_stride + 1;
|
2693 | b7bcbe95 | bellard | |
2694 | b7bcbe95 | bellard | if ((rm & bank_mask) == 0) { |
2695 | b7bcbe95 | bellard | /* mixed scalar/vector */
|
2696 | b7bcbe95 | bellard | delta_m = 0;
|
2697 | b7bcbe95 | bellard | } else {
|
2698 | b7bcbe95 | bellard | /* vector */
|
2699 | b7bcbe95 | bellard | delta_m = delta_d; |
2700 | b7bcbe95 | bellard | } |
2701 | b7bcbe95 | bellard | } |
2702 | b7bcbe95 | bellard | } |
2703 | b7bcbe95 | bellard | |
2704 | b7bcbe95 | bellard | /* Load the initial operands. */
|
2705 | b7bcbe95 | bellard | if (op == 15) { |
2706 | b7bcbe95 | bellard | switch (rn) {
|
2707 | b7bcbe95 | bellard | case 16: |
2708 | b7bcbe95 | bellard | case 17: |
2709 | b7bcbe95 | bellard | /* Integer source */
|
2710 | b7bcbe95 | bellard | gen_mov_F0_vreg(0, rm);
|
2711 | b7bcbe95 | bellard | break;
|
2712 | b7bcbe95 | bellard | case 8: |
2713 | b7bcbe95 | bellard | case 9: |
2714 | b7bcbe95 | bellard | /* Compare */
|
2715 | b7bcbe95 | bellard | gen_mov_F0_vreg(dp, rd); |
2716 | b7bcbe95 | bellard | gen_mov_F1_vreg(dp, rm); |
2717 | b7bcbe95 | bellard | break;
|
2718 | b7bcbe95 | bellard | case 10: |
2719 | b7bcbe95 | bellard | case 11: |
2720 | b7bcbe95 | bellard | /* Compare with zero */
|
2721 | b7bcbe95 | bellard | gen_mov_F0_vreg(dp, rd); |
2722 | b7bcbe95 | bellard | gen_vfp_F1_ld0(dp); |
2723 | b7bcbe95 | bellard | break;
|
2724 | 9ee6e8bb | pbrook | case 20: |
2725 | 9ee6e8bb | pbrook | case 21: |
2726 | 9ee6e8bb | pbrook | case 22: |
2727 | 9ee6e8bb | pbrook | case 23: |
2728 | 9ee6e8bb | pbrook | /* Source and destination the same. */
|
2729 | 9ee6e8bb | pbrook | gen_mov_F0_vreg(dp, rd); |
2730 | 9ee6e8bb | pbrook | break;
|
2731 | b7bcbe95 | bellard | default:
|
2732 | b7bcbe95 | bellard | /* One source operand. */
|
2733 | b7bcbe95 | bellard | gen_mov_F0_vreg(dp, rm); |
2734 | 9ee6e8bb | pbrook | break;
|
2735 | b7bcbe95 | bellard | } |
2736 | b7bcbe95 | bellard | } else {
|
2737 | b7bcbe95 | bellard | /* Two source operands. */
|
2738 | b7bcbe95 | bellard | gen_mov_F0_vreg(dp, rn); |
2739 | b7bcbe95 | bellard | gen_mov_F1_vreg(dp, rm); |
2740 | b7bcbe95 | bellard | } |
2741 | b7bcbe95 | bellard | |
2742 | b7bcbe95 | bellard | for (;;) {
|
2743 | b7bcbe95 | bellard | /* Perform the calculation. */
|
2744 | b7bcbe95 | bellard | switch (op) {
|
2745 | b7bcbe95 | bellard | case 0: /* mac: fd + (fn * fm) */ |
2746 | b7bcbe95 | bellard | gen_vfp_mul(dp); |
2747 | b7bcbe95 | bellard | gen_mov_F1_vreg(dp, rd); |
2748 | b7bcbe95 | bellard | gen_vfp_add(dp); |
2749 | b7bcbe95 | bellard | break;
|
2750 | b7bcbe95 | bellard | case 1: /* nmac: fd - (fn * fm) */ |
2751 | b7bcbe95 | bellard | gen_vfp_mul(dp); |
2752 | b7bcbe95 | bellard | gen_vfp_neg(dp); |
2753 | b7bcbe95 | bellard | gen_mov_F1_vreg(dp, rd); |
2754 | b7bcbe95 | bellard | gen_vfp_add(dp); |
2755 | b7bcbe95 | bellard | break;
|
2756 | b7bcbe95 | bellard | case 2: /* msc: -fd + (fn * fm) */ |
2757 | b7bcbe95 | bellard | gen_vfp_mul(dp); |
2758 | b7bcbe95 | bellard | gen_mov_F1_vreg(dp, rd); |
2759 | b7bcbe95 | bellard | gen_vfp_sub(dp); |
2760 | b7bcbe95 | bellard | break;
|
2761 | b7bcbe95 | bellard | case 3: /* nmsc: -fd - (fn * fm) */ |
2762 | b7bcbe95 | bellard | gen_vfp_mul(dp); |
2763 | b7bcbe95 | bellard | gen_mov_F1_vreg(dp, rd); |
2764 | b7bcbe95 | bellard | gen_vfp_add(dp); |
2765 | b7bcbe95 | bellard | gen_vfp_neg(dp); |
2766 | b7bcbe95 | bellard | break;
|
2767 | b7bcbe95 | bellard | case 4: /* mul: fn * fm */ |
2768 | b7bcbe95 | bellard | gen_vfp_mul(dp); |
2769 | b7bcbe95 | bellard | break;
|
2770 | b7bcbe95 | bellard | case 5: /* nmul: -(fn * fm) */ |
2771 | b7bcbe95 | bellard | gen_vfp_mul(dp); |
2772 | b7bcbe95 | bellard | gen_vfp_neg(dp); |
2773 | b7bcbe95 | bellard | break;
|
2774 | b7bcbe95 | bellard | case 6: /* add: fn + fm */ |
2775 | b7bcbe95 | bellard | gen_vfp_add(dp); |
2776 | b7bcbe95 | bellard | break;
|
2777 | b7bcbe95 | bellard | case 7: /* sub: fn - fm */ |
2778 | b7bcbe95 | bellard | gen_vfp_sub(dp); |
2779 | b7bcbe95 | bellard | break;
|
2780 | b7bcbe95 | bellard | case 8: /* div: fn / fm */ |
2781 | b7bcbe95 | bellard | gen_vfp_div(dp); |
2782 | b7bcbe95 | bellard | break;
|
2783 | 9ee6e8bb | pbrook | case 14: /* fconst */ |
2784 | 9ee6e8bb | pbrook | if (!arm_feature(env, ARM_FEATURE_VFP3))
|
2785 | 9ee6e8bb | pbrook | return 1; |
2786 | 9ee6e8bb | pbrook | |
2787 | 9ee6e8bb | pbrook | n = (insn << 12) & 0x80000000; |
2788 | 9ee6e8bb | pbrook | i = ((insn >> 12) & 0x70) | (insn & 0xf); |
2789 | 9ee6e8bb | pbrook | if (dp) {
|
2790 | 9ee6e8bb | pbrook | if (i & 0x40) |
2791 | 9ee6e8bb | pbrook | i |= 0x3f80;
|
2792 | 9ee6e8bb | pbrook | else
|
2793 | 9ee6e8bb | pbrook | i |= 0x4000;
|
2794 | 9ee6e8bb | pbrook | n |= i << 16;
|
2795 | 4373f3ce | pbrook | tcg_gen_movi_i64(cpu_F0d, ((uint64_t)n) << 32);
|
2796 | 9ee6e8bb | pbrook | } else {
|
2797 | 9ee6e8bb | pbrook | if (i & 0x40) |
2798 | 9ee6e8bb | pbrook | i |= 0x780;
|
2799 | 9ee6e8bb | pbrook | else
|
2800 | 9ee6e8bb | pbrook | i |= 0x800;
|
2801 | 9ee6e8bb | pbrook | n |= i << 19;
|
2802 | 4373f3ce | pbrook | tcg_gen_movi_i32(cpu_F0d, ((uint64_t)n) << 32);
|
2803 | 9ee6e8bb | pbrook | } |
2804 | 9ee6e8bb | pbrook | break;
|
2805 | b7bcbe95 | bellard | case 15: /* extension space */ |
2806 | b7bcbe95 | bellard | switch (rn) {
|
2807 | b7bcbe95 | bellard | case 0: /* cpy */ |
2808 | b7bcbe95 | bellard | /* no-op */
|
2809 | b7bcbe95 | bellard | break;
|
2810 | b7bcbe95 | bellard | case 1: /* abs */ |
2811 | b7bcbe95 | bellard | gen_vfp_abs(dp); |
2812 | b7bcbe95 | bellard | break;
|
2813 | b7bcbe95 | bellard | case 2: /* neg */ |
2814 | b7bcbe95 | bellard | gen_vfp_neg(dp); |
2815 | b7bcbe95 | bellard | break;
|
2816 | b7bcbe95 | bellard | case 3: /* sqrt */ |
2817 | b7bcbe95 | bellard | gen_vfp_sqrt(dp); |
2818 | b7bcbe95 | bellard | break;
|
2819 | b7bcbe95 | bellard | case 8: /* cmp */ |
2820 | b7bcbe95 | bellard | gen_vfp_cmp(dp); |
2821 | b7bcbe95 | bellard | break;
|
2822 | b7bcbe95 | bellard | case 9: /* cmpe */ |
2823 | b7bcbe95 | bellard | gen_vfp_cmpe(dp); |
2824 | b7bcbe95 | bellard | break;
|
2825 | b7bcbe95 | bellard | case 10: /* cmpz */ |
2826 | b7bcbe95 | bellard | gen_vfp_cmp(dp); |
2827 | b7bcbe95 | bellard | break;
|
2828 | b7bcbe95 | bellard | case 11: /* cmpez */ |
2829 | b7bcbe95 | bellard | gen_vfp_F1_ld0(dp); |
2830 | b7bcbe95 | bellard | gen_vfp_cmpe(dp); |
2831 | b7bcbe95 | bellard | break;
|
2832 | b7bcbe95 | bellard | case 15: /* single<->double conversion */ |
2833 | b7bcbe95 | bellard | if (dp)
|
2834 | 4373f3ce | pbrook | gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_env); |
2835 | b7bcbe95 | bellard | else
|
2836 | 4373f3ce | pbrook | gen_helper_vfp_fcvtds(cpu_F0d, cpu_F0s, cpu_env); |
2837 | b7bcbe95 | bellard | break;
|
2838 | b7bcbe95 | bellard | case 16: /* fuito */ |
2839 | b7bcbe95 | bellard | gen_vfp_uito(dp); |
2840 | b7bcbe95 | bellard | break;
|
2841 | b7bcbe95 | bellard | case 17: /* fsito */ |
2842 | b7bcbe95 | bellard | gen_vfp_sito(dp); |
2843 | b7bcbe95 | bellard | break;
|
2844 | 9ee6e8bb | pbrook | case 20: /* fshto */ |
2845 | 9ee6e8bb | pbrook | if (!arm_feature(env, ARM_FEATURE_VFP3))
|
2846 | 9ee6e8bb | pbrook | return 1; |
2847 | 9ee6e8bb | pbrook | gen_vfp_shto(dp, rm); |
2848 | 9ee6e8bb | pbrook | break;
|
2849 | 9ee6e8bb | pbrook | case 21: /* fslto */ |
2850 | 9ee6e8bb | pbrook | if (!arm_feature(env, ARM_FEATURE_VFP3))
|
2851 | 9ee6e8bb | pbrook | return 1; |
2852 | 9ee6e8bb | pbrook | gen_vfp_slto(dp, rm); |
2853 | 9ee6e8bb | pbrook | break;
|
2854 | 9ee6e8bb | pbrook | case 22: /* fuhto */ |
2855 | 9ee6e8bb | pbrook | if (!arm_feature(env, ARM_FEATURE_VFP3))
|
2856 | 9ee6e8bb | pbrook | return 1; |
2857 | 9ee6e8bb | pbrook | gen_vfp_uhto(dp, rm); |
2858 | 9ee6e8bb | pbrook | break;
|
2859 | 9ee6e8bb | pbrook | case 23: /* fulto */ |
2860 | 9ee6e8bb | pbrook | if (!arm_feature(env, ARM_FEATURE_VFP3))
|
2861 | 9ee6e8bb | pbrook | return 1; |
2862 | 9ee6e8bb | pbrook | gen_vfp_ulto(dp, rm); |
2863 | 9ee6e8bb | pbrook | break;
|
2864 | b7bcbe95 | bellard | case 24: /* ftoui */ |
2865 | b7bcbe95 | bellard | gen_vfp_toui(dp); |
2866 | b7bcbe95 | bellard | break;
|
2867 | b7bcbe95 | bellard | case 25: /* ftouiz */ |
2868 | b7bcbe95 | bellard | gen_vfp_touiz(dp); |
2869 | b7bcbe95 | bellard | break;
|
2870 | b7bcbe95 | bellard | case 26: /* ftosi */ |
2871 | b7bcbe95 | bellard | gen_vfp_tosi(dp); |
2872 | b7bcbe95 | bellard | break;
|
2873 | b7bcbe95 | bellard | case 27: /* ftosiz */ |
2874 | b7bcbe95 | bellard | gen_vfp_tosiz(dp); |
2875 | b7bcbe95 | bellard | break;
|
2876 | 9ee6e8bb | pbrook | case 28: /* ftosh */ |
2877 | 9ee6e8bb | pbrook | if (!arm_feature(env, ARM_FEATURE_VFP3))
|
2878 | 9ee6e8bb | pbrook | return 1; |
2879 | 9ee6e8bb | pbrook | gen_vfp_tosh(dp, rm); |
2880 | 9ee6e8bb | pbrook | break;
|
2881 | 9ee6e8bb | pbrook | case 29: /* ftosl */ |
2882 | 9ee6e8bb | pbrook | if (!arm_feature(env, ARM_FEATURE_VFP3))
|
2883 | 9ee6e8bb | pbrook | return 1; |
2884 | 9ee6e8bb | pbrook | gen_vfp_tosl(dp, rm); |
2885 | 9ee6e8bb | pbrook | break;
|
2886 | 9ee6e8bb | pbrook | case 30: /* ftouh */ |
2887 | 9ee6e8bb | pbrook | if (!arm_feature(env, ARM_FEATURE_VFP3))
|
2888 | 9ee6e8bb | pbrook | return 1; |
2889 | 9ee6e8bb | pbrook | gen_vfp_touh(dp, rm); |
2890 | 9ee6e8bb | pbrook | break;
|
2891 | 9ee6e8bb | pbrook | case 31: /* ftoul */ |
2892 | 9ee6e8bb | pbrook | if (!arm_feature(env, ARM_FEATURE_VFP3))
|
2893 | 9ee6e8bb | pbrook | return 1; |
2894 | 9ee6e8bb | pbrook | gen_vfp_toul(dp, rm); |
2895 | 9ee6e8bb | pbrook | break;
|
2896 | b7bcbe95 | bellard | default: /* undefined */ |
2897 | b7bcbe95 | bellard | printf ("rn:%d\n", rn);
|
2898 | b7bcbe95 | bellard | return 1; |
2899 | b7bcbe95 | bellard | } |
2900 | b7bcbe95 | bellard | break;
|
2901 | b7bcbe95 | bellard | default: /* undefined */ |
2902 | b7bcbe95 | bellard | printf ("op:%d\n", op);
|
2903 | b7bcbe95 | bellard | return 1; |
2904 | b7bcbe95 | bellard | } |
2905 | b7bcbe95 | bellard | |
2906 | b7bcbe95 | bellard | /* Write back the result. */
|
2907 | b7bcbe95 | bellard | if (op == 15 && (rn >= 8 && rn <= 11)) |
2908 | b7bcbe95 | bellard | ; /* Comparison, do nothing. */
|
2909 | b7bcbe95 | bellard | else if (op == 15 && rn > 17) |
2910 | b7bcbe95 | bellard | /* Integer result. */
|
2911 | b7bcbe95 | bellard | gen_mov_vreg_F0(0, rd);
|
2912 | b7bcbe95 | bellard | else if (op == 15 && rn == 15) |
2913 | b7bcbe95 | bellard | /* conversion */
|
2914 | b7bcbe95 | bellard | gen_mov_vreg_F0(!dp, rd); |
2915 | b7bcbe95 | bellard | else
|
2916 | b7bcbe95 | bellard | gen_mov_vreg_F0(dp, rd); |
2917 | b7bcbe95 | bellard | |
2918 | b7bcbe95 | bellard | /* break out of the loop if we have finished */
|
2919 | b7bcbe95 | bellard | if (veclen == 0) |
2920 | b7bcbe95 | bellard | break;
|
2921 | b7bcbe95 | bellard | |
2922 | b7bcbe95 | bellard | if (op == 15 && delta_m == 0) { |
2923 | b7bcbe95 | bellard | /* single source one-many */
|
2924 | b7bcbe95 | bellard | while (veclen--) {
|
2925 | b7bcbe95 | bellard | rd = ((rd + delta_d) & (bank_mask - 1))
|
2926 | b7bcbe95 | bellard | | (rd & bank_mask); |
2927 | b7bcbe95 | bellard | gen_mov_vreg_F0(dp, rd); |
2928 | b7bcbe95 | bellard | } |
2929 | b7bcbe95 | bellard | break;
|
2930 | b7bcbe95 | bellard | } |
2931 | b7bcbe95 | bellard | /* Setup the next operands. */
|
2932 | b7bcbe95 | bellard | veclen--; |
2933 | b7bcbe95 | bellard | rd = ((rd + delta_d) & (bank_mask - 1))
|
2934 | b7bcbe95 | bellard | | (rd & bank_mask); |
2935 | b7bcbe95 | bellard | |
2936 | b7bcbe95 | bellard | if (op == 15) { |
2937 | b7bcbe95 | bellard | /* One source operand. */
|
2938 | b7bcbe95 | bellard | rm = ((rm + delta_m) & (bank_mask - 1))
|
2939 | b7bcbe95 | bellard | | (rm & bank_mask); |
2940 | b7bcbe95 | bellard | gen_mov_F0_vreg(dp, rm); |
2941 | b7bcbe95 | bellard | } else {
|
2942 | b7bcbe95 | bellard | /* Two source operands. */
|
2943 | b7bcbe95 | bellard | rn = ((rn + delta_d) & (bank_mask - 1))
|
2944 | b7bcbe95 | bellard | | (rn & bank_mask); |
2945 | b7bcbe95 | bellard | gen_mov_F0_vreg(dp, rn); |
2946 | b7bcbe95 | bellard | if (delta_m) {
|
2947 | b7bcbe95 | bellard | rm = ((rm + delta_m) & (bank_mask - 1))
|
2948 | b7bcbe95 | bellard | | (rm & bank_mask); |
2949 | b7bcbe95 | bellard | gen_mov_F1_vreg(dp, rm); |
2950 | b7bcbe95 | bellard | } |
2951 | b7bcbe95 | bellard | } |
2952 | b7bcbe95 | bellard | } |
2953 | b7bcbe95 | bellard | } |
2954 | b7bcbe95 | bellard | break;
|
2955 | b7bcbe95 | bellard | case 0xc: |
2956 | b7bcbe95 | bellard | case 0xd: |
2957 | 9ee6e8bb | pbrook | if (dp && (insn & 0x03e00000) == 0x00400000) { |
2958 | b7bcbe95 | bellard | /* two-register transfer */
|
2959 | b7bcbe95 | bellard | rn = (insn >> 16) & 0xf; |
2960 | b7bcbe95 | bellard | rd = (insn >> 12) & 0xf; |
2961 | b7bcbe95 | bellard | if (dp) {
|
2962 | 9ee6e8bb | pbrook | VFP_DREG_M(rm, insn); |
2963 | 9ee6e8bb | pbrook | } else {
|
2964 | 9ee6e8bb | pbrook | rm = VFP_SREG_M(insn); |
2965 | 9ee6e8bb | pbrook | } |
2966 | b7bcbe95 | bellard | |
2967 | 18c9b560 | balrog | if (insn & ARM_CP_RW_BIT) {
|
2968 | b7bcbe95 | bellard | /* vfp->arm */
|
2969 | b7bcbe95 | bellard | if (dp) {
|
2970 | 4373f3ce | pbrook | gen_mov_F0_vreg(0, rm * 2); |
2971 | 4373f3ce | pbrook | tmp = gen_vfp_mrs(); |
2972 | 4373f3ce | pbrook | store_reg(s, rd, tmp); |
2973 | 4373f3ce | pbrook | gen_mov_F0_vreg(0, rm * 2 + 1); |
2974 | 4373f3ce | pbrook | tmp = gen_vfp_mrs(); |
2975 | 4373f3ce | pbrook | store_reg(s, rn, tmp); |
2976 | b7bcbe95 | bellard | } else {
|
2977 | b7bcbe95 | bellard | gen_mov_F0_vreg(0, rm);
|
2978 | 4373f3ce | pbrook | tmp = gen_vfp_mrs(); |
2979 | 4373f3ce | pbrook | store_reg(s, rn, tmp); |
2980 | b7bcbe95 | bellard | gen_mov_F0_vreg(0, rm + 1); |
2981 | 4373f3ce | pbrook | tmp = gen_vfp_mrs(); |
2982 | 4373f3ce | pbrook | store_reg(s, rd, tmp); |
2983 | b7bcbe95 | bellard | } |
2984 | b7bcbe95 | bellard | } else {
|
2985 | b7bcbe95 | bellard | /* arm->vfp */
|
2986 | b7bcbe95 | bellard | if (dp) {
|
2987 | 4373f3ce | pbrook | tmp = load_reg(s, rd); |
2988 | 4373f3ce | pbrook | gen_vfp_msr(tmp); |
2989 | 4373f3ce | pbrook | gen_mov_vreg_F0(0, rm * 2); |
2990 | 4373f3ce | pbrook | tmp = load_reg(s, rn); |
2991 | 4373f3ce | pbrook | gen_vfp_msr(tmp); |
2992 | 4373f3ce | pbrook | gen_mov_vreg_F0(0, rm * 2 + 1); |
2993 | b7bcbe95 | bellard | } else {
|
2994 | 4373f3ce | pbrook | tmp = load_reg(s, rn); |
2995 | 4373f3ce | pbrook | gen_vfp_msr(tmp); |
2996 | b7bcbe95 | bellard | gen_mov_vreg_F0(0, rm);
|
2997 | 4373f3ce | pbrook | tmp = load_reg(s, rd); |
2998 | 4373f3ce | pbrook | gen_vfp_msr(tmp); |
2999 | b7bcbe95 | bellard | gen_mov_vreg_F0(0, rm + 1); |
3000 | b7bcbe95 | bellard | } |
3001 | b7bcbe95 | bellard | } |
3002 | b7bcbe95 | bellard | } else {
|
3003 | b7bcbe95 | bellard | /* Load/store */
|
3004 | b7bcbe95 | bellard | rn = (insn >> 16) & 0xf; |
3005 | b7bcbe95 | bellard | if (dp)
|
3006 | 9ee6e8bb | pbrook | VFP_DREG_D(rd, insn); |
3007 | b7bcbe95 | bellard | else
|
3008 | 9ee6e8bb | pbrook | rd = VFP_SREG_D(insn); |
3009 | 9ee6e8bb | pbrook | if (s->thumb && rn == 15) { |
3010 | 9ee6e8bb | pbrook | gen_op_movl_T1_im(s->pc & ~2);
|
3011 | 9ee6e8bb | pbrook | } else {
|
3012 | 9ee6e8bb | pbrook | gen_movl_T1_reg(s, rn); |
3013 | 9ee6e8bb | pbrook | } |
3014 | b7bcbe95 | bellard | if ((insn & 0x01200000) == 0x01000000) { |
3015 | b7bcbe95 | bellard | /* Single load/store */
|
3016 | b7bcbe95 | bellard | offset = (insn & 0xff) << 2; |
3017 | b7bcbe95 | bellard | if ((insn & (1 << 23)) == 0) |
3018 | b7bcbe95 | bellard | offset = -offset; |
3019 | b7bcbe95 | bellard | gen_op_addl_T1_im(offset); |
3020 | b7bcbe95 | bellard | if (insn & (1 << 20)) { |
3021 | b5ff1b31 | bellard | gen_vfp_ld(s, dp); |
3022 | b7bcbe95 | bellard | gen_mov_vreg_F0(dp, rd); |
3023 | b7bcbe95 | bellard | } else {
|
3024 | b7bcbe95 | bellard | gen_mov_F0_vreg(dp, rd); |
3025 | b5ff1b31 | bellard | gen_vfp_st(s, dp); |
3026 | b7bcbe95 | bellard | } |
3027 | b7bcbe95 | bellard | } else {
|
3028 | b7bcbe95 | bellard | /* load/store multiple */
|
3029 | b7bcbe95 | bellard | if (dp)
|
3030 | b7bcbe95 | bellard | n = (insn >> 1) & 0x7f; |
3031 | b7bcbe95 | bellard | else
|
3032 | b7bcbe95 | bellard | n = insn & 0xff;
|
3033 | b7bcbe95 | bellard | |
3034 | b7bcbe95 | bellard | if (insn & (1 << 24)) /* pre-decrement */ |
3035 | b7bcbe95 | bellard | gen_op_addl_T1_im(-((insn & 0xff) << 2)); |
3036 | b7bcbe95 | bellard | |
3037 | b7bcbe95 | bellard | if (dp)
|
3038 | b7bcbe95 | bellard | offset = 8;
|
3039 | b7bcbe95 | bellard | else
|
3040 | b7bcbe95 | bellard | offset = 4;
|
3041 | b7bcbe95 | bellard | for (i = 0; i < n; i++) { |
3042 | 18c9b560 | balrog | if (insn & ARM_CP_RW_BIT) {
|
3043 | b7bcbe95 | bellard | /* load */
|
3044 | b5ff1b31 | bellard | gen_vfp_ld(s, dp); |
3045 | b7bcbe95 | bellard | gen_mov_vreg_F0(dp, rd + i); |
3046 | b7bcbe95 | bellard | } else {
|
3047 | b7bcbe95 | bellard | /* store */
|
3048 | b7bcbe95 | bellard | gen_mov_F0_vreg(dp, rd + i); |
3049 | b5ff1b31 | bellard | gen_vfp_st(s, dp); |
3050 | b7bcbe95 | bellard | } |
3051 | b7bcbe95 | bellard | gen_op_addl_T1_im(offset); |
3052 | b7bcbe95 | bellard | } |
3053 | b7bcbe95 | bellard | if (insn & (1 << 21)) { |
3054 | b7bcbe95 | bellard | /* writeback */
|
3055 | b7bcbe95 | bellard | if (insn & (1 << 24)) |
3056 | b7bcbe95 | bellard | offset = -offset * n; |
3057 | b7bcbe95 | bellard | else if (dp && (insn & 1)) |
3058 | b7bcbe95 | bellard | offset = 4;
|
3059 | b7bcbe95 | bellard | else
|
3060 | b7bcbe95 | bellard | offset = 0;
|
3061 | b7bcbe95 | bellard | |
3062 | b7bcbe95 | bellard | if (offset != 0) |
3063 | b7bcbe95 | bellard | gen_op_addl_T1_im(offset); |
3064 | b7bcbe95 | bellard | gen_movl_reg_T1(s, rn); |
3065 | b7bcbe95 | bellard | } |
3066 | b7bcbe95 | bellard | } |
3067 | b7bcbe95 | bellard | } |
3068 | b7bcbe95 | bellard | break;
|
3069 | b7bcbe95 | bellard | default:
|
3070 | b7bcbe95 | bellard | /* Should never happen. */
|
3071 | b7bcbe95 | bellard | return 1; |
3072 | b7bcbe95 | bellard | } |
3073 | b7bcbe95 | bellard | return 0; |
3074 | b7bcbe95 | bellard | } |
3075 | b7bcbe95 | bellard | |
3076 | 6e256c93 | bellard | static inline void gen_goto_tb(DisasContext *s, int n, uint32_t dest) |
3077 | c53be334 | bellard | { |
3078 | 6e256c93 | bellard | TranslationBlock *tb; |
3079 | 6e256c93 | bellard | |
3080 | 6e256c93 | bellard | tb = s->tb; |
3081 | 6e256c93 | bellard | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
|
3082 | 57fec1fe | bellard | tcg_gen_goto_tb(n); |
3083 | 8984bd2e | pbrook | gen_set_pc_im(dest); |
3084 | 57fec1fe | bellard | tcg_gen_exit_tb((long)tb + n);
|
3085 | 6e256c93 | bellard | } else {
|
3086 | 8984bd2e | pbrook | gen_set_pc_im(dest); |
3087 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3088 | 6e256c93 | bellard | } |
3089 | c53be334 | bellard | } |
3090 | c53be334 | bellard | |
3091 | 8aaca4c0 | bellard | static inline void gen_jmp (DisasContext *s, uint32_t dest) |
3092 | 8aaca4c0 | bellard | { |
3093 | 8aaca4c0 | bellard | if (__builtin_expect(s->singlestep_enabled, 0)) { |
3094 | 8aaca4c0 | bellard | /* An indirect jump so that we still trigger the debug exception. */
|
3095 | 5899f386 | bellard | if (s->thumb)
|
3096 | d9ba4830 | pbrook | dest |= 1;
|
3097 | d9ba4830 | pbrook | gen_bx_im(s, dest); |
3098 | 8aaca4c0 | bellard | } else {
|
3099 | 6e256c93 | bellard | gen_goto_tb(s, 0, dest);
|
3100 | 8aaca4c0 | bellard | s->is_jmp = DISAS_TB_JUMP; |
3101 | 8aaca4c0 | bellard | } |
3102 | 8aaca4c0 | bellard | } |
3103 | 8aaca4c0 | bellard | |
3104 | d9ba4830 | pbrook | static inline void gen_mulxy(TCGv t0, TCGv t1, int x, int y) |
3105 | b5ff1b31 | bellard | { |
3106 | ee097184 | bellard | if (x)
|
3107 | d9ba4830 | pbrook | tcg_gen_sari_i32(t0, t0, 16);
|
3108 | b5ff1b31 | bellard | else
|
3109 | d9ba4830 | pbrook | gen_sxth(t0); |
3110 | ee097184 | bellard | if (y)
|
3111 | d9ba4830 | pbrook | tcg_gen_sari_i32(t1, t1, 16);
|
3112 | b5ff1b31 | bellard | else
|
3113 | d9ba4830 | pbrook | gen_sxth(t1); |
3114 | d9ba4830 | pbrook | tcg_gen_mul_i32(t0, t0, t1); |
3115 | b5ff1b31 | bellard | } |
3116 | b5ff1b31 | bellard | |
3117 | b5ff1b31 | bellard | /* Return the mask of PSR bits set by a MSR instruction. */
|
3118 | 9ee6e8bb | pbrook | static uint32_t msr_mask(CPUState *env, DisasContext *s, int flags, int spsr) { |
3119 | b5ff1b31 | bellard | uint32_t mask; |
3120 | b5ff1b31 | bellard | |
3121 | b5ff1b31 | bellard | mask = 0;
|
3122 | b5ff1b31 | bellard | if (flags & (1 << 0)) |
3123 | b5ff1b31 | bellard | mask |= 0xff;
|
3124 | b5ff1b31 | bellard | if (flags & (1 << 1)) |
3125 | b5ff1b31 | bellard | mask |= 0xff00;
|
3126 | b5ff1b31 | bellard | if (flags & (1 << 2)) |
3127 | b5ff1b31 | bellard | mask |= 0xff0000;
|
3128 | b5ff1b31 | bellard | if (flags & (1 << 3)) |
3129 | b5ff1b31 | bellard | mask |= 0xff000000;
|
3130 | 9ee6e8bb | pbrook | |
3131 | 2ae23e75 | pbrook | /* Mask out undefined bits. */
|
3132 | 9ee6e8bb | pbrook | mask &= ~CPSR_RESERVED; |
3133 | 9ee6e8bb | pbrook | if (!arm_feature(env, ARM_FEATURE_V6))
|
3134 | e160c51c | pbrook | mask &= ~(CPSR_E | CPSR_GE); |
3135 | 9ee6e8bb | pbrook | if (!arm_feature(env, ARM_FEATURE_THUMB2))
|
3136 | e160c51c | pbrook | mask &= ~CPSR_IT; |
3137 | 9ee6e8bb | pbrook | /* Mask out execution state bits. */
|
3138 | 2ae23e75 | pbrook | if (!spsr)
|
3139 | e160c51c | pbrook | mask &= ~CPSR_EXEC; |
3140 | b5ff1b31 | bellard | /* Mask out privileged bits. */
|
3141 | b5ff1b31 | bellard | if (IS_USER(s))
|
3142 | 9ee6e8bb | pbrook | mask &= CPSR_USER; |
3143 | b5ff1b31 | bellard | return mask;
|
3144 | b5ff1b31 | bellard | } |
3145 | b5ff1b31 | bellard | |
3146 | b5ff1b31 | bellard | /* Returns nonzero if access to the PSR is not permitted. */
|
3147 | b5ff1b31 | bellard | static int gen_set_psr_T0(DisasContext *s, uint32_t mask, int spsr) |
3148 | b5ff1b31 | bellard | { |
3149 | d9ba4830 | pbrook | TCGv tmp; |
3150 | b5ff1b31 | bellard | if (spsr) {
|
3151 | b5ff1b31 | bellard | /* ??? This is also undefined in system mode. */
|
3152 | b5ff1b31 | bellard | if (IS_USER(s))
|
3153 | b5ff1b31 | bellard | return 1; |
3154 | d9ba4830 | pbrook | |
3155 | d9ba4830 | pbrook | tmp = load_cpu_field(spsr); |
3156 | d9ba4830 | pbrook | tcg_gen_andi_i32(tmp, tmp, ~mask); |
3157 | d9ba4830 | pbrook | tcg_gen_andi_i32(cpu_T[0], cpu_T[0], mask); |
3158 | d9ba4830 | pbrook | tcg_gen_or_i32(tmp, tmp, cpu_T[0]);
|
3159 | d9ba4830 | pbrook | store_cpu_field(tmp, spsr); |
3160 | b5ff1b31 | bellard | } else {
|
3161 | d9ba4830 | pbrook | gen_set_cpsr(cpu_T[0], mask);
|
3162 | b5ff1b31 | bellard | } |
3163 | b5ff1b31 | bellard | gen_lookup_tb(s); |
3164 | b5ff1b31 | bellard | return 0; |
3165 | b5ff1b31 | bellard | } |
3166 | b5ff1b31 | bellard | |
3167 | 9ee6e8bb | pbrook | /* Generate an old-style exception return. */
|
3168 | b5ff1b31 | bellard | static void gen_exception_return(DisasContext *s) |
3169 | b5ff1b31 | bellard | { |
3170 | d9ba4830 | pbrook | TCGv tmp; |
3171 | b26eefb6 | pbrook | gen_set_pc_T0(); |
3172 | d9ba4830 | pbrook | tmp = load_cpu_field(spsr); |
3173 | d9ba4830 | pbrook | gen_set_cpsr(tmp, 0xffffffff);
|
3174 | d9ba4830 | pbrook | dead_tmp(tmp); |
3175 | b5ff1b31 | bellard | s->is_jmp = DISAS_UPDATE; |
3176 | b5ff1b31 | bellard | } |
3177 | b5ff1b31 | bellard | |
3178 | b0109805 | pbrook | /* Generate a v6 exception return. Marks both values as dead. */
|
3179 | b0109805 | pbrook | static void gen_rfe(DisasContext *s, TCGv pc, TCGv cpsr) |
3180 | 2c0262af | bellard | { |
3181 | b0109805 | pbrook | gen_set_cpsr(cpsr, 0xffffffff);
|
3182 | b0109805 | pbrook | dead_tmp(cpsr); |
3183 | b0109805 | pbrook | store_reg(s, 15, pc);
|
3184 | 9ee6e8bb | pbrook | s->is_jmp = DISAS_UPDATE; |
3185 | 9ee6e8bb | pbrook | } |
3186 | 3b46e624 | ths | |
3187 | 9ee6e8bb | pbrook | static inline void |
3188 | 9ee6e8bb | pbrook | gen_set_condexec (DisasContext *s) |
3189 | 9ee6e8bb | pbrook | { |
3190 | 9ee6e8bb | pbrook | if (s->condexec_mask) {
|
3191 | 8f01245e | pbrook | uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1); |
3192 | 8f01245e | pbrook | TCGv tmp = new_tmp(); |
3193 | 8f01245e | pbrook | tcg_gen_movi_i32(tmp, val); |
3194 | d9ba4830 | pbrook | store_cpu_field(tmp, condexec_bits); |
3195 | 9ee6e8bb | pbrook | } |
3196 | 9ee6e8bb | pbrook | } |
3197 | 3b46e624 | ths | |
3198 | 9ee6e8bb | pbrook | static void gen_nop_hint(DisasContext *s, int val) |
3199 | 9ee6e8bb | pbrook | { |
3200 | 9ee6e8bb | pbrook | switch (val) {
|
3201 | 9ee6e8bb | pbrook | case 3: /* wfi */ |
3202 | 8984bd2e | pbrook | gen_set_pc_im(s->pc); |
3203 | 9ee6e8bb | pbrook | s->is_jmp = DISAS_WFI; |
3204 | 9ee6e8bb | pbrook | break;
|
3205 | 9ee6e8bb | pbrook | case 2: /* wfe */ |
3206 | 9ee6e8bb | pbrook | case 4: /* sev */ |
3207 | 9ee6e8bb | pbrook | /* TODO: Implement SEV and WFE. May help SMP performance. */
|
3208 | 9ee6e8bb | pbrook | default: /* nop */ |
3209 | 9ee6e8bb | pbrook | break;
|
3210 | 9ee6e8bb | pbrook | } |
3211 | 9ee6e8bb | pbrook | } |
3212 | 99c475ab | bellard | |
3213 | 9ee6e8bb | pbrook | /* Neon shift by constant. The actual ops are the same as used for variable
|
3214 | 9ee6e8bb | pbrook | shifts. [OP][U][SIZE] */
|
3215 | 9ee6e8bb | pbrook | static GenOpFunc *gen_neon_shift_im[8][2][4] = { |
3216 | 9ee6e8bb | pbrook | { /* 0 */ /* VSHR */ |
3217 | 9ee6e8bb | pbrook | { |
3218 | 9ee6e8bb | pbrook | gen_op_neon_shl_u8, |
3219 | 9ee6e8bb | pbrook | gen_op_neon_shl_u16, |
3220 | 9ee6e8bb | pbrook | gen_op_neon_shl_u32, |
3221 | 9ee6e8bb | pbrook | gen_op_neon_shl_u64 |
3222 | 9ee6e8bb | pbrook | }, { |
3223 | 9ee6e8bb | pbrook | gen_op_neon_shl_s8, |
3224 | 9ee6e8bb | pbrook | gen_op_neon_shl_s16, |
3225 | 9ee6e8bb | pbrook | gen_op_neon_shl_s32, |
3226 | 9ee6e8bb | pbrook | gen_op_neon_shl_s64 |
3227 | 9ee6e8bb | pbrook | } |
3228 | 9ee6e8bb | pbrook | }, { /* 1 */ /* VSRA */ |
3229 | 9ee6e8bb | pbrook | { |
3230 | 9ee6e8bb | pbrook | gen_op_neon_shl_u8, |
3231 | 9ee6e8bb | pbrook | gen_op_neon_shl_u16, |
3232 | 9ee6e8bb | pbrook | gen_op_neon_shl_u32, |
3233 | 9ee6e8bb | pbrook | gen_op_neon_shl_u64 |
3234 | 9ee6e8bb | pbrook | }, { |
3235 | 9ee6e8bb | pbrook | gen_op_neon_shl_s8, |
3236 | 9ee6e8bb | pbrook | gen_op_neon_shl_s16, |
3237 | 9ee6e8bb | pbrook | gen_op_neon_shl_s32, |
3238 | 9ee6e8bb | pbrook | gen_op_neon_shl_s64 |
3239 | 9ee6e8bb | pbrook | } |
3240 | 9ee6e8bb | pbrook | }, { /* 2 */ /* VRSHR */ |
3241 | 9ee6e8bb | pbrook | { |
3242 | 9ee6e8bb | pbrook | gen_op_neon_rshl_u8, |
3243 | 9ee6e8bb | pbrook | gen_op_neon_rshl_u16, |
3244 | 9ee6e8bb | pbrook | gen_op_neon_rshl_u32, |
3245 | 9ee6e8bb | pbrook | gen_op_neon_rshl_u64 |
3246 | 9ee6e8bb | pbrook | }, { |
3247 | 9ee6e8bb | pbrook | gen_op_neon_rshl_s8, |
3248 | 9ee6e8bb | pbrook | gen_op_neon_rshl_s16, |
3249 | 9ee6e8bb | pbrook | gen_op_neon_rshl_s32, |
3250 | 9ee6e8bb | pbrook | gen_op_neon_rshl_s64 |
3251 | 9ee6e8bb | pbrook | } |
3252 | 9ee6e8bb | pbrook | }, { /* 3 */ /* VRSRA */ |
3253 | 9ee6e8bb | pbrook | { |
3254 | 9ee6e8bb | pbrook | gen_op_neon_rshl_u8, |
3255 | 9ee6e8bb | pbrook | gen_op_neon_rshl_u16, |
3256 | 9ee6e8bb | pbrook | gen_op_neon_rshl_u32, |
3257 | 9ee6e8bb | pbrook | gen_op_neon_rshl_u64 |
3258 | 9ee6e8bb | pbrook | }, { |
3259 | 9ee6e8bb | pbrook | gen_op_neon_rshl_s8, |
3260 | 9ee6e8bb | pbrook | gen_op_neon_rshl_s16, |
3261 | 9ee6e8bb | pbrook | gen_op_neon_rshl_s32, |
3262 | 9ee6e8bb | pbrook | gen_op_neon_rshl_s64 |
3263 | 9ee6e8bb | pbrook | } |
3264 | 9ee6e8bb | pbrook | }, { /* 4 */
|
3265 | 9ee6e8bb | pbrook | { |
3266 | 9ee6e8bb | pbrook | NULL, NULL, NULL, NULL |
3267 | 9ee6e8bb | pbrook | }, { /* VSRI */
|
3268 | 9ee6e8bb | pbrook | gen_op_neon_shl_u8, |
3269 | 9ee6e8bb | pbrook | gen_op_neon_shl_u16, |
3270 | 9ee6e8bb | pbrook | gen_op_neon_shl_u32, |
3271 | 9ee6e8bb | pbrook | gen_op_neon_shl_u64, |
3272 | 9ee6e8bb | pbrook | } |
3273 | 9ee6e8bb | pbrook | }, { /* 5 */
|
3274 | 9ee6e8bb | pbrook | { /* VSHL */
|
3275 | 9ee6e8bb | pbrook | gen_op_neon_shl_u8, |
3276 | 9ee6e8bb | pbrook | gen_op_neon_shl_u16, |
3277 | 9ee6e8bb | pbrook | gen_op_neon_shl_u32, |
3278 | 9ee6e8bb | pbrook | gen_op_neon_shl_u64, |
3279 | 9ee6e8bb | pbrook | }, { /* VSLI */
|
3280 | 9ee6e8bb | pbrook | gen_op_neon_shl_u8, |
3281 | 9ee6e8bb | pbrook | gen_op_neon_shl_u16, |
3282 | 9ee6e8bb | pbrook | gen_op_neon_shl_u32, |
3283 | 9ee6e8bb | pbrook | gen_op_neon_shl_u64, |
3284 | 9ee6e8bb | pbrook | } |
3285 | 9ee6e8bb | pbrook | }, { /* 6 */ /* VQSHL */ |
3286 | 9ee6e8bb | pbrook | { |
3287 | 9ee6e8bb | pbrook | gen_op_neon_qshl_u8, |
3288 | 9ee6e8bb | pbrook | gen_op_neon_qshl_u16, |
3289 | 9ee6e8bb | pbrook | gen_op_neon_qshl_u32, |
3290 | 9ee6e8bb | pbrook | gen_op_neon_qshl_u64 |
3291 | 9ee6e8bb | pbrook | }, { |
3292 | 9ee6e8bb | pbrook | gen_op_neon_qshl_s8, |
3293 | 9ee6e8bb | pbrook | gen_op_neon_qshl_s16, |
3294 | 9ee6e8bb | pbrook | gen_op_neon_qshl_s32, |
3295 | 9ee6e8bb | pbrook | gen_op_neon_qshl_s64 |
3296 | 9ee6e8bb | pbrook | } |
3297 | 9ee6e8bb | pbrook | }, { /* 7 */ /* VQSHLU */ |
3298 | 9ee6e8bb | pbrook | { |
3299 | 9ee6e8bb | pbrook | gen_op_neon_qshl_u8, |
3300 | 9ee6e8bb | pbrook | gen_op_neon_qshl_u16, |
3301 | 9ee6e8bb | pbrook | gen_op_neon_qshl_u32, |
3302 | 9ee6e8bb | pbrook | gen_op_neon_qshl_u64 |
3303 | 9ee6e8bb | pbrook | }, { |
3304 | 9ee6e8bb | pbrook | gen_op_neon_qshl_u8, |
3305 | 9ee6e8bb | pbrook | gen_op_neon_qshl_u16, |
3306 | 9ee6e8bb | pbrook | gen_op_neon_qshl_u32, |
3307 | 9ee6e8bb | pbrook | gen_op_neon_qshl_u64 |
3308 | 9ee6e8bb | pbrook | } |
3309 | 99c475ab | bellard | } |
3310 | 9ee6e8bb | pbrook | }; |
3311 | 9ee6e8bb | pbrook | |
3312 | 9ee6e8bb | pbrook | /* [R][U][size - 1] */
|
3313 | 9ee6e8bb | pbrook | static GenOpFunc *gen_neon_shift_im_narrow[2][2][3] = { |
3314 | 9ee6e8bb | pbrook | { |
3315 | 9ee6e8bb | pbrook | { |
3316 | 9ee6e8bb | pbrook | gen_op_neon_shl_u16, |
3317 | 9ee6e8bb | pbrook | gen_op_neon_shl_u32, |
3318 | 9ee6e8bb | pbrook | gen_op_neon_shl_u64 |
3319 | 9ee6e8bb | pbrook | }, { |
3320 | 9ee6e8bb | pbrook | gen_op_neon_shl_s16, |
3321 | 9ee6e8bb | pbrook | gen_op_neon_shl_s32, |
3322 | 9ee6e8bb | pbrook | gen_op_neon_shl_s64 |
3323 | 9ee6e8bb | pbrook | } |
3324 | 9ee6e8bb | pbrook | }, { |
3325 | 9ee6e8bb | pbrook | { |
3326 | 9ee6e8bb | pbrook | gen_op_neon_rshl_u16, |
3327 | 9ee6e8bb | pbrook | gen_op_neon_rshl_u32, |
3328 | 9ee6e8bb | pbrook | gen_op_neon_rshl_u64 |
3329 | 9ee6e8bb | pbrook | }, { |
3330 | 9ee6e8bb | pbrook | gen_op_neon_rshl_s16, |
3331 | 9ee6e8bb | pbrook | gen_op_neon_rshl_s32, |
3332 | 9ee6e8bb | pbrook | gen_op_neon_rshl_s64 |
3333 | 9ee6e8bb | pbrook | } |
3334 | 2c0262af | bellard | } |
3335 | 9ee6e8bb | pbrook | }; |
3336 | 99c475ab | bellard | |
3337 | 9ee6e8bb | pbrook | static inline void |
3338 | 9ee6e8bb | pbrook | gen_op_neon_narrow_u32 () |
3339 | 9ee6e8bb | pbrook | { |
3340 | 9ee6e8bb | pbrook | /* No-op. */
|
3341 | 9ee6e8bb | pbrook | } |
3342 | 9ee6e8bb | pbrook | |
3343 | 9ee6e8bb | pbrook | static GenOpFunc *gen_neon_narrow[3] = { |
3344 | 9ee6e8bb | pbrook | gen_op_neon_narrow_u8, |
3345 | 9ee6e8bb | pbrook | gen_op_neon_narrow_u16, |
3346 | 9ee6e8bb | pbrook | gen_op_neon_narrow_u32 |
3347 | 9ee6e8bb | pbrook | }; |
3348 | 9ee6e8bb | pbrook | |
3349 | 9ee6e8bb | pbrook | static GenOpFunc *gen_neon_narrow_satu[3] = { |
3350 | 9ee6e8bb | pbrook | gen_op_neon_narrow_sat_u8, |
3351 | 9ee6e8bb | pbrook | gen_op_neon_narrow_sat_u16, |
3352 | 9ee6e8bb | pbrook | gen_op_neon_narrow_sat_u32 |
3353 | 9ee6e8bb | pbrook | }; |
3354 | 9ee6e8bb | pbrook | |
3355 | 9ee6e8bb | pbrook | static GenOpFunc *gen_neon_narrow_sats[3] = { |
3356 | 9ee6e8bb | pbrook | gen_op_neon_narrow_sat_s8, |
3357 | 9ee6e8bb | pbrook | gen_op_neon_narrow_sat_s16, |
3358 | 9ee6e8bb | pbrook | gen_op_neon_narrow_sat_s32 |
3359 | 9ee6e8bb | pbrook | }; |
3360 | 9ee6e8bb | pbrook | |
3361 | 9ee6e8bb | pbrook | static inline int gen_neon_add(int size) |
3362 | 9ee6e8bb | pbrook | { |
3363 | 9ee6e8bb | pbrook | switch (size) {
|
3364 | 9ee6e8bb | pbrook | case 0: gen_op_neon_add_u8(); break; |
3365 | 9ee6e8bb | pbrook | case 1: gen_op_neon_add_u16(); break; |
3366 | 9ee6e8bb | pbrook | case 2: gen_op_addl_T0_T1(); break; |
3367 | 9ee6e8bb | pbrook | default: return 1; |
3368 | 9ee6e8bb | pbrook | } |
3369 | 9ee6e8bb | pbrook | return 0; |
3370 | 9ee6e8bb | pbrook | } |
3371 | 9ee6e8bb | pbrook | |
3372 | 9ee6e8bb | pbrook | /* 32-bit pairwise ops end up the same as the elementsise versions. */
|
3373 | 9ee6e8bb | pbrook | #define gen_op_neon_pmax_s32 gen_op_neon_max_s32
|
3374 | 9ee6e8bb | pbrook | #define gen_op_neon_pmax_u32 gen_op_neon_max_u32
|
3375 | 9ee6e8bb | pbrook | #define gen_op_neon_pmin_s32 gen_op_neon_min_s32
|
3376 | 9ee6e8bb | pbrook | #define gen_op_neon_pmin_u32 gen_op_neon_min_u32
|
3377 | 9ee6e8bb | pbrook | |
3378 | 9ee6e8bb | pbrook | #define GEN_NEON_INTEGER_OP(name) do { \ |
3379 | 9ee6e8bb | pbrook | switch ((size << 1) | u) { \ |
3380 | 9ee6e8bb | pbrook | case 0: gen_op_neon_##name##_s8(); break; \ |
3381 | 9ee6e8bb | pbrook | case 1: gen_op_neon_##name##_u8(); break; \ |
3382 | 9ee6e8bb | pbrook | case 2: gen_op_neon_##name##_s16(); break; \ |
3383 | 9ee6e8bb | pbrook | case 3: gen_op_neon_##name##_u16(); break; \ |
3384 | 9ee6e8bb | pbrook | case 4: gen_op_neon_##name##_s32(); break; \ |
3385 | 9ee6e8bb | pbrook | case 5: gen_op_neon_##name##_u32(); break; \ |
3386 | 9ee6e8bb | pbrook | default: return 1; \ |
3387 | 9ee6e8bb | pbrook | }} while (0) |
3388 | 9ee6e8bb | pbrook | |
3389 | 9ee6e8bb | pbrook | static inline void |
3390 | 9ee6e8bb | pbrook | gen_neon_movl_scratch_T0(int scratch)
|
3391 | 9ee6e8bb | pbrook | { |
3392 | 9ee6e8bb | pbrook | uint32_t offset; |
3393 | 9ee6e8bb | pbrook | |
3394 | 9ee6e8bb | pbrook | offset = offsetof(CPUARMState, vfp.scratch[scratch]); |
3395 | 9ee6e8bb | pbrook | gen_op_neon_setreg_T0(offset); |
3396 | 9ee6e8bb | pbrook | } |
3397 | 9ee6e8bb | pbrook | |
3398 | 9ee6e8bb | pbrook | static inline void |
3399 | 9ee6e8bb | pbrook | gen_neon_movl_scratch_T1(int scratch)
|
3400 | 9ee6e8bb | pbrook | { |
3401 | 9ee6e8bb | pbrook | uint32_t offset; |
3402 | 9ee6e8bb | pbrook | |
3403 | 9ee6e8bb | pbrook | offset = offsetof(CPUARMState, vfp.scratch[scratch]); |
3404 | 9ee6e8bb | pbrook | gen_op_neon_setreg_T1(offset); |
3405 | 9ee6e8bb | pbrook | } |
3406 | 9ee6e8bb | pbrook | |
3407 | 9ee6e8bb | pbrook | static inline void |
3408 | 9ee6e8bb | pbrook | gen_neon_movl_T0_scratch(int scratch)
|
3409 | 9ee6e8bb | pbrook | { |
3410 | 9ee6e8bb | pbrook | uint32_t offset; |
3411 | 9ee6e8bb | pbrook | |
3412 | 9ee6e8bb | pbrook | offset = offsetof(CPUARMState, vfp.scratch[scratch]); |
3413 | 9ee6e8bb | pbrook | gen_op_neon_getreg_T0(offset); |
3414 | 9ee6e8bb | pbrook | } |
3415 | 9ee6e8bb | pbrook | |
3416 | 9ee6e8bb | pbrook | static inline void |
3417 | 9ee6e8bb | pbrook | gen_neon_movl_T1_scratch(int scratch)
|
3418 | 9ee6e8bb | pbrook | { |
3419 | 9ee6e8bb | pbrook | uint32_t offset; |
3420 | 9ee6e8bb | pbrook | |
3421 | 9ee6e8bb | pbrook | offset = offsetof(CPUARMState, vfp.scratch[scratch]); |
3422 | 9ee6e8bb | pbrook | gen_op_neon_getreg_T1(offset); |
3423 | 9ee6e8bb | pbrook | } |
3424 | 9ee6e8bb | pbrook | |
3425 | 9ee6e8bb | pbrook | static inline void gen_op_neon_widen_u32(void) |
3426 | 9ee6e8bb | pbrook | { |
3427 | 9ee6e8bb | pbrook | gen_op_movl_T1_im(0);
|
3428 | 9ee6e8bb | pbrook | } |
3429 | 9ee6e8bb | pbrook | |
3430 | 9ee6e8bb | pbrook | static inline void gen_neon_get_scalar(int size, int reg) |
3431 | 9ee6e8bb | pbrook | { |
3432 | 9ee6e8bb | pbrook | if (size == 1) { |
3433 | 9ee6e8bb | pbrook | NEON_GET_REG(T0, reg >> 1, reg & 1); |
3434 | 9ee6e8bb | pbrook | } else {
|
3435 | 9ee6e8bb | pbrook | NEON_GET_REG(T0, reg >> 2, (reg >> 1) & 1); |
3436 | 9ee6e8bb | pbrook | if (reg & 1) |
3437 | 9ee6e8bb | pbrook | gen_op_neon_dup_low16(); |
3438 | 9ee6e8bb | pbrook | else
|
3439 | 9ee6e8bb | pbrook | gen_op_neon_dup_high16(); |
3440 | 9ee6e8bb | pbrook | } |
3441 | 9ee6e8bb | pbrook | } |
3442 | 9ee6e8bb | pbrook | |
3443 | 9ee6e8bb | pbrook | static void gen_neon_unzip(int reg, int q, int tmp, int size) |
3444 | 9ee6e8bb | pbrook | { |
3445 | 9ee6e8bb | pbrook | int n;
|
3446 | 9ee6e8bb | pbrook | |
3447 | 9ee6e8bb | pbrook | for (n = 0; n < q + 1; n += 2) { |
3448 | 9ee6e8bb | pbrook | NEON_GET_REG(T0, reg, n); |
3449 | 9ee6e8bb | pbrook | NEON_GET_REG(T0, reg, n + n); |
3450 | 9ee6e8bb | pbrook | switch (size) {
|
3451 | 9ee6e8bb | pbrook | case 0: gen_op_neon_unzip_u8(); break; |
3452 | 9ee6e8bb | pbrook | case 1: gen_op_neon_zip_u16(); break; /* zip and unzip are the same. */ |
3453 | 9ee6e8bb | pbrook | case 2: /* no-op */; break; |
3454 | 9ee6e8bb | pbrook | default: abort();
|
3455 | 9ee6e8bb | pbrook | } |
3456 | 9ee6e8bb | pbrook | gen_neon_movl_scratch_T0(tmp + n); |
3457 | 9ee6e8bb | pbrook | gen_neon_movl_scratch_T1(tmp + n + 1);
|
3458 | 9ee6e8bb | pbrook | } |
3459 | 9ee6e8bb | pbrook | } |
3460 | 9ee6e8bb | pbrook | |
3461 | 9ee6e8bb | pbrook | static struct { |
3462 | 9ee6e8bb | pbrook | int nregs;
|
3463 | 9ee6e8bb | pbrook | int interleave;
|
3464 | 9ee6e8bb | pbrook | int spacing;
|
3465 | 9ee6e8bb | pbrook | } neon_ls_element_type[11] = {
|
3466 | 9ee6e8bb | pbrook | {4, 4, 1}, |
3467 | 9ee6e8bb | pbrook | {4, 4, 2}, |
3468 | 9ee6e8bb | pbrook | {4, 1, 1}, |
3469 | 9ee6e8bb | pbrook | {4, 2, 1}, |
3470 | 9ee6e8bb | pbrook | {3, 3, 1}, |
3471 | 9ee6e8bb | pbrook | {3, 3, 2}, |
3472 | 9ee6e8bb | pbrook | {3, 1, 1}, |
3473 | 9ee6e8bb | pbrook | {1, 1, 1}, |
3474 | 9ee6e8bb | pbrook | {2, 2, 1}, |
3475 | 9ee6e8bb | pbrook | {2, 2, 2}, |
3476 | 9ee6e8bb | pbrook | {2, 1, 1} |
3477 | 9ee6e8bb | pbrook | }; |
3478 | 9ee6e8bb | pbrook | |
3479 | 9ee6e8bb | pbrook | /* Translate a NEON load/store element instruction. Return nonzero if the
|
3480 | 9ee6e8bb | pbrook | instruction is invalid. */
|
3481 | 9ee6e8bb | pbrook | static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn) |
3482 | 9ee6e8bb | pbrook | { |
3483 | 9ee6e8bb | pbrook | int rd, rn, rm;
|
3484 | 9ee6e8bb | pbrook | int op;
|
3485 | 9ee6e8bb | pbrook | int nregs;
|
3486 | 9ee6e8bb | pbrook | int interleave;
|
3487 | 9ee6e8bb | pbrook | int stride;
|
3488 | 9ee6e8bb | pbrook | int size;
|
3489 | 9ee6e8bb | pbrook | int reg;
|
3490 | 9ee6e8bb | pbrook | int pass;
|
3491 | 9ee6e8bb | pbrook | int load;
|
3492 | 9ee6e8bb | pbrook | int shift;
|
3493 | 9ee6e8bb | pbrook | int n;
|
3494 | b0109805 | pbrook | TCGv tmp; |
3495 | 8f8e3aa4 | pbrook | TCGv tmp2; |
3496 | 9ee6e8bb | pbrook | |
3497 | 9ee6e8bb | pbrook | if (!vfp_enabled(env))
|
3498 | 9ee6e8bb | pbrook | return 1; |
3499 | 9ee6e8bb | pbrook | VFP_DREG_D(rd, insn); |
3500 | 9ee6e8bb | pbrook | rn = (insn >> 16) & 0xf; |
3501 | 9ee6e8bb | pbrook | rm = insn & 0xf;
|
3502 | 9ee6e8bb | pbrook | load = (insn & (1 << 21)) != 0; |
3503 | 9ee6e8bb | pbrook | if ((insn & (1 << 23)) == 0) { |
3504 | 9ee6e8bb | pbrook | /* Load store all elements. */
|
3505 | 9ee6e8bb | pbrook | op = (insn >> 8) & 0xf; |
3506 | 9ee6e8bb | pbrook | size = (insn >> 6) & 3; |
3507 | 9ee6e8bb | pbrook | if (op > 10 || size == 3) |
3508 | 9ee6e8bb | pbrook | return 1; |
3509 | 9ee6e8bb | pbrook | nregs = neon_ls_element_type[op].nregs; |
3510 | 9ee6e8bb | pbrook | interleave = neon_ls_element_type[op].interleave; |
3511 | 9ee6e8bb | pbrook | gen_movl_T1_reg(s, rn); |
3512 | 9ee6e8bb | pbrook | stride = (1 << size) * interleave;
|
3513 | 9ee6e8bb | pbrook | for (reg = 0; reg < nregs; reg++) { |
3514 | 9ee6e8bb | pbrook | if (interleave > 2 || (interleave == 2 && nregs == 2)) { |
3515 | 9ee6e8bb | pbrook | gen_movl_T1_reg(s, rn); |
3516 | 9ee6e8bb | pbrook | gen_op_addl_T1_im((1 << size) * reg);
|
3517 | 9ee6e8bb | pbrook | } else if (interleave == 2 && nregs == 4 && reg == 2) { |
3518 | 9ee6e8bb | pbrook | gen_movl_T1_reg(s, rn); |
3519 | 9ee6e8bb | pbrook | gen_op_addl_T1_im(1 << size);
|
3520 | 9ee6e8bb | pbrook | } |
3521 | 9ee6e8bb | pbrook | for (pass = 0; pass < 2; pass++) { |
3522 | 9ee6e8bb | pbrook | if (size == 2) { |
3523 | 9ee6e8bb | pbrook | if (load) {
|
3524 | b0109805 | pbrook | tmp = gen_ld32(cpu_T[1], IS_USER(s));
|
3525 | b0109805 | pbrook | tcg_gen_mov_i32(cpu_T[0], tmp);
|
3526 | b0109805 | pbrook | dead_tmp(tmp); |
3527 | 9ee6e8bb | pbrook | NEON_SET_REG(T0, rd, pass); |
3528 | 9ee6e8bb | pbrook | } else {
|
3529 | 9ee6e8bb | pbrook | NEON_GET_REG(T0, rd, pass); |
3530 | b0109805 | pbrook | tmp = new_tmp(); |
3531 | b0109805 | pbrook | tcg_gen_mov_i32(tmp, cpu_T[0]);
|
3532 | b0109805 | pbrook | gen_st32(tmp, cpu_T[1], IS_USER(s));
|
3533 | 9ee6e8bb | pbrook | } |
3534 | 9ee6e8bb | pbrook | gen_op_addl_T1_im(stride); |
3535 | 9ee6e8bb | pbrook | } else if (size == 1) { |
3536 | 9ee6e8bb | pbrook | if (load) {
|
3537 | b0109805 | pbrook | tmp = gen_ld16u(cpu_T[1], IS_USER(s));
|
3538 | 9ee6e8bb | pbrook | gen_op_addl_T1_im(stride); |
3539 | 8f8e3aa4 | pbrook | tmp2 = gen_ld16u(cpu_T[1], IS_USER(s));
|
3540 | 9ee6e8bb | pbrook | gen_op_addl_T1_im(stride); |
3541 | 8f8e3aa4 | pbrook | gen_bfi(tmp, tmp, tmp2, 16, 0xffff); |
3542 | 8f8e3aa4 | pbrook | dead_tmp(tmp2); |
3543 | 8f8e3aa4 | pbrook | neon_store_reg(rd, pass, tmp); |
3544 | 9ee6e8bb | pbrook | } else {
|
3545 | 8f8e3aa4 | pbrook | tmp = neon_load_reg(rd, pass); |
3546 | 8f8e3aa4 | pbrook | tmp2 = new_tmp(); |
3547 | 8f8e3aa4 | pbrook | tcg_gen_shri_i32(tmp2, tmp, 16);
|
3548 | b0109805 | pbrook | gen_st16(tmp, cpu_T[1], IS_USER(s));
|
3549 | 9ee6e8bb | pbrook | gen_op_addl_T1_im(stride); |
3550 | 8f8e3aa4 | pbrook | gen_st16(tmp2, cpu_T[1], IS_USER(s));
|
3551 | 9ee6e8bb | pbrook | gen_op_addl_T1_im(stride); |
3552 | 9ee6e8bb | pbrook | } |
3553 | 9ee6e8bb | pbrook | } else /* size == 0 */ { |
3554 | 9ee6e8bb | pbrook | if (load) {
|
3555 | 9ee6e8bb | pbrook | for (n = 0; n < 4; n++) { |
3556 | b0109805 | pbrook | tmp = gen_ld8u(cpu_T[1], IS_USER(s));
|
3557 | 9ee6e8bb | pbrook | gen_op_addl_T1_im(stride); |
3558 | 9ee6e8bb | pbrook | if (n == 0) { |
3559 | 8f8e3aa4 | pbrook | tmp2 = tmp; |
3560 | 9ee6e8bb | pbrook | } else {
|
3561 | 8f8e3aa4 | pbrook | gen_bfi(tmp2, tmp2, tmp, n * 8, 0xff); |
3562 | 8f8e3aa4 | pbrook | dead_tmp(tmp); |
3563 | 9ee6e8bb | pbrook | } |
3564 | 9ee6e8bb | pbrook | } |
3565 | 8f8e3aa4 | pbrook | neon_store_reg(rd, pass, tmp2); |
3566 | 9ee6e8bb | pbrook | } else {
|
3567 | 8f8e3aa4 | pbrook | tmp2 = neon_load_reg(rd, pass); |
3568 | 9ee6e8bb | pbrook | for (n = 0; n < 4; n++) { |
3569 | 8f8e3aa4 | pbrook | tmp = new_tmp(); |
3570 | 9ee6e8bb | pbrook | if (n == 0) { |
3571 | 8f8e3aa4 | pbrook | tcg_gen_mov_i32(tmp, tmp2); |
3572 | 9ee6e8bb | pbrook | } else {
|
3573 | 8f8e3aa4 | pbrook | tcg_gen_shri_i32(tmp, tmp2, n * 8);
|
3574 | 9ee6e8bb | pbrook | } |
3575 | b0109805 | pbrook | gen_st8(tmp, cpu_T[1], IS_USER(s));
|
3576 | 9ee6e8bb | pbrook | gen_op_addl_T1_im(stride); |
3577 | 9ee6e8bb | pbrook | } |
3578 | 8f8e3aa4 | pbrook | dead_tmp(tmp2); |
3579 | 9ee6e8bb | pbrook | } |
3580 | 9ee6e8bb | pbrook | } |
3581 | 9ee6e8bb | pbrook | } |
3582 | 9ee6e8bb | pbrook | rd += neon_ls_element_type[op].spacing; |
3583 | 9ee6e8bb | pbrook | } |
3584 | 9ee6e8bb | pbrook | stride = nregs * 8;
|
3585 | 9ee6e8bb | pbrook | } else {
|
3586 | 9ee6e8bb | pbrook | size = (insn >> 10) & 3; |
3587 | 9ee6e8bb | pbrook | if (size == 3) { |
3588 | 9ee6e8bb | pbrook | /* Load single element to all lanes. */
|
3589 | 9ee6e8bb | pbrook | if (!load)
|
3590 | 9ee6e8bb | pbrook | return 1; |
3591 | 9ee6e8bb | pbrook | size = (insn >> 6) & 3; |
3592 | 9ee6e8bb | pbrook | nregs = ((insn >> 8) & 3) + 1; |
3593 | 9ee6e8bb | pbrook | stride = (insn & (1 << 5)) ? 2 : 1; |
3594 | ff8263a9 | bellard | gen_movl_T1_reg(s, rn); |
3595 | 9ee6e8bb | pbrook | for (reg = 0; reg < nregs; reg++) { |
3596 | 9ee6e8bb | pbrook | switch (size) {
|
3597 | 9ee6e8bb | pbrook | case 0: |
3598 | b0109805 | pbrook | tmp = gen_ld8u(cpu_T[1], IS_USER(s));
|
3599 | b0109805 | pbrook | tcg_gen_mov_i32(cpu_T[0], tmp);
|
3600 | b0109805 | pbrook | dead_tmp(tmp); |
3601 | 9ee6e8bb | pbrook | gen_op_neon_dup_u8(0);
|
3602 | 9ee6e8bb | pbrook | break;
|
3603 | 9ee6e8bb | pbrook | case 1: |
3604 | b0109805 | pbrook | tmp = gen_ld16u(cpu_T[1], IS_USER(s));
|
3605 | b0109805 | pbrook | tcg_gen_mov_i32(cpu_T[0], tmp);
|
3606 | b0109805 | pbrook | dead_tmp(tmp); |
3607 | 9ee6e8bb | pbrook | gen_op_neon_dup_low16(); |
3608 | 9ee6e8bb | pbrook | break;
|
3609 | 9ee6e8bb | pbrook | case 2: |
3610 | b0109805 | pbrook | tmp = gen_ld32(cpu_T[0], IS_USER(s));
|
3611 | b0109805 | pbrook | tcg_gen_mov_i32(cpu_T[0], tmp);
|
3612 | b0109805 | pbrook | dead_tmp(tmp); |
3613 | 9ee6e8bb | pbrook | break;
|
3614 | 9ee6e8bb | pbrook | case 3: |
3615 | 9ee6e8bb | pbrook | return 1; |
3616 | 99c475ab | bellard | } |
3617 | 9ee6e8bb | pbrook | gen_op_addl_T1_im(1 << size);
|
3618 | 9ee6e8bb | pbrook | NEON_SET_REG(T0, rd, 0);
|
3619 | 9ee6e8bb | pbrook | NEON_SET_REG(T0, rd, 1);
|
3620 | 9ee6e8bb | pbrook | rd += stride; |
3621 | 9ee6e8bb | pbrook | } |
3622 | 9ee6e8bb | pbrook | stride = (1 << size) * nregs;
|
3623 | 9ee6e8bb | pbrook | } else {
|
3624 | 9ee6e8bb | pbrook | /* Single element. */
|
3625 | 9ee6e8bb | pbrook | pass = (insn >> 7) & 1; |
3626 | 9ee6e8bb | pbrook | switch (size) {
|
3627 | 9ee6e8bb | pbrook | case 0: |
3628 | 9ee6e8bb | pbrook | shift = ((insn >> 5) & 3) * 8; |
3629 | 9ee6e8bb | pbrook | stride = 1;
|
3630 | 9ee6e8bb | pbrook | break;
|
3631 | 9ee6e8bb | pbrook | case 1: |
3632 | 9ee6e8bb | pbrook | shift = ((insn >> 6) & 1) * 16; |
3633 | 9ee6e8bb | pbrook | stride = (insn & (1 << 5)) ? 2 : 1; |
3634 | 9ee6e8bb | pbrook | break;
|
3635 | 9ee6e8bb | pbrook | case 2: |
3636 | 9ee6e8bb | pbrook | shift = 0;
|
3637 | 9ee6e8bb | pbrook | stride = (insn & (1 << 6)) ? 2 : 1; |
3638 | 9ee6e8bb | pbrook | break;
|
3639 | 9ee6e8bb | pbrook | default:
|
3640 | 9ee6e8bb | pbrook | abort(); |
3641 | 9ee6e8bb | pbrook | } |
3642 | 9ee6e8bb | pbrook | nregs = ((insn >> 8) & 3) + 1; |
3643 | 9ee6e8bb | pbrook | gen_movl_T1_reg(s, rn); |
3644 | 9ee6e8bb | pbrook | for (reg = 0; reg < nregs; reg++) { |
3645 | 9ee6e8bb | pbrook | if (load) {
|
3646 | 9ee6e8bb | pbrook | switch (size) {
|
3647 | 9ee6e8bb | pbrook | case 0: |
3648 | b0109805 | pbrook | tmp = gen_ld8u(cpu_T[1], IS_USER(s));
|
3649 | 9ee6e8bb | pbrook | break;
|
3650 | 9ee6e8bb | pbrook | case 1: |
3651 | b0109805 | pbrook | tmp = gen_ld16u(cpu_T[1], IS_USER(s));
|
3652 | 9ee6e8bb | pbrook | break;
|
3653 | 9ee6e8bb | pbrook | case 2: |
3654 | b0109805 | pbrook | tmp = gen_ld32(cpu_T[1], IS_USER(s));
|
3655 | 9ee6e8bb | pbrook | break;
|
3656 | 9ee6e8bb | pbrook | } |
3657 | 9ee6e8bb | pbrook | if (size != 2) { |
3658 | 8f8e3aa4 | pbrook | tmp2 = neon_load_reg(rd, pass); |
3659 | 8f8e3aa4 | pbrook | gen_bfi(tmp, tmp2, tmp, shift, size ? 0xffff : 0xff); |
3660 | 8f8e3aa4 | pbrook | dead_tmp(tmp2); |
3661 | 9ee6e8bb | pbrook | } |
3662 | 8f8e3aa4 | pbrook | neon_store_reg(rd, pass, tmp); |
3663 | 9ee6e8bb | pbrook | } else { /* Store */ |
3664 | 8f8e3aa4 | pbrook | tmp = neon_load_reg(rd, pass); |
3665 | 8f8e3aa4 | pbrook | if (shift)
|
3666 | 8f8e3aa4 | pbrook | tcg_gen_shri_i32(tmp, tmp, shift); |
3667 | 9ee6e8bb | pbrook | switch (size) {
|
3668 | 9ee6e8bb | pbrook | case 0: |
3669 | b0109805 | pbrook | gen_st8(tmp, cpu_T[1], IS_USER(s));
|
3670 | 9ee6e8bb | pbrook | break;
|
3671 | 9ee6e8bb | pbrook | case 1: |
3672 | b0109805 | pbrook | gen_st16(tmp, cpu_T[1], IS_USER(s));
|
3673 | 9ee6e8bb | pbrook | break;
|
3674 | 9ee6e8bb | pbrook | case 2: |
3675 | b0109805 | pbrook | gen_st32(tmp, cpu_T[1], IS_USER(s));
|
3676 | 9ee6e8bb | pbrook | break;
|
3677 | 99c475ab | bellard | } |
3678 | 99c475ab | bellard | } |
3679 | 9ee6e8bb | pbrook | rd += stride; |
3680 | 9ee6e8bb | pbrook | gen_op_addl_T1_im(1 << size);
|
3681 | 99c475ab | bellard | } |
3682 | 9ee6e8bb | pbrook | stride = nregs * (1 << size);
|
3683 | 99c475ab | bellard | } |
3684 | 9ee6e8bb | pbrook | } |
3685 | 9ee6e8bb | pbrook | if (rm != 15) { |
3686 | b26eefb6 | pbrook | TCGv base; |
3687 | b26eefb6 | pbrook | |
3688 | b26eefb6 | pbrook | base = load_reg(s, rn); |
3689 | 9ee6e8bb | pbrook | if (rm == 13) { |
3690 | b26eefb6 | pbrook | tcg_gen_addi_i32(base, base, stride); |
3691 | 9ee6e8bb | pbrook | } else {
|
3692 | b26eefb6 | pbrook | TCGv index; |
3693 | b26eefb6 | pbrook | index = load_reg(s, rm); |
3694 | b26eefb6 | pbrook | tcg_gen_add_i32(base, base, index); |
3695 | b26eefb6 | pbrook | dead_tmp(index); |
3696 | 9ee6e8bb | pbrook | } |
3697 | b26eefb6 | pbrook | store_reg(s, rn, base); |
3698 | 9ee6e8bb | pbrook | } |
3699 | 9ee6e8bb | pbrook | return 0; |
3700 | 9ee6e8bb | pbrook | } |
3701 | 3b46e624 | ths | |
3702 | 8f8e3aa4 | pbrook | /* Bitwise select. dest = c ? t : f. Clobbers T and F. */
|
3703 | 8f8e3aa4 | pbrook | static void gen_neon_bsl(TCGv dest, TCGv t, TCGv f, TCGv c) |
3704 | 8f8e3aa4 | pbrook | { |
3705 | 8f8e3aa4 | pbrook | tcg_gen_and_i32(t, t, c); |
3706 | 8f8e3aa4 | pbrook | tcg_gen_bic_i32(f, f, c); |
3707 | 8f8e3aa4 | pbrook | tcg_gen_or_i32(dest, t, f); |
3708 | 8f8e3aa4 | pbrook | } |
3709 | 8f8e3aa4 | pbrook | |
3710 | 9ee6e8bb | pbrook | /* Translate a NEON data processing instruction. Return nonzero if the
|
3711 | 9ee6e8bb | pbrook | instruction is invalid.
|
3712 | 9ee6e8bb | pbrook | In general we process vectors in 32-bit chunks. This means we can reuse
|
3713 | 9ee6e8bb | pbrook | some of the scalar ops, and hopefully the code generated for 32-bit
|
3714 | 9ee6e8bb | pbrook | hosts won't be too awful. The downside is that the few 64-bit operations
|
3715 | 9ee6e8bb | pbrook | (mainly shifts) get complicated. */
|
3716 | 2c0262af | bellard | |
3717 | 9ee6e8bb | pbrook | static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) |
3718 | 9ee6e8bb | pbrook | { |
3719 | 9ee6e8bb | pbrook | int op;
|
3720 | 9ee6e8bb | pbrook | int q;
|
3721 | 9ee6e8bb | pbrook | int rd, rn, rm;
|
3722 | 9ee6e8bb | pbrook | int size;
|
3723 | 9ee6e8bb | pbrook | int shift;
|
3724 | 9ee6e8bb | pbrook | int pass;
|
3725 | 9ee6e8bb | pbrook | int count;
|
3726 | 9ee6e8bb | pbrook | int pairwise;
|
3727 | 9ee6e8bb | pbrook | int u;
|
3728 | 9ee6e8bb | pbrook | int n;
|
3729 | 9ee6e8bb | pbrook | uint32_t imm; |
3730 | 8f8e3aa4 | pbrook | TCGv tmp; |
3731 | 8f8e3aa4 | pbrook | TCGv tmp2; |
3732 | 8f8e3aa4 | pbrook | TCGv tmp3; |
3733 | 9ee6e8bb | pbrook | |
3734 | 9ee6e8bb | pbrook | if (!vfp_enabled(env))
|
3735 | 9ee6e8bb | pbrook | return 1; |
3736 | 9ee6e8bb | pbrook | q = (insn & (1 << 6)) != 0; |
3737 | 9ee6e8bb | pbrook | u = (insn >> 24) & 1; |
3738 | 9ee6e8bb | pbrook | VFP_DREG_D(rd, insn); |
3739 | 9ee6e8bb | pbrook | VFP_DREG_N(rn, insn); |
3740 | 9ee6e8bb | pbrook | VFP_DREG_M(rm, insn); |
3741 | 9ee6e8bb | pbrook | size = (insn >> 20) & 3; |
3742 | 9ee6e8bb | pbrook | if ((insn & (1 << 23)) == 0) { |
3743 | 9ee6e8bb | pbrook | /* Three register same length. */
|
3744 | 9ee6e8bb | pbrook | op = ((insn >> 7) & 0x1e) | ((insn >> 4) & 1); |
3745 | 9ee6e8bb | pbrook | if (size == 3 && (op == 1 || op == 5 || op == 16)) { |
3746 | 9ee6e8bb | pbrook | for (pass = 0; pass < (q ? 2 : 1); pass++) { |
3747 | 9ee6e8bb | pbrook | NEON_GET_REG(T0, rm, pass * 2);
|
3748 | 9ee6e8bb | pbrook | NEON_GET_REG(T1, rm, pass * 2 + 1); |
3749 | 9ee6e8bb | pbrook | gen_neon_movl_scratch_T0(0);
|
3750 | 9ee6e8bb | pbrook | gen_neon_movl_scratch_T1(1);
|
3751 | 9ee6e8bb | pbrook | NEON_GET_REG(T0, rn, pass * 2);
|
3752 | 9ee6e8bb | pbrook | NEON_GET_REG(T1, rn, pass * 2 + 1); |
3753 | 9ee6e8bb | pbrook | switch (op) {
|
3754 | 9ee6e8bb | pbrook | case 1: /* VQADD */ |
3755 | 9ee6e8bb | pbrook | if (u) {
|
3756 | 9ee6e8bb | pbrook | gen_op_neon_addl_saturate_u64(); |
3757 | 2c0262af | bellard | } else {
|
3758 | 9ee6e8bb | pbrook | gen_op_neon_addl_saturate_s64(); |
3759 | 2c0262af | bellard | } |
3760 | 9ee6e8bb | pbrook | break;
|
3761 | 9ee6e8bb | pbrook | case 5: /* VQSUB */ |
3762 | 9ee6e8bb | pbrook | if (u) {
|
3763 | 9ee6e8bb | pbrook | gen_op_neon_subl_saturate_u64(); |
3764 | 1e8d4eec | bellard | } else {
|
3765 | 9ee6e8bb | pbrook | gen_op_neon_subl_saturate_s64(); |
3766 | 1e8d4eec | bellard | } |
3767 | 9ee6e8bb | pbrook | break;
|
3768 | 9ee6e8bb | pbrook | case 16: |
3769 | 9ee6e8bb | pbrook | if (u) {
|
3770 | 9ee6e8bb | pbrook | gen_op_neon_subl_u64(); |
3771 | 9ee6e8bb | pbrook | } else {
|
3772 | 9ee6e8bb | pbrook | gen_op_neon_addl_u64(); |
3773 | 9ee6e8bb | pbrook | } |
3774 | 9ee6e8bb | pbrook | break;
|
3775 | 9ee6e8bb | pbrook | default:
|
3776 | 9ee6e8bb | pbrook | abort(); |
3777 | 2c0262af | bellard | } |
3778 | 9ee6e8bb | pbrook | NEON_SET_REG(T0, rd, pass * 2);
|
3779 | 9ee6e8bb | pbrook | NEON_SET_REG(T1, rd, pass * 2 + 1); |
3780 | 2c0262af | bellard | } |
3781 | 9ee6e8bb | pbrook | return 0; |
3782 | 2c0262af | bellard | } |
3783 | 9ee6e8bb | pbrook | switch (op) {
|
3784 | 9ee6e8bb | pbrook | case 8: /* VSHL */ |
3785 | 9ee6e8bb | pbrook | case 9: /* VQSHL */ |
3786 | 9ee6e8bb | pbrook | case 10: /* VRSHL */ |
3787 | 9ee6e8bb | pbrook | case 11: /* VQSHL */ |
3788 | 9ee6e8bb | pbrook | /* Shift operations have Rn and Rm reversed. */
|
3789 | 9ee6e8bb | pbrook | { |
3790 | 9ee6e8bb | pbrook | int tmp;
|
3791 | 9ee6e8bb | pbrook | tmp = rn; |
3792 | 9ee6e8bb | pbrook | rn = rm; |
3793 | 9ee6e8bb | pbrook | rm = tmp; |
3794 | 9ee6e8bb | pbrook | pairwise = 0;
|
3795 | 9ee6e8bb | pbrook | } |
3796 | 2c0262af | bellard | break;
|
3797 | 9ee6e8bb | pbrook | case 20: /* VPMAX */ |
3798 | 9ee6e8bb | pbrook | case 21: /* VPMIN */ |
3799 | 9ee6e8bb | pbrook | case 23: /* VPADD */ |
3800 | 9ee6e8bb | pbrook | pairwise = 1;
|
3801 | 2c0262af | bellard | break;
|
3802 | 9ee6e8bb | pbrook | case 26: /* VPADD (float) */ |
3803 | 9ee6e8bb | pbrook | pairwise = (u && size < 2);
|
3804 | 2c0262af | bellard | break;
|
3805 | 9ee6e8bb | pbrook | case 30: /* VPMIN/VPMAX (float) */ |
3806 | 9ee6e8bb | pbrook | pairwise = u; |
3807 | 2c0262af | bellard | break;
|
3808 | 9ee6e8bb | pbrook | default:
|
3809 | 9ee6e8bb | pbrook | pairwise = 0;
|
3810 | 2c0262af | bellard | break;
|
3811 | 9ee6e8bb | pbrook | } |
3812 | 9ee6e8bb | pbrook | for (pass = 0; pass < (q ? 4 : 2); pass++) { |
3813 | 9ee6e8bb | pbrook | |
3814 | 9ee6e8bb | pbrook | if (pairwise) {
|
3815 | 9ee6e8bb | pbrook | /* Pairwise. */
|
3816 | 9ee6e8bb | pbrook | if (q)
|
3817 | 9ee6e8bb | pbrook | n = (pass & 1) * 2; |
3818 | 2c0262af | bellard | else
|
3819 | 9ee6e8bb | pbrook | n = 0;
|
3820 | 9ee6e8bb | pbrook | if (pass < q + 1) { |
3821 | 9ee6e8bb | pbrook | NEON_GET_REG(T0, rn, n); |
3822 | 9ee6e8bb | pbrook | NEON_GET_REG(T1, rn, n + 1);
|
3823 | 9ee6e8bb | pbrook | } else {
|
3824 | 9ee6e8bb | pbrook | NEON_GET_REG(T0, rm, n); |
3825 | 9ee6e8bb | pbrook | NEON_GET_REG(T1, rm, n + 1);
|
3826 | 9ee6e8bb | pbrook | } |
3827 | 9ee6e8bb | pbrook | } else {
|
3828 | 9ee6e8bb | pbrook | /* Elementwise. */
|
3829 | 9ee6e8bb | pbrook | NEON_GET_REG(T0, rn, pass); |
3830 | 9ee6e8bb | pbrook | NEON_GET_REG(T1, rm, pass); |
3831 | 9ee6e8bb | pbrook | } |
3832 | 9ee6e8bb | pbrook | switch (op) {
|
3833 | 9ee6e8bb | pbrook | case 0: /* VHADD */ |
3834 | 9ee6e8bb | pbrook | GEN_NEON_INTEGER_OP(hadd); |
3835 | 9ee6e8bb | pbrook | break;
|
3836 | 9ee6e8bb | pbrook | case 1: /* VQADD */ |
3837 | 9ee6e8bb | pbrook | switch (size << 1| u) { |
3838 | 9ee6e8bb | pbrook | case 0: gen_op_neon_qadd_s8(); break; |
3839 | 9ee6e8bb | pbrook | case 1: gen_op_neon_qadd_u8(); break; |
3840 | 9ee6e8bb | pbrook | case 2: gen_op_neon_qadd_s16(); break; |
3841 | 9ee6e8bb | pbrook | case 3: gen_op_neon_qadd_u16(); break; |
3842 | 5e3f878a | pbrook | case 4: |
3843 | 5e3f878a | pbrook | gen_helper_add_saturate(cpu_T[0], cpu_T[0], cpu_T[1]); |
3844 | 5e3f878a | pbrook | break;
|
3845 | 5e3f878a | pbrook | case 5: |
3846 | 5e3f878a | pbrook | gen_helper_add_usaturate(cpu_T[0], cpu_T[0], cpu_T[1]); |
3847 | 5e3f878a | pbrook | break;
|
3848 | 9ee6e8bb | pbrook | default: abort();
|
3849 | 9ee6e8bb | pbrook | } |
3850 | 2c0262af | bellard | break;
|
3851 | 9ee6e8bb | pbrook | case 2: /* VRHADD */ |
3852 | 9ee6e8bb | pbrook | GEN_NEON_INTEGER_OP(rhadd); |
3853 | 2c0262af | bellard | break;
|
3854 | 9ee6e8bb | pbrook | case 3: /* Logic ops. */ |
3855 | 9ee6e8bb | pbrook | switch ((u << 2) | size) { |
3856 | 9ee6e8bb | pbrook | case 0: /* VAND */ |
3857 | 2c0262af | bellard | gen_op_andl_T0_T1(); |
3858 | 9ee6e8bb | pbrook | break;
|
3859 | 9ee6e8bb | pbrook | case 1: /* BIC */ |
3860 | 9ee6e8bb | pbrook | gen_op_bicl_T0_T1(); |
3861 | 9ee6e8bb | pbrook | break;
|
3862 | 9ee6e8bb | pbrook | case 2: /* VORR */ |
3863 | 9ee6e8bb | pbrook | gen_op_orl_T0_T1(); |
3864 | 9ee6e8bb | pbrook | break;
|
3865 | 9ee6e8bb | pbrook | case 3: /* VORN */ |
3866 | 9ee6e8bb | pbrook | gen_op_notl_T1(); |
3867 | 9ee6e8bb | pbrook | gen_op_orl_T0_T1(); |
3868 | 9ee6e8bb | pbrook | break;
|
3869 | 9ee6e8bb | pbrook | case 4: /* VEOR */ |
3870 | 9ee6e8bb | pbrook | gen_op_xorl_T0_T1(); |
3871 | 9ee6e8bb | pbrook | break;
|
3872 | 9ee6e8bb | pbrook | case 5: /* VBSL */ |
3873 | 8f8e3aa4 | pbrook | tmp = neon_load_reg(rd, pass); |
3874 | 8f8e3aa4 | pbrook | gen_neon_bsl(cpu_T[0], cpu_T[0], cpu_T[1], tmp); |
3875 | 8f8e3aa4 | pbrook | dead_tmp(tmp); |
3876 | 9ee6e8bb | pbrook | break;
|
3877 | 9ee6e8bb | pbrook | case 6: /* VBIT */ |
3878 | 8f8e3aa4 | pbrook | tmp = neon_load_reg(rd, pass); |
3879 | 8f8e3aa4 | pbrook | gen_neon_bsl(cpu_T[0], cpu_T[0], tmp, cpu_T[1]); |
3880 | 8f8e3aa4 | pbrook | dead_tmp(tmp); |
3881 | 9ee6e8bb | pbrook | break;
|
3882 | 9ee6e8bb | pbrook | case 7: /* VBIF */ |
3883 | 8f8e3aa4 | pbrook | tmp = neon_load_reg(rd, pass); |
3884 | 8f8e3aa4 | pbrook | gen_neon_bsl(cpu_T[0], tmp, cpu_T[0], cpu_T[1]); |
3885 | 8f8e3aa4 | pbrook | dead_tmp(tmp); |
3886 | 9ee6e8bb | pbrook | break;
|
3887 | 2c0262af | bellard | } |
3888 | 2c0262af | bellard | break;
|
3889 | 9ee6e8bb | pbrook | case 4: /* VHSUB */ |
3890 | 9ee6e8bb | pbrook | GEN_NEON_INTEGER_OP(hsub); |
3891 | 9ee6e8bb | pbrook | break;
|
3892 | 9ee6e8bb | pbrook | case 5: /* VQSUB */ |
3893 | 9ee6e8bb | pbrook | switch ((size << 1) | u) { |
3894 | 9ee6e8bb | pbrook | case 0: gen_op_neon_qsub_s8(); break; |
3895 | 9ee6e8bb | pbrook | case 1: gen_op_neon_qsub_u8(); break; |
3896 | 9ee6e8bb | pbrook | case 2: gen_op_neon_qsub_s16(); break; |
3897 | 9ee6e8bb | pbrook | case 3: gen_op_neon_qsub_u16(); break; |
3898 | 5e3f878a | pbrook | case 4: |
3899 | 5e3f878a | pbrook | gen_helper_sub_saturate(cpu_T[0], cpu_T[0], cpu_T[1]); |
3900 | 5e3f878a | pbrook | break;
|
3901 | 5e3f878a | pbrook | case 5: |
3902 | 5e3f878a | pbrook | gen_helper_sub_usaturate(cpu_T[0], cpu_T[0], cpu_T[1]); |
3903 | 5e3f878a | pbrook | break;
|
3904 | 9ee6e8bb | pbrook | default: abort();
|
3905 | 2c0262af | bellard | } |
3906 | 2c0262af | bellard | break;
|
3907 | 9ee6e8bb | pbrook | case 6: /* VCGT */ |
3908 | 9ee6e8bb | pbrook | GEN_NEON_INTEGER_OP(cgt); |
3909 | 9ee6e8bb | pbrook | break;
|
3910 | 9ee6e8bb | pbrook | case 7: /* VCGE */ |
3911 | 9ee6e8bb | pbrook | GEN_NEON_INTEGER_OP(cge); |
3912 | 9ee6e8bb | pbrook | break;
|
3913 | 9ee6e8bb | pbrook | case 8: /* VSHL */ |
3914 | 9ee6e8bb | pbrook | switch ((size << 1) | u) { |
3915 | 9ee6e8bb | pbrook | case 0: gen_op_neon_shl_s8(); break; |
3916 | 9ee6e8bb | pbrook | case 1: gen_op_neon_shl_u8(); break; |
3917 | 9ee6e8bb | pbrook | case 2: gen_op_neon_shl_s16(); break; |
3918 | 9ee6e8bb | pbrook | case 3: gen_op_neon_shl_u16(); break; |
3919 | 9ee6e8bb | pbrook | case 4: gen_op_neon_shl_s32(); break; |
3920 | 9ee6e8bb | pbrook | case 5: gen_op_neon_shl_u32(); break; |
3921 | 9ee6e8bb | pbrook | #if 0
|
3922 | 9ee6e8bb | pbrook | /* ??? Implementing these is tricky because the vector ops work
|
3923 | 9ee6e8bb | pbrook | on 32-bit pieces. */
|
3924 | 9ee6e8bb | pbrook | case 6: gen_op_neon_shl_s64(); break;
|
3925 | 9ee6e8bb | pbrook | case 7: gen_op_neon_shl_u64(); break;
|
3926 | 9ee6e8bb | pbrook | #else
|
3927 | 9ee6e8bb | pbrook | case 6: case 7: cpu_abort(env, "VSHL.64 not implemented"); |
3928 | 9ee6e8bb | pbrook | #endif
|
3929 | 2c0262af | bellard | } |
3930 | 2c0262af | bellard | break;
|
3931 | 9ee6e8bb | pbrook | case 9: /* VQSHL */ |
3932 | 9ee6e8bb | pbrook | switch ((size << 1) | u) { |
3933 | 9ee6e8bb | pbrook | case 0: gen_op_neon_qshl_s8(); break; |
3934 | 9ee6e8bb | pbrook | case 1: gen_op_neon_qshl_u8(); break; |
3935 | 9ee6e8bb | pbrook | case 2: gen_op_neon_qshl_s16(); break; |
3936 | 9ee6e8bb | pbrook | case 3: gen_op_neon_qshl_u16(); break; |
3937 | 9ee6e8bb | pbrook | case 4: gen_op_neon_qshl_s32(); break; |
3938 | 9ee6e8bb | pbrook | case 5: gen_op_neon_qshl_u32(); break; |
3939 | 9ee6e8bb | pbrook | #if 0
|
3940 | 9ee6e8bb | pbrook | /* ??? Implementing these is tricky because the vector ops work
|
3941 | 9ee6e8bb | pbrook | on 32-bit pieces. */
|
3942 | 9ee6e8bb | pbrook | case 6: gen_op_neon_qshl_s64(); break;
|
3943 | 9ee6e8bb | pbrook | case 7: gen_op_neon_qshl_u64(); break;
|
3944 | 9ee6e8bb | pbrook | #else
|
3945 | 9ee6e8bb | pbrook | case 6: case 7: cpu_abort(env, "VQSHL.64 not implemented"); |
3946 | 9ee6e8bb | pbrook | #endif
|
3947 | 2c0262af | bellard | } |
3948 | 2c0262af | bellard | break;
|
3949 | 9ee6e8bb | pbrook | case 10: /* VRSHL */ |
3950 | 9ee6e8bb | pbrook | switch ((size << 1) | u) { |
3951 | 9ee6e8bb | pbrook | case 0: gen_op_neon_rshl_s8(); break; |
3952 | 9ee6e8bb | pbrook | case 1: gen_op_neon_rshl_u8(); break; |
3953 | 9ee6e8bb | pbrook | case 2: gen_op_neon_rshl_s16(); break; |
3954 | 9ee6e8bb | pbrook | case 3: gen_op_neon_rshl_u16(); break; |
3955 | 9ee6e8bb | pbrook | case 4: gen_op_neon_rshl_s32(); break; |
3956 | 9ee6e8bb | pbrook | case 5: gen_op_neon_rshl_u32(); break; |
3957 | 9ee6e8bb | pbrook | #if 0
|
3958 | 9ee6e8bb | pbrook | /* ??? Implementing these is tricky because the vector ops work
|
3959 | 9ee6e8bb | pbrook | on 32-bit pieces. */
|
3960 | 9ee6e8bb | pbrook | case 6: gen_op_neon_rshl_s64(); break;
|
3961 | 9ee6e8bb | pbrook | case 7: gen_op_neon_rshl_u64(); break;
|
3962 | 9ee6e8bb | pbrook | #else
|
3963 | 9ee6e8bb | pbrook | case 6: case 7: cpu_abort(env, "VRSHL.64 not implemented"); |
3964 | 9ee6e8bb | pbrook | #endif
|
3965 | 9ee6e8bb | pbrook | } |
3966 | 2c0262af | bellard | break;
|
3967 | 9ee6e8bb | pbrook | case 11: /* VQRSHL */ |
3968 | 9ee6e8bb | pbrook | switch ((size << 1) | u) { |
3969 | 9ee6e8bb | pbrook | case 0: gen_op_neon_qrshl_s8(); break; |
3970 | 9ee6e8bb | pbrook | case 1: gen_op_neon_qrshl_u8(); break; |
3971 | 9ee6e8bb | pbrook | case 2: gen_op_neon_qrshl_s16(); break; |
3972 | 9ee6e8bb | pbrook | case 3: gen_op_neon_qrshl_u16(); break; |
3973 | 9ee6e8bb | pbrook | case 4: gen_op_neon_qrshl_s32(); break; |
3974 | 9ee6e8bb | pbrook | case 5: gen_op_neon_qrshl_u32(); break; |
3975 | 9ee6e8bb | pbrook | #if 0
|
3976 | 9ee6e8bb | pbrook | /* ??? Implementing these is tricky because the vector ops work
|
3977 | 9ee6e8bb | pbrook | on 32-bit pieces. */
|
3978 | 9ee6e8bb | pbrook | case 6: gen_op_neon_qrshl_s64(); break;
|
3979 | 9ee6e8bb | pbrook | case 7: gen_op_neon_qrshl_u64(); break;
|
3980 | 9ee6e8bb | pbrook | #else
|
3981 | 9ee6e8bb | pbrook | case 6: case 7: cpu_abort(env, "VQRSHL.64 not implemented"); |
3982 | 9ee6e8bb | pbrook | #endif
|
3983 | 9ee6e8bb | pbrook | } |
3984 | 9ee6e8bb | pbrook | break;
|
3985 | 9ee6e8bb | pbrook | case 12: /* VMAX */ |
3986 | 9ee6e8bb | pbrook | GEN_NEON_INTEGER_OP(max); |
3987 | 9ee6e8bb | pbrook | break;
|
3988 | 9ee6e8bb | pbrook | case 13: /* VMIN */ |
3989 | 9ee6e8bb | pbrook | GEN_NEON_INTEGER_OP(min); |
3990 | 9ee6e8bb | pbrook | break;
|
3991 | 9ee6e8bb | pbrook | case 14: /* VABD */ |
3992 | 9ee6e8bb | pbrook | GEN_NEON_INTEGER_OP(abd); |
3993 | 9ee6e8bb | pbrook | break;
|
3994 | 9ee6e8bb | pbrook | case 15: /* VABA */ |
3995 | 9ee6e8bb | pbrook | GEN_NEON_INTEGER_OP(abd); |
3996 | 9ee6e8bb | pbrook | NEON_GET_REG(T1, rd, pass); |
3997 | 9ee6e8bb | pbrook | gen_neon_add(size); |
3998 | 9ee6e8bb | pbrook | break;
|
3999 | 9ee6e8bb | pbrook | case 16: |
4000 | 9ee6e8bb | pbrook | if (!u) { /* VADD */ |
4001 | 9ee6e8bb | pbrook | if (gen_neon_add(size))
|
4002 | 9ee6e8bb | pbrook | return 1; |
4003 | 9ee6e8bb | pbrook | } else { /* VSUB */ |
4004 | 9ee6e8bb | pbrook | switch (size) {
|
4005 | 9ee6e8bb | pbrook | case 0: gen_op_neon_sub_u8(); break; |
4006 | 9ee6e8bb | pbrook | case 1: gen_op_neon_sub_u16(); break; |
4007 | 9ee6e8bb | pbrook | case 2: gen_op_subl_T0_T1(); break; |
4008 | 9ee6e8bb | pbrook | default: return 1; |
4009 | 9ee6e8bb | pbrook | } |
4010 | 9ee6e8bb | pbrook | } |
4011 | 9ee6e8bb | pbrook | break;
|
4012 | 9ee6e8bb | pbrook | case 17: |
4013 | 9ee6e8bb | pbrook | if (!u) { /* VTST */ |
4014 | 9ee6e8bb | pbrook | switch (size) {
|
4015 | 9ee6e8bb | pbrook | case 0: gen_op_neon_tst_u8(); break; |
4016 | 9ee6e8bb | pbrook | case 1: gen_op_neon_tst_u16(); break; |
4017 | 9ee6e8bb | pbrook | case 2: gen_op_neon_tst_u32(); break; |
4018 | 9ee6e8bb | pbrook | default: return 1; |
4019 | 9ee6e8bb | pbrook | } |
4020 | 9ee6e8bb | pbrook | } else { /* VCEQ */ |
4021 | 9ee6e8bb | pbrook | switch (size) {
|
4022 | 9ee6e8bb | pbrook | case 0: gen_op_neon_ceq_u8(); break; |
4023 | 9ee6e8bb | pbrook | case 1: gen_op_neon_ceq_u16(); break; |
4024 | 9ee6e8bb | pbrook | case 2: gen_op_neon_ceq_u32(); break; |
4025 | 9ee6e8bb | pbrook | default: return 1; |
4026 | 9ee6e8bb | pbrook | } |
4027 | 9ee6e8bb | pbrook | } |
4028 | 9ee6e8bb | pbrook | break;
|
4029 | 9ee6e8bb | pbrook | case 18: /* Multiply. */ |
4030 | 9ee6e8bb | pbrook | switch (size) {
|
4031 | 9ee6e8bb | pbrook | case 0: gen_op_neon_mul_u8(); break; |
4032 | 9ee6e8bb | pbrook | case 1: gen_op_neon_mul_u16(); break; |
4033 | 9ee6e8bb | pbrook | case 2: gen_op_mul_T0_T1(); break; |
4034 | 9ee6e8bb | pbrook | default: return 1; |
4035 | 9ee6e8bb | pbrook | } |
4036 | 9ee6e8bb | pbrook | NEON_GET_REG(T1, rd, pass); |
4037 | 9ee6e8bb | pbrook | if (u) { /* VMLS */ |
4038 | 9ee6e8bb | pbrook | switch (size) {
|
4039 | 9ee6e8bb | pbrook | case 0: gen_op_neon_rsb_u8(); break; |
4040 | 9ee6e8bb | pbrook | case 1: gen_op_neon_rsb_u16(); break; |
4041 | 9ee6e8bb | pbrook | case 2: gen_op_rsbl_T0_T1(); break; |
4042 | 9ee6e8bb | pbrook | default: return 1; |
4043 | 9ee6e8bb | pbrook | } |
4044 | 9ee6e8bb | pbrook | } else { /* VMLA */ |
4045 | 9ee6e8bb | pbrook | gen_neon_add(size); |
4046 | 9ee6e8bb | pbrook | } |
4047 | 9ee6e8bb | pbrook | break;
|
4048 | 9ee6e8bb | pbrook | case 19: /* VMUL */ |
4049 | 9ee6e8bb | pbrook | if (u) { /* polynomial */ |
4050 | 9ee6e8bb | pbrook | gen_op_neon_mul_p8(); |
4051 | 9ee6e8bb | pbrook | } else { /* Integer */ |
4052 | 9ee6e8bb | pbrook | switch (size) {
|
4053 | 9ee6e8bb | pbrook | case 0: gen_op_neon_mul_u8(); break; |
4054 | 9ee6e8bb | pbrook | case 1: gen_op_neon_mul_u16(); break; |
4055 | 9ee6e8bb | pbrook | case 2: gen_op_mul_T0_T1(); break; |
4056 | 9ee6e8bb | pbrook | default: return 1; |
4057 | 9ee6e8bb | pbrook | } |
4058 | 9ee6e8bb | pbrook | } |
4059 | 9ee6e8bb | pbrook | break;
|
4060 | 9ee6e8bb | pbrook | case 20: /* VPMAX */ |
4061 | 9ee6e8bb | pbrook | GEN_NEON_INTEGER_OP(pmax); |
4062 | 9ee6e8bb | pbrook | break;
|
4063 | 9ee6e8bb | pbrook | case 21: /* VPMIN */ |
4064 | 9ee6e8bb | pbrook | GEN_NEON_INTEGER_OP(pmin); |
4065 | 9ee6e8bb | pbrook | break;
|
4066 | 9ee6e8bb | pbrook | case 22: /* Hultiply high. */ |
4067 | 9ee6e8bb | pbrook | if (!u) { /* VQDMULH */ |
4068 | 9ee6e8bb | pbrook | switch (size) {
|
4069 | 9ee6e8bb | pbrook | case 1: gen_op_neon_qdmulh_s16(); break; |
4070 | 9ee6e8bb | pbrook | case 2: gen_op_neon_qdmulh_s32(); break; |
4071 | 9ee6e8bb | pbrook | default: return 1; |
4072 | 9ee6e8bb | pbrook | } |
4073 | 9ee6e8bb | pbrook | } else { /* VQRDHMUL */ |
4074 | 9ee6e8bb | pbrook | switch (size) {
|
4075 | 9ee6e8bb | pbrook | case 1: gen_op_neon_qrdmulh_s16(); break; |
4076 | 9ee6e8bb | pbrook | case 2: gen_op_neon_qrdmulh_s32(); break; |
4077 | 9ee6e8bb | pbrook | default: return 1; |
4078 | 9ee6e8bb | pbrook | } |
4079 | 9ee6e8bb | pbrook | } |
4080 | 9ee6e8bb | pbrook | break;
|
4081 | 9ee6e8bb | pbrook | case 23: /* VPADD */ |
4082 | 9ee6e8bb | pbrook | if (u)
|
4083 | 9ee6e8bb | pbrook | return 1; |
4084 | 9ee6e8bb | pbrook | switch (size) {
|
4085 | 9ee6e8bb | pbrook | case 0: gen_op_neon_padd_u8(); break; |
4086 | 9ee6e8bb | pbrook | case 1: gen_op_neon_padd_u16(); break; |
4087 | 9ee6e8bb | pbrook | case 2: gen_op_addl_T0_T1(); break; |
4088 | 9ee6e8bb | pbrook | default: return 1; |
4089 | 9ee6e8bb | pbrook | } |
4090 | 9ee6e8bb | pbrook | break;
|
4091 | 9ee6e8bb | pbrook | case 26: /* Floating point arithnetic. */ |
4092 | 9ee6e8bb | pbrook | switch ((u << 2) | size) { |
4093 | 9ee6e8bb | pbrook | case 0: /* VADD */ |
4094 | 9ee6e8bb | pbrook | gen_op_neon_add_f32(); |
4095 | 9ee6e8bb | pbrook | break;
|
4096 | 9ee6e8bb | pbrook | case 2: /* VSUB */ |
4097 | 9ee6e8bb | pbrook | gen_op_neon_sub_f32(); |
4098 | 9ee6e8bb | pbrook | break;
|
4099 | 9ee6e8bb | pbrook | case 4: /* VPADD */ |
4100 | 9ee6e8bb | pbrook | gen_op_neon_add_f32(); |
4101 | 9ee6e8bb | pbrook | break;
|
4102 | 9ee6e8bb | pbrook | case 6: /* VABD */ |
4103 | 9ee6e8bb | pbrook | gen_op_neon_abd_f32(); |
4104 | 9ee6e8bb | pbrook | break;
|
4105 | 9ee6e8bb | pbrook | default:
|
4106 | 9ee6e8bb | pbrook | return 1; |
4107 | 9ee6e8bb | pbrook | } |
4108 | 9ee6e8bb | pbrook | break;
|
4109 | 9ee6e8bb | pbrook | case 27: /* Float multiply. */ |
4110 | 9ee6e8bb | pbrook | gen_op_neon_mul_f32(); |
4111 | 9ee6e8bb | pbrook | if (!u) {
|
4112 | 9ee6e8bb | pbrook | NEON_GET_REG(T1, rd, pass); |
4113 | 9ee6e8bb | pbrook | if (size == 0) { |
4114 | 9ee6e8bb | pbrook | gen_op_neon_add_f32(); |
4115 | 9ee6e8bb | pbrook | } else {
|
4116 | 9ee6e8bb | pbrook | gen_op_neon_rsb_f32(); |
4117 | 9ee6e8bb | pbrook | } |
4118 | 9ee6e8bb | pbrook | } |
4119 | 9ee6e8bb | pbrook | break;
|
4120 | 9ee6e8bb | pbrook | case 28: /* Float compare. */ |
4121 | 9ee6e8bb | pbrook | if (!u) {
|
4122 | 9ee6e8bb | pbrook | gen_op_neon_ceq_f32(); |
4123 | b5ff1b31 | bellard | } else {
|
4124 | 9ee6e8bb | pbrook | if (size == 0) |
4125 | 9ee6e8bb | pbrook | gen_op_neon_cge_f32(); |
4126 | 9ee6e8bb | pbrook | else
|
4127 | 9ee6e8bb | pbrook | gen_op_neon_cgt_f32(); |
4128 | b5ff1b31 | bellard | } |
4129 | 2c0262af | bellard | break;
|
4130 | 9ee6e8bb | pbrook | case 29: /* Float compare absolute. */ |
4131 | 9ee6e8bb | pbrook | if (!u)
|
4132 | 9ee6e8bb | pbrook | return 1; |
4133 | 9ee6e8bb | pbrook | if (size == 0) |
4134 | 9ee6e8bb | pbrook | gen_op_neon_acge_f32(); |
4135 | 9ee6e8bb | pbrook | else
|
4136 | 9ee6e8bb | pbrook | gen_op_neon_acgt_f32(); |
4137 | 2c0262af | bellard | break;
|
4138 | 9ee6e8bb | pbrook | case 30: /* Float min/max. */ |
4139 | 9ee6e8bb | pbrook | if (size == 0) |
4140 | 9ee6e8bb | pbrook | gen_op_neon_max_f32(); |
4141 | 9ee6e8bb | pbrook | else
|
4142 | 9ee6e8bb | pbrook | gen_op_neon_min_f32(); |
4143 | 9ee6e8bb | pbrook | break;
|
4144 | 9ee6e8bb | pbrook | case 31: |
4145 | 9ee6e8bb | pbrook | if (size == 0) |
4146 | 4373f3ce | pbrook | gen_helper_recps_f32(cpu_T[0], cpu_T[0], cpu_T[1], cpu_env); |
4147 | 9ee6e8bb | pbrook | else
|
4148 | 4373f3ce | pbrook | gen_helper_rsqrts_f32(cpu_T[0], cpu_T[0], cpu_T[1], cpu_env); |
4149 | 2c0262af | bellard | break;
|
4150 | 9ee6e8bb | pbrook | default:
|
4151 | 9ee6e8bb | pbrook | abort(); |
4152 | 2c0262af | bellard | } |
4153 | 9ee6e8bb | pbrook | /* Save the result. For elementwise operations we can put it
|
4154 | 9ee6e8bb | pbrook | straight into the destination register. For pairwise operations
|
4155 | 9ee6e8bb | pbrook | we have to be careful to avoid clobbering the source operands. */
|
4156 | 9ee6e8bb | pbrook | if (pairwise && rd == rm) {
|
4157 | 9ee6e8bb | pbrook | gen_neon_movl_scratch_T0(pass); |
4158 | 9ee6e8bb | pbrook | } else {
|
4159 | 9ee6e8bb | pbrook | NEON_SET_REG(T0, rd, pass); |
4160 | 9ee6e8bb | pbrook | } |
4161 | 9ee6e8bb | pbrook | |
4162 | 9ee6e8bb | pbrook | } /* for pass */
|
4163 | 9ee6e8bb | pbrook | if (pairwise && rd == rm) {
|
4164 | 9ee6e8bb | pbrook | for (pass = 0; pass < (q ? 4 : 2); pass++) { |
4165 | 9ee6e8bb | pbrook | gen_neon_movl_T0_scratch(pass); |
4166 | 9ee6e8bb | pbrook | NEON_SET_REG(T0, rd, pass); |
4167 | 9ee6e8bb | pbrook | } |
4168 | 9ee6e8bb | pbrook | } |
4169 | 9ee6e8bb | pbrook | } else if (insn & (1 << 4)) { |
4170 | 9ee6e8bb | pbrook | if ((insn & 0x00380080) != 0) { |
4171 | 9ee6e8bb | pbrook | /* Two registers and shift. */
|
4172 | 9ee6e8bb | pbrook | op = (insn >> 8) & 0xf; |
4173 | 9ee6e8bb | pbrook | if (insn & (1 << 7)) { |
4174 | 9ee6e8bb | pbrook | /* 64-bit shift. */
|
4175 | 9ee6e8bb | pbrook | size = 3;
|
4176 | 9ee6e8bb | pbrook | } else {
|
4177 | 9ee6e8bb | pbrook | size = 2;
|
4178 | 9ee6e8bb | pbrook | while ((insn & (1 << (size + 19))) == 0) |
4179 | 9ee6e8bb | pbrook | size--; |
4180 | 9ee6e8bb | pbrook | } |
4181 | 9ee6e8bb | pbrook | shift = (insn >> 16) & ((1 << (3 + size)) - 1); |
4182 | 9ee6e8bb | pbrook | /* To avoid excessive dumplication of ops we implement shift
|
4183 | 9ee6e8bb | pbrook | by immediate using the variable shift operations. */
|
4184 | 9ee6e8bb | pbrook | if (op < 8) { |
4185 | 9ee6e8bb | pbrook | /* Shift by immediate:
|
4186 | 9ee6e8bb | pbrook | VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */
|
4187 | 9ee6e8bb | pbrook | /* Right shifts are encoded as N - shift, where N is the
|
4188 | 9ee6e8bb | pbrook | element size in bits. */
|
4189 | 9ee6e8bb | pbrook | if (op <= 4) |
4190 | 9ee6e8bb | pbrook | shift = shift - (1 << (size + 3)); |
4191 | 9ee6e8bb | pbrook | if (size == 3) { |
4192 | 9ee6e8bb | pbrook | count = q + 1;
|
4193 | 9ee6e8bb | pbrook | } else {
|
4194 | 9ee6e8bb | pbrook | count = q ? 4: 2; |
4195 | 9ee6e8bb | pbrook | } |
4196 | 9ee6e8bb | pbrook | switch (size) {
|
4197 | 9ee6e8bb | pbrook | case 0: |
4198 | 9ee6e8bb | pbrook | imm = (uint8_t) shift; |
4199 | 9ee6e8bb | pbrook | imm |= imm << 8;
|
4200 | 9ee6e8bb | pbrook | imm |= imm << 16;
|
4201 | 9ee6e8bb | pbrook | break;
|
4202 | 9ee6e8bb | pbrook | case 1: |
4203 | 9ee6e8bb | pbrook | imm = (uint16_t) shift; |
4204 | 9ee6e8bb | pbrook | imm |= imm << 16;
|
4205 | 9ee6e8bb | pbrook | break;
|
4206 | 9ee6e8bb | pbrook | case 2: |
4207 | 9ee6e8bb | pbrook | case 3: |
4208 | 9ee6e8bb | pbrook | imm = shift; |
4209 | 9ee6e8bb | pbrook | break;
|
4210 | 9ee6e8bb | pbrook | default:
|
4211 | 9ee6e8bb | pbrook | abort(); |
4212 | 9ee6e8bb | pbrook | } |
4213 | 9ee6e8bb | pbrook | |
4214 | 9ee6e8bb | pbrook | for (pass = 0; pass < count; pass++) { |
4215 | 9ee6e8bb | pbrook | if (size < 3) { |
4216 | 9ee6e8bb | pbrook | /* Operands in T0 and T1. */
|
4217 | 9ee6e8bb | pbrook | gen_op_movl_T1_im(imm); |
4218 | 9ee6e8bb | pbrook | NEON_GET_REG(T0, rm, pass); |
4219 | 2c0262af | bellard | } else {
|
4220 | 9ee6e8bb | pbrook | /* Operands in {T0, T1} and env->vfp.scratch. */
|
4221 | 9ee6e8bb | pbrook | gen_op_movl_T0_im(imm); |
4222 | 9ee6e8bb | pbrook | gen_neon_movl_scratch_T0(0);
|
4223 | 9ee6e8bb | pbrook | gen_op_movl_T0_im((int32_t)imm >> 31);
|
4224 | 9ee6e8bb | pbrook | gen_neon_movl_scratch_T0(1);
|
4225 | 9ee6e8bb | pbrook | NEON_GET_REG(T0, rm, pass * 2);
|
4226 | 9ee6e8bb | pbrook | NEON_GET_REG(T1, rm, pass * 2 + 1); |
4227 | 9ee6e8bb | pbrook | } |
4228 | 9ee6e8bb | pbrook | |
4229 | 9ee6e8bb | pbrook | if (gen_neon_shift_im[op][u][size] == NULL) |
4230 | 9ee6e8bb | pbrook | return 1; |
4231 | 9ee6e8bb | pbrook | gen_neon_shift_im[op][u][size](); |
4232 | 9ee6e8bb | pbrook | |
4233 | 9ee6e8bb | pbrook | if (op == 1 || op == 3) { |
4234 | 9ee6e8bb | pbrook | /* Accumulate. */
|
4235 | 9ee6e8bb | pbrook | if (size == 3) { |
4236 | 9ee6e8bb | pbrook | gen_neon_movl_scratch_T0(0);
|
4237 | 9ee6e8bb | pbrook | gen_neon_movl_scratch_T1(1);
|
4238 | 9ee6e8bb | pbrook | NEON_GET_REG(T0, rd, pass * 2);
|
4239 | 9ee6e8bb | pbrook | NEON_GET_REG(T1, rd, pass * 2 + 1); |
4240 | 9ee6e8bb | pbrook | gen_op_neon_addl_u64(); |
4241 | 9ee6e8bb | pbrook | } else {
|
4242 | 9ee6e8bb | pbrook | NEON_GET_REG(T1, rd, pass); |
4243 | 9ee6e8bb | pbrook | gen_neon_add(size); |
4244 | 99c475ab | bellard | } |
4245 | 9ee6e8bb | pbrook | } else if (op == 4 || (op == 5 && u)) { |
4246 | 9ee6e8bb | pbrook | /* Insert */
|
4247 | 9ee6e8bb | pbrook | if (size == 3) { |
4248 | 9ee6e8bb | pbrook | cpu_abort(env, "VS[LR]I.64 not implemented");
|
4249 | 9ee6e8bb | pbrook | } |
4250 | 9ee6e8bb | pbrook | switch (size) {
|
4251 | 9ee6e8bb | pbrook | case 0: |
4252 | 9ee6e8bb | pbrook | if (op == 4) |
4253 | 9ee6e8bb | pbrook | imm = 0xff >> -shift;
|
4254 | 9ee6e8bb | pbrook | else
|
4255 | 9ee6e8bb | pbrook | imm = (uint8_t)(0xff << shift);
|
4256 | 9ee6e8bb | pbrook | imm |= imm << 8;
|
4257 | 9ee6e8bb | pbrook | imm |= imm << 16;
|
4258 | 9ee6e8bb | pbrook | break;
|
4259 | 9ee6e8bb | pbrook | case 1: |
4260 | 9ee6e8bb | pbrook | if (op == 4) |
4261 | 9ee6e8bb | pbrook | imm = 0xffff >> -shift;
|
4262 | 9ee6e8bb | pbrook | else
|
4263 | 9ee6e8bb | pbrook | imm = (uint16_t)(0xffff << shift);
|
4264 | 9ee6e8bb | pbrook | imm |= imm << 16;
|
4265 | 9ee6e8bb | pbrook | break;
|
4266 | 9ee6e8bb | pbrook | case 2: |
4267 | 9ee6e8bb | pbrook | if (op == 4) |
4268 | 9ee6e8bb | pbrook | imm = 0xffffffffu >> -shift;
|
4269 | 9ee6e8bb | pbrook | else
|
4270 | 9ee6e8bb | pbrook | imm = 0xffffffffu << shift;
|
4271 | 9ee6e8bb | pbrook | break;
|
4272 | 9ee6e8bb | pbrook | default:
|
4273 | 9ee6e8bb | pbrook | abort(); |
4274 | 9ee6e8bb | pbrook | } |
4275 | 8f8e3aa4 | pbrook | tmp = neon_load_reg(rd, pass); |
4276 | 8f8e3aa4 | pbrook | tcg_gen_andi_i32(cpu_T[0], cpu_T[0], imm); |
4277 | 8f8e3aa4 | pbrook | tcg_gen_andi_i32(tmp, tmp, ~imm); |
4278 | 8f8e3aa4 | pbrook | tcg_gen_or_i32(cpu_T[0], cpu_T[0], tmp); |
4279 | 2c0262af | bellard | } |
4280 | 9ee6e8bb | pbrook | if (size == 3) { |
4281 | 9ee6e8bb | pbrook | NEON_SET_REG(T0, rd, pass * 2);
|
4282 | 9ee6e8bb | pbrook | NEON_SET_REG(T1, rd, pass * 2 + 1); |
4283 | 9ee6e8bb | pbrook | } else {
|
4284 | 9ee6e8bb | pbrook | NEON_SET_REG(T0, rd, pass); |
4285 | 9ee6e8bb | pbrook | } |
4286 | 9ee6e8bb | pbrook | } /* for pass */
|
4287 | 9ee6e8bb | pbrook | } else if (op < 10) { |
4288 | 9ee6e8bb | pbrook | /* Shift by immedaiate and narrow:
|
4289 | 9ee6e8bb | pbrook | VSHRN, VRSHRN, VQSHRN, VQRSHRN. */
|
4290 | 9ee6e8bb | pbrook | shift = shift - (1 << (size + 3)); |
4291 | 9ee6e8bb | pbrook | size++; |
4292 | 9ee6e8bb | pbrook | if (size == 3) { |
4293 | 9ee6e8bb | pbrook | count = q + 1;
|
4294 | 2c0262af | bellard | } else {
|
4295 | 9ee6e8bb | pbrook | count = q ? 4: 2; |
4296 | 9ee6e8bb | pbrook | } |
4297 | 9ee6e8bb | pbrook | switch (size) {
|
4298 | 9ee6e8bb | pbrook | case 1: |
4299 | 9ee6e8bb | pbrook | imm = (uint16_t) shift; |
4300 | 9ee6e8bb | pbrook | imm |= imm << 16;
|
4301 | 9ee6e8bb | pbrook | break;
|
4302 | 9ee6e8bb | pbrook | case 2: |
4303 | 9ee6e8bb | pbrook | case 3: |
4304 | 9ee6e8bb | pbrook | imm = shift; |
4305 | 9ee6e8bb | pbrook | break;
|
4306 | 9ee6e8bb | pbrook | default:
|
4307 | 9ee6e8bb | pbrook | abort(); |
4308 | 9ee6e8bb | pbrook | } |
4309 | 9ee6e8bb | pbrook | |
4310 | 9ee6e8bb | pbrook | /* Processing MSB first means we need to do less shuffling at
|
4311 | 9ee6e8bb | pbrook | the end. */
|
4312 | 9ee6e8bb | pbrook | for (pass = count - 1; pass >= 0; pass--) { |
4313 | 9ee6e8bb | pbrook | /* Avoid clobbering the second operand before it has been
|
4314 | 9ee6e8bb | pbrook | written. */
|
4315 | 9ee6e8bb | pbrook | n = pass; |
4316 | 9ee6e8bb | pbrook | if (rd == rm)
|
4317 | 9ee6e8bb | pbrook | n ^= (count - 1);
|
4318 | 9ee6e8bb | pbrook | else
|
4319 | 9ee6e8bb | pbrook | n = pass; |
4320 | 9ee6e8bb | pbrook | |
4321 | 9ee6e8bb | pbrook | if (size < 3) { |
4322 | 9ee6e8bb | pbrook | /* Operands in T0 and T1. */
|
4323 | 9ee6e8bb | pbrook | gen_op_movl_T1_im(imm); |
4324 | 9ee6e8bb | pbrook | NEON_GET_REG(T0, rm, n); |
4325 | 2c0262af | bellard | } else {
|
4326 | 9ee6e8bb | pbrook | /* Operands in {T0, T1} and env->vfp.scratch. */
|
4327 | 9ee6e8bb | pbrook | gen_op_movl_T0_im(imm); |
4328 | 9ee6e8bb | pbrook | gen_neon_movl_scratch_T0(0);
|
4329 | 9ee6e8bb | pbrook | gen_op_movl_T0_im((int32_t)imm >> 31);
|
4330 | 9ee6e8bb | pbrook | gen_neon_movl_scratch_T0(1);
|
4331 | 9ee6e8bb | pbrook | NEON_GET_REG(T0, rm, n * 2);
|
4332 | 9ee6e8bb | pbrook | NEON_GET_REG(T0, rm, n * 2 + 1); |
4333 | 9ee6e8bb | pbrook | } |
4334 | 3b46e624 | ths | |
4335 | 9ee6e8bb | pbrook | gen_neon_shift_im_narrow[q][u][size - 1]();
|
4336 | 9ee6e8bb | pbrook | |
4337 | 9ee6e8bb | pbrook | if (size < 3 && (pass & 1) == 0) { |
4338 | 9ee6e8bb | pbrook | gen_neon_movl_scratch_T0(0);
|
4339 | 9ee6e8bb | pbrook | } else {
|
4340 | 9ee6e8bb | pbrook | uint32_t offset; |
4341 | 9ee6e8bb | pbrook | |
4342 | 9ee6e8bb | pbrook | if (size < 3) |
4343 | 9ee6e8bb | pbrook | gen_neon_movl_T1_scratch(0);
|
4344 | 9ee6e8bb | pbrook | |
4345 | 9ee6e8bb | pbrook | if (op == 8 && !u) { |
4346 | 9ee6e8bb | pbrook | gen_neon_narrow[size - 1]();
|
4347 | 99c475ab | bellard | } else {
|
4348 | 9ee6e8bb | pbrook | if (op == 8) |
4349 | 9ee6e8bb | pbrook | gen_neon_narrow_sats[size - 2]();
|
4350 | 9ee6e8bb | pbrook | else
|
4351 | 9ee6e8bb | pbrook | gen_neon_narrow_satu[size - 1]();
|
4352 | 99c475ab | bellard | } |
4353 | 9ee6e8bb | pbrook | if (size == 3) |
4354 | 9ee6e8bb | pbrook | offset = neon_reg_offset(rd, n); |
4355 | 9ee6e8bb | pbrook | else
|
4356 | 9ee6e8bb | pbrook | offset = neon_reg_offset(rd, n >> 1);
|
4357 | 9ee6e8bb | pbrook | gen_op_neon_setreg_T0(offset); |
4358 | 9ee6e8bb | pbrook | } |
4359 | 9ee6e8bb | pbrook | } /* for pass */
|
4360 | 9ee6e8bb | pbrook | } else if (op == 10) { |
4361 | 9ee6e8bb | pbrook | /* VSHLL */
|
4362 | 9ee6e8bb | pbrook | if (q)
|
4363 | 9ee6e8bb | pbrook | return 1; |
4364 | 9ee6e8bb | pbrook | for (pass = 0; pass < 2; pass++) { |
4365 | 9ee6e8bb | pbrook | /* Avoid clobbering the input operand. */
|
4366 | 9ee6e8bb | pbrook | if (rd == rm)
|
4367 | 9ee6e8bb | pbrook | n = 1 - pass;
|
4368 | 9ee6e8bb | pbrook | else
|
4369 | 9ee6e8bb | pbrook | n = pass; |
4370 | 9ee6e8bb | pbrook | |
4371 | 9ee6e8bb | pbrook | NEON_GET_REG(T0, rm, n); |
4372 | 9ee6e8bb | pbrook | GEN_NEON_INTEGER_OP(widen); |
4373 | 9ee6e8bb | pbrook | if (shift != 0) { |
4374 | 9ee6e8bb | pbrook | /* The shift is less than the width of the source
|
4375 | 9ee6e8bb | pbrook | type, so in some cases we can just
|
4376 | 9ee6e8bb | pbrook | shift the whole register. */
|
4377 | 9ee6e8bb | pbrook | if (size == 1 || (size == 0 && u)) { |
4378 | 9ee6e8bb | pbrook | gen_op_shll_T0_im(shift); |
4379 | 9ee6e8bb | pbrook | gen_op_shll_T1_im(shift); |
4380 | 9ee6e8bb | pbrook | } else {
|
4381 | 9ee6e8bb | pbrook | switch (size) {
|
4382 | 9ee6e8bb | pbrook | case 0: gen_op_neon_shll_u16(shift); break; |
4383 | 9ee6e8bb | pbrook | case 2: gen_op_neon_shll_u64(shift); break; |
4384 | 9ee6e8bb | pbrook | default: abort();
|
4385 | 9ee6e8bb | pbrook | } |
4386 | 9ee6e8bb | pbrook | } |
4387 | 9ee6e8bb | pbrook | } |
4388 | 9ee6e8bb | pbrook | NEON_SET_REG(T0, rd, n * 2);
|
4389 | 9ee6e8bb | pbrook | NEON_SET_REG(T1, rd, n * 2 + 1); |
4390 | 9ee6e8bb | pbrook | } |
4391 | 9ee6e8bb | pbrook | } else if (op == 15 || op == 16) { |
4392 | 9ee6e8bb | pbrook | /* VCVT fixed-point. */
|
4393 | 9ee6e8bb | pbrook | for (pass = 0; pass < (q ? 4 : 2); pass++) { |
4394 | 4373f3ce | pbrook | tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, pass)); |
4395 | 9ee6e8bb | pbrook | if (op & 1) { |
4396 | 9ee6e8bb | pbrook | if (u)
|
4397 | 4373f3ce | pbrook | gen_vfp_ulto(0, shift);
|
4398 | 9ee6e8bb | pbrook | else
|
4399 | 4373f3ce | pbrook | gen_vfp_slto(0, shift);
|
4400 | 9ee6e8bb | pbrook | } else {
|
4401 | 9ee6e8bb | pbrook | if (u)
|
4402 | 4373f3ce | pbrook | gen_vfp_toul(0, shift);
|
4403 | 9ee6e8bb | pbrook | else
|
4404 | 4373f3ce | pbrook | gen_vfp_tosl(0, shift);
|
4405 | 2c0262af | bellard | } |
4406 | 4373f3ce | pbrook | tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, pass)); |
4407 | 2c0262af | bellard | } |
4408 | 2c0262af | bellard | } else {
|
4409 | 9ee6e8bb | pbrook | return 1; |
4410 | 9ee6e8bb | pbrook | } |
4411 | 9ee6e8bb | pbrook | } else { /* (insn & 0x00380080) == 0 */ |
4412 | 9ee6e8bb | pbrook | int invert;
|
4413 | 9ee6e8bb | pbrook | |
4414 | 9ee6e8bb | pbrook | op = (insn >> 8) & 0xf; |
4415 | 9ee6e8bb | pbrook | /* One register and immediate. */
|
4416 | 9ee6e8bb | pbrook | imm = (u << 7) | ((insn >> 12) & 0x70) | (insn & 0xf); |
4417 | 9ee6e8bb | pbrook | invert = (insn & (1 << 5)) != 0; |
4418 | 9ee6e8bb | pbrook | switch (op) {
|
4419 | 9ee6e8bb | pbrook | case 0: case 1: |
4420 | 9ee6e8bb | pbrook | /* no-op */
|
4421 | 9ee6e8bb | pbrook | break;
|
4422 | 9ee6e8bb | pbrook | case 2: case 3: |
4423 | 9ee6e8bb | pbrook | imm <<= 8;
|
4424 | 9ee6e8bb | pbrook | break;
|
4425 | 9ee6e8bb | pbrook | case 4: case 5: |
4426 | 9ee6e8bb | pbrook | imm <<= 16;
|
4427 | 9ee6e8bb | pbrook | break;
|
4428 | 9ee6e8bb | pbrook | case 6: case 7: |
4429 | 9ee6e8bb | pbrook | imm <<= 24;
|
4430 | 9ee6e8bb | pbrook | break;
|
4431 | 9ee6e8bb | pbrook | case 8: case 9: |
4432 | 9ee6e8bb | pbrook | imm |= imm << 16;
|
4433 | 9ee6e8bb | pbrook | break;
|
4434 | 9ee6e8bb | pbrook | case 10: case 11: |
4435 | 9ee6e8bb | pbrook | imm = (imm << 8) | (imm << 24); |
4436 | 9ee6e8bb | pbrook | break;
|
4437 | 9ee6e8bb | pbrook | case 12: |
4438 | 9ee6e8bb | pbrook | imm = (imm < 8) | 0xff; |
4439 | 9ee6e8bb | pbrook | break;
|
4440 | 9ee6e8bb | pbrook | case 13: |
4441 | 9ee6e8bb | pbrook | imm = (imm << 16) | 0xffff; |
4442 | 9ee6e8bb | pbrook | break;
|
4443 | 9ee6e8bb | pbrook | case 14: |
4444 | 9ee6e8bb | pbrook | imm |= (imm << 8) | (imm << 16) | (imm << 24); |
4445 | 9ee6e8bb | pbrook | if (invert)
|
4446 | 9ee6e8bb | pbrook | imm = ~imm; |
4447 | 9ee6e8bb | pbrook | break;
|
4448 | 9ee6e8bb | pbrook | case 15: |
4449 | 9ee6e8bb | pbrook | imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19) |
4450 | 9ee6e8bb | pbrook | | ((imm & 0x40) ? (0x1f << 25) : (1 << 30)); |
4451 | 9ee6e8bb | pbrook | break;
|
4452 | 9ee6e8bb | pbrook | } |
4453 | 9ee6e8bb | pbrook | if (invert)
|
4454 | 9ee6e8bb | pbrook | imm = ~imm; |
4455 | 9ee6e8bb | pbrook | |
4456 | 9ee6e8bb | pbrook | if (op != 14 || !invert) |
4457 | 9ee6e8bb | pbrook | gen_op_movl_T1_im(imm); |
4458 | 9ee6e8bb | pbrook | |
4459 | 9ee6e8bb | pbrook | for (pass = 0; pass < (q ? 4 : 2); pass++) { |
4460 | 9ee6e8bb | pbrook | if (op & 1 && op < 12) { |
4461 | 9ee6e8bb | pbrook | NEON_GET_REG(T0, rd, pass); |
4462 | 9ee6e8bb | pbrook | if (invert) {
|
4463 | 9ee6e8bb | pbrook | /* The immediate value has already been inverted, so
|
4464 | 9ee6e8bb | pbrook | BIC becomes AND. */
|
4465 | 9ee6e8bb | pbrook | gen_op_andl_T0_T1(); |
4466 | 9ee6e8bb | pbrook | } else {
|
4467 | 9ee6e8bb | pbrook | gen_op_orl_T0_T1(); |
4468 | 9ee6e8bb | pbrook | } |
4469 | 9ee6e8bb | pbrook | NEON_SET_REG(T0, rd, pass); |
4470 | 9ee6e8bb | pbrook | } else {
|
4471 | 9ee6e8bb | pbrook | if (op == 14 && invert) { |
4472 | 9ee6e8bb | pbrook | uint32_t tmp; |
4473 | 9ee6e8bb | pbrook | tmp = 0;
|
4474 | 9ee6e8bb | pbrook | for (n = 0; n < 4; n++) { |
4475 | 9ee6e8bb | pbrook | if (imm & (1 << (n + (pass & 1) * 4))) |
4476 | 9ee6e8bb | pbrook | tmp |= 0xff << (n * 8); |
4477 | 9ee6e8bb | pbrook | } |
4478 | 9ee6e8bb | pbrook | gen_op_movl_T1_im(tmp); |
4479 | 9ee6e8bb | pbrook | } |
4480 | 9ee6e8bb | pbrook | /* VMOV, VMVN. */
|
4481 | 9ee6e8bb | pbrook | NEON_SET_REG(T1, rd, pass); |
4482 | 9ee6e8bb | pbrook | } |
4483 | 9ee6e8bb | pbrook | } |
4484 | 9ee6e8bb | pbrook | } |
4485 | 9ee6e8bb | pbrook | } else { /* (insn & 0x00800010 == 0x00800010) */ |
4486 | 9ee6e8bb | pbrook | if (size != 3) { |
4487 | 9ee6e8bb | pbrook | op = (insn >> 8) & 0xf; |
4488 | 9ee6e8bb | pbrook | if ((insn & (1 << 6)) == 0) { |
4489 | 9ee6e8bb | pbrook | /* Three registers of different lengths. */
|
4490 | 9ee6e8bb | pbrook | int src1_wide;
|
4491 | 9ee6e8bb | pbrook | int src2_wide;
|
4492 | 9ee6e8bb | pbrook | int prewiden;
|
4493 | 9ee6e8bb | pbrook | /* prewiden, src1_wide, src2_wide */
|
4494 | 9ee6e8bb | pbrook | static const int neon_3reg_wide[16][3] = { |
4495 | 9ee6e8bb | pbrook | {1, 0, 0}, /* VADDL */ |
4496 | 9ee6e8bb | pbrook | {1, 1, 0}, /* VADDW */ |
4497 | 9ee6e8bb | pbrook | {1, 0, 0}, /* VSUBL */ |
4498 | 9ee6e8bb | pbrook | {1, 1, 0}, /* VSUBW */ |
4499 | 9ee6e8bb | pbrook | {0, 1, 1}, /* VADDHN */ |
4500 | 9ee6e8bb | pbrook | {0, 0, 0}, /* VABAL */ |
4501 | 9ee6e8bb | pbrook | {0, 1, 1}, /* VSUBHN */ |
4502 | 9ee6e8bb | pbrook | {0, 0, 0}, /* VABDL */ |
4503 | 9ee6e8bb | pbrook | {0, 0, 0}, /* VMLAL */ |
4504 | 9ee6e8bb | pbrook | {0, 0, 0}, /* VQDMLAL */ |
4505 | 9ee6e8bb | pbrook | {0, 0, 0}, /* VMLSL */ |
4506 | 9ee6e8bb | pbrook | {0, 0, 0}, /* VQDMLSL */ |
4507 | 9ee6e8bb | pbrook | {0, 0, 0}, /* Integer VMULL */ |
4508 | 9ee6e8bb | pbrook | {0, 0, 0}, /* VQDMULL */ |
4509 | 9ee6e8bb | pbrook | {0, 0, 0} /* Polynomial VMULL */ |
4510 | 9ee6e8bb | pbrook | }; |
4511 | 9ee6e8bb | pbrook | |
4512 | 9ee6e8bb | pbrook | prewiden = neon_3reg_wide[op][0];
|
4513 | 9ee6e8bb | pbrook | src1_wide = neon_3reg_wide[op][1];
|
4514 | 9ee6e8bb | pbrook | src2_wide = neon_3reg_wide[op][2];
|
4515 | 9ee6e8bb | pbrook | |
4516 | 9ee6e8bb | pbrook | /* Avoid overlapping operands. Wide source operands are
|
4517 | 9ee6e8bb | pbrook | always aligned so will never overlap with wide
|
4518 | 9ee6e8bb | pbrook | destinations in problematic ways. */
|
4519 | 8f8e3aa4 | pbrook | if (rd == rm && !src2_wide) {
|
4520 | 8f8e3aa4 | pbrook | NEON_GET_REG(T0, rm, 1);
|
4521 | 8f8e3aa4 | pbrook | gen_neon_movl_scratch_T0(2);
|
4522 | 8f8e3aa4 | pbrook | } else if (rd == rn && !src1_wide) { |
4523 | 8f8e3aa4 | pbrook | NEON_GET_REG(T0, rn, 1);
|
4524 | 8f8e3aa4 | pbrook | gen_neon_movl_scratch_T0(2);
|
4525 | 9ee6e8bb | pbrook | } |
4526 | 9ee6e8bb | pbrook | for (pass = 0; pass < 2; pass++) { |
4527 | 9ee6e8bb | pbrook | /* Load the second operand into env->vfp.scratch.
|
4528 | 9ee6e8bb | pbrook | Also widen narrow operands. */
|
4529 | 8f8e3aa4 | pbrook | if (src2_wide) {
|
4530 | 8f8e3aa4 | pbrook | NEON_GET_REG(T0, rm, pass * 2);
|
4531 | 8f8e3aa4 | pbrook | NEON_GET_REG(T1, rm, pass * 2 + 1); |
4532 | 9ee6e8bb | pbrook | } else {
|
4533 | 8f8e3aa4 | pbrook | if (pass == 1 && rd == rm) { |
4534 | 8f8e3aa4 | pbrook | if (prewiden) {
|
4535 | 8f8e3aa4 | pbrook | gen_neon_movl_T0_scratch(2);
|
4536 | 8f8e3aa4 | pbrook | } else {
|
4537 | 8f8e3aa4 | pbrook | gen_neon_movl_T1_scratch(2);
|
4538 | 8f8e3aa4 | pbrook | } |
4539 | 9ee6e8bb | pbrook | } else {
|
4540 | 9ee6e8bb | pbrook | if (prewiden) {
|
4541 | 9ee6e8bb | pbrook | NEON_GET_REG(T0, rm, pass); |
4542 | 9ee6e8bb | pbrook | } else {
|
4543 | 9ee6e8bb | pbrook | NEON_GET_REG(T1, rm, pass); |
4544 | 9ee6e8bb | pbrook | } |
4545 | 9ee6e8bb | pbrook | } |
4546 | 9ee6e8bb | pbrook | } |
4547 | 9ee6e8bb | pbrook | if (prewiden && !src2_wide) {
|
4548 | 9ee6e8bb | pbrook | GEN_NEON_INTEGER_OP(widen); |
4549 | 9ee6e8bb | pbrook | } |
4550 | 9ee6e8bb | pbrook | if (prewiden || src2_wide) {
|
4551 | 9ee6e8bb | pbrook | gen_neon_movl_scratch_T0(0);
|
4552 | 9ee6e8bb | pbrook | gen_neon_movl_scratch_T1(1);
|
4553 | 9ee6e8bb | pbrook | } |
4554 | 9ee6e8bb | pbrook | |
4555 | 9ee6e8bb | pbrook | /* Load the first operand. */
|
4556 | 8f8e3aa4 | pbrook | if (src1_wide) {
|
4557 | 8f8e3aa4 | pbrook | NEON_GET_REG(T0, rn, pass * 2);
|
4558 | 8f8e3aa4 | pbrook | NEON_GET_REG(T1, rn, pass * 2 + 1); |
4559 | 9ee6e8bb | pbrook | } else {
|
4560 | 8f8e3aa4 | pbrook | if (pass == 1 && rd == rn) { |
4561 | 8f8e3aa4 | pbrook | gen_neon_movl_T0_scratch(2);
|
4562 | 9ee6e8bb | pbrook | } else {
|
4563 | 9ee6e8bb | pbrook | NEON_GET_REG(T0, rn, pass); |
4564 | 9ee6e8bb | pbrook | } |
4565 | 9ee6e8bb | pbrook | } |
4566 | 9ee6e8bb | pbrook | if (prewiden && !src1_wide) {
|
4567 | 9ee6e8bb | pbrook | GEN_NEON_INTEGER_OP(widen); |
4568 | 9ee6e8bb | pbrook | } |
4569 | 9ee6e8bb | pbrook | switch (op) {
|
4570 | 9ee6e8bb | pbrook | case 0: case 1: case 4: /* VADDL, VADDW, VADDHN, VRADDHN */ |
4571 | 9ee6e8bb | pbrook | switch (size) {
|
4572 | 9ee6e8bb | pbrook | case 0: gen_op_neon_addl_u16(); break; |
4573 | 9ee6e8bb | pbrook | case 1: gen_op_neon_addl_u32(); break; |
4574 | 9ee6e8bb | pbrook | case 2: gen_op_neon_addl_u64(); break; |
4575 | 9ee6e8bb | pbrook | default: abort();
|
4576 | 9ee6e8bb | pbrook | } |
4577 | 9ee6e8bb | pbrook | break;
|
4578 | 9ee6e8bb | pbrook | case 2: case 3: case 6: /* VSUBL, VSUBW, VSUBHL, VRSUBHL */ |
4579 | 9ee6e8bb | pbrook | switch (size) {
|
4580 | 9ee6e8bb | pbrook | case 0: gen_op_neon_subl_u16(); break; |
4581 | 9ee6e8bb | pbrook | case 1: gen_op_neon_subl_u32(); break; |
4582 | 9ee6e8bb | pbrook | case 2: gen_op_neon_subl_u64(); break; |
4583 | 9ee6e8bb | pbrook | default: abort();
|
4584 | 9ee6e8bb | pbrook | } |
4585 | 9ee6e8bb | pbrook | break;
|
4586 | 9ee6e8bb | pbrook | case 5: case 7: /* VABAL, VABDL */ |
4587 | 9ee6e8bb | pbrook | switch ((size << 1) | u) { |
4588 | 9ee6e8bb | pbrook | case 0: gen_op_neon_abdl_s16(); break; |
4589 | 9ee6e8bb | pbrook | case 1: gen_op_neon_abdl_u16(); break; |
4590 | 9ee6e8bb | pbrook | case 2: gen_op_neon_abdl_s32(); break; |
4591 | 9ee6e8bb | pbrook | case 3: gen_op_neon_abdl_u32(); break; |
4592 | 9ee6e8bb | pbrook | case 4: gen_op_neon_abdl_s64(); break; |
4593 | 9ee6e8bb | pbrook | case 5: gen_op_neon_abdl_u64(); break; |
4594 | 9ee6e8bb | pbrook | default: abort();
|
4595 | 9ee6e8bb | pbrook | } |
4596 | 9ee6e8bb | pbrook | break;
|
4597 | 9ee6e8bb | pbrook | case 8: case 9: case 10: case 11: case 12: case 13: |
4598 | 9ee6e8bb | pbrook | /* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL */
|
4599 | 9ee6e8bb | pbrook | switch ((size << 1) | u) { |
4600 | 9ee6e8bb | pbrook | case 0: gen_op_neon_mull_s8(); break; |
4601 | 9ee6e8bb | pbrook | case 1: gen_op_neon_mull_u8(); break; |
4602 | 9ee6e8bb | pbrook | case 2: gen_op_neon_mull_s16(); break; |
4603 | 9ee6e8bb | pbrook | case 3: gen_op_neon_mull_u16(); break; |
4604 | 9ee6e8bb | pbrook | case 4: gen_op_imull_T0_T1(); break; |
4605 | 9ee6e8bb | pbrook | case 5: gen_op_mull_T0_T1(); break; |
4606 | 9ee6e8bb | pbrook | default: abort();
|
4607 | 9ee6e8bb | pbrook | } |
4608 | 9ee6e8bb | pbrook | break;
|
4609 | 9ee6e8bb | pbrook | case 14: /* Polynomial VMULL */ |
4610 | 9ee6e8bb | pbrook | cpu_abort(env, "Polynomial VMULL not implemented");
|
4611 | 9ee6e8bb | pbrook | |
4612 | 9ee6e8bb | pbrook | default: /* 15 is RESERVED. */ |
4613 | 9ee6e8bb | pbrook | return 1; |
4614 | 9ee6e8bb | pbrook | } |
4615 | 9ee6e8bb | pbrook | if (op == 5 || op == 13 || (op >= 8 && op <= 11)) { |
4616 | 9ee6e8bb | pbrook | /* Accumulate. */
|
4617 | 9ee6e8bb | pbrook | if (op == 10 || op == 11) { |
4618 | 9ee6e8bb | pbrook | switch (size) {
|
4619 | 9ee6e8bb | pbrook | case 0: gen_op_neon_negl_u16(); break; |
4620 | 9ee6e8bb | pbrook | case 1: gen_op_neon_negl_u32(); break; |
4621 | 9ee6e8bb | pbrook | case 2: gen_op_neon_negl_u64(); break; |
4622 | 9ee6e8bb | pbrook | default: abort();
|
4623 | 9ee6e8bb | pbrook | } |
4624 | 9ee6e8bb | pbrook | } |
4625 | 9ee6e8bb | pbrook | |
4626 | 9ee6e8bb | pbrook | gen_neon_movl_scratch_T0(0);
|
4627 | 9ee6e8bb | pbrook | gen_neon_movl_scratch_T1(1);
|
4628 | 9ee6e8bb | pbrook | |
4629 | 9ee6e8bb | pbrook | if (op != 13) { |
4630 | 9ee6e8bb | pbrook | NEON_GET_REG(T0, rd, pass * 2);
|
4631 | 9ee6e8bb | pbrook | NEON_GET_REG(T1, rd, pass * 2 + 1); |
4632 | 9ee6e8bb | pbrook | } |
4633 | 9ee6e8bb | pbrook | |
4634 | 9ee6e8bb | pbrook | switch (op) {
|
4635 | 9ee6e8bb | pbrook | case 5: case 8: case 10: /* VABAL, VMLAL, VMLSL */ |
4636 | 9ee6e8bb | pbrook | switch (size) {
|
4637 | 9ee6e8bb | pbrook | case 0: gen_op_neon_addl_u16(); break; |
4638 | 9ee6e8bb | pbrook | case 1: gen_op_neon_addl_u32(); break; |
4639 | 9ee6e8bb | pbrook | case 2: gen_op_neon_addl_u64(); break; |
4640 | 9ee6e8bb | pbrook | default: abort();
|
4641 | 9ee6e8bb | pbrook | } |
4642 | 9ee6e8bb | pbrook | break;
|
4643 | 9ee6e8bb | pbrook | case 9: case 11: /* VQDMLAL, VQDMLSL */ |
4644 | 9ee6e8bb | pbrook | switch (size) {
|
4645 | 9ee6e8bb | pbrook | case 1: gen_op_neon_addl_saturate_s32(); break; |
4646 | 9ee6e8bb | pbrook | case 2: gen_op_neon_addl_saturate_s64(); break; |
4647 | 9ee6e8bb | pbrook | default: abort();
|
4648 | 9ee6e8bb | pbrook | } |
4649 | 9ee6e8bb | pbrook | /* Fall through. */
|
4650 | 9ee6e8bb | pbrook | case 13: /* VQDMULL */ |
4651 | 9ee6e8bb | pbrook | switch (size) {
|
4652 | 9ee6e8bb | pbrook | case 1: gen_op_neon_addl_saturate_s32(); break; |
4653 | 9ee6e8bb | pbrook | case 2: gen_op_neon_addl_saturate_s64(); break; |
4654 | 9ee6e8bb | pbrook | default: abort();
|
4655 | 9ee6e8bb | pbrook | } |
4656 | 9ee6e8bb | pbrook | break;
|
4657 | 9ee6e8bb | pbrook | default:
|
4658 | 9ee6e8bb | pbrook | abort(); |
4659 | 9ee6e8bb | pbrook | } |
4660 | 9ee6e8bb | pbrook | NEON_SET_REG(T0, rd, pass * 2);
|
4661 | 9ee6e8bb | pbrook | NEON_SET_REG(T1, rd, pass * 2 + 1); |
4662 | 9ee6e8bb | pbrook | } else if (op == 4 || op == 6) { |
4663 | 9ee6e8bb | pbrook | /* Narrowing operation. */
|
4664 | 9ee6e8bb | pbrook | if (u) {
|
4665 | 9ee6e8bb | pbrook | switch (size) {
|
4666 | 9ee6e8bb | pbrook | case 0: gen_op_neon_narrow_high_u8(); break; |
4667 | 9ee6e8bb | pbrook | case 1: gen_op_neon_narrow_high_u16(); break; |
4668 | 9ee6e8bb | pbrook | case 2: gen_op_movl_T0_T1(); break; |
4669 | 9ee6e8bb | pbrook | default: abort();
|
4670 | 9ee6e8bb | pbrook | } |
4671 | 9ee6e8bb | pbrook | } else {
|
4672 | 9ee6e8bb | pbrook | switch (size) {
|
4673 | 9ee6e8bb | pbrook | case 0: gen_op_neon_narrow_high_round_u8(); break; |
4674 | 9ee6e8bb | pbrook | case 1: gen_op_neon_narrow_high_round_u16(); break; |
4675 | 9ee6e8bb | pbrook | case 2: gen_op_neon_narrow_high_round_u32(); break; |
4676 | 9ee6e8bb | pbrook | default: abort();
|
4677 | 9ee6e8bb | pbrook | } |
4678 | 9ee6e8bb | pbrook | } |
4679 | 9ee6e8bb | pbrook | NEON_SET_REG(T0, rd, pass); |
4680 | 9ee6e8bb | pbrook | } else {
|
4681 | 9ee6e8bb | pbrook | /* Write back the result. */
|
4682 | 9ee6e8bb | pbrook | NEON_SET_REG(T0, rd, pass * 2);
|
4683 | 9ee6e8bb | pbrook | NEON_SET_REG(T1, rd, pass * 2 + 1); |
4684 | 9ee6e8bb | pbrook | } |
4685 | 9ee6e8bb | pbrook | } |
4686 | 9ee6e8bb | pbrook | } else {
|
4687 | 9ee6e8bb | pbrook | /* Two registers and a scalar. */
|
4688 | 9ee6e8bb | pbrook | switch (op) {
|
4689 | 9ee6e8bb | pbrook | case 0: /* Integer VMLA scalar */ |
4690 | 9ee6e8bb | pbrook | case 1: /* Float VMLA scalar */ |
4691 | 9ee6e8bb | pbrook | case 4: /* Integer VMLS scalar */ |
4692 | 9ee6e8bb | pbrook | case 5: /* Floating point VMLS scalar */ |
4693 | 9ee6e8bb | pbrook | case 8: /* Integer VMUL scalar */ |
4694 | 9ee6e8bb | pbrook | case 9: /* Floating point VMUL scalar */ |
4695 | 9ee6e8bb | pbrook | case 12: /* VQDMULH scalar */ |
4696 | 9ee6e8bb | pbrook | case 13: /* VQRDMULH scalar */ |
4697 | 9ee6e8bb | pbrook | gen_neon_get_scalar(size, rm); |
4698 | 8f8e3aa4 | pbrook | gen_neon_movl_scratch_T0(0);
|
4699 | 9ee6e8bb | pbrook | for (pass = 0; pass < (u ? 4 : 2); pass++) { |
4700 | 9ee6e8bb | pbrook | if (pass != 0) |
4701 | 8f8e3aa4 | pbrook | gen_neon_movl_T0_scratch(0);
|
4702 | 9ee6e8bb | pbrook | NEON_GET_REG(T1, rn, pass); |
4703 | 9ee6e8bb | pbrook | if (op == 12) { |
4704 | 9ee6e8bb | pbrook | if (size == 1) { |
4705 | 9ee6e8bb | pbrook | gen_op_neon_qdmulh_s16(); |
4706 | 9ee6e8bb | pbrook | } else {
|
4707 | 9ee6e8bb | pbrook | gen_op_neon_qdmulh_s32(); |
4708 | 9ee6e8bb | pbrook | } |
4709 | 9ee6e8bb | pbrook | } else if (op == 13) { |
4710 | 9ee6e8bb | pbrook | if (size == 1) { |
4711 | 9ee6e8bb | pbrook | gen_op_neon_qrdmulh_s16(); |
4712 | 9ee6e8bb | pbrook | } else {
|
4713 | 9ee6e8bb | pbrook | gen_op_neon_qrdmulh_s32(); |
4714 | 9ee6e8bb | pbrook | } |
4715 | 9ee6e8bb | pbrook | } else if (op & 1) { |
4716 | 9ee6e8bb | pbrook | gen_op_neon_mul_f32(); |
4717 | 9ee6e8bb | pbrook | } else {
|
4718 | 9ee6e8bb | pbrook | switch (size) {
|
4719 | 9ee6e8bb | pbrook | case 0: gen_op_neon_mul_u8(); break; |
4720 | 9ee6e8bb | pbrook | case 1: gen_op_neon_mul_u16(); break; |
4721 | 9ee6e8bb | pbrook | case 2: gen_op_mul_T0_T1(); break; |
4722 | 9ee6e8bb | pbrook | default: return 1; |
4723 | 9ee6e8bb | pbrook | } |
4724 | 9ee6e8bb | pbrook | } |
4725 | 9ee6e8bb | pbrook | if (op < 8) { |
4726 | 9ee6e8bb | pbrook | /* Accumulate. */
|
4727 | 9ee6e8bb | pbrook | NEON_GET_REG(T1, rd, pass); |
4728 | 9ee6e8bb | pbrook | switch (op) {
|
4729 | 9ee6e8bb | pbrook | case 0: |
4730 | 9ee6e8bb | pbrook | gen_neon_add(size); |
4731 | 9ee6e8bb | pbrook | break;
|
4732 | 9ee6e8bb | pbrook | case 1: |
4733 | 9ee6e8bb | pbrook | gen_op_neon_add_f32(); |
4734 | 9ee6e8bb | pbrook | break;
|
4735 | 9ee6e8bb | pbrook | case 4: |
4736 | 9ee6e8bb | pbrook | switch (size) {
|
4737 | 9ee6e8bb | pbrook | case 0: gen_op_neon_rsb_u8(); break; |
4738 | 9ee6e8bb | pbrook | case 1: gen_op_neon_rsb_u16(); break; |
4739 | 9ee6e8bb | pbrook | case 2: gen_op_rsbl_T0_T1(); break; |
4740 | 9ee6e8bb | pbrook | default: return 1; |
4741 | 9ee6e8bb | pbrook | } |
4742 | 9ee6e8bb | pbrook | break;
|
4743 | 9ee6e8bb | pbrook | case 5: |
4744 | 9ee6e8bb | pbrook | gen_op_neon_rsb_f32(); |
4745 | 9ee6e8bb | pbrook | break;
|
4746 | 9ee6e8bb | pbrook | default:
|
4747 | 9ee6e8bb | pbrook | abort(); |
4748 | 9ee6e8bb | pbrook | } |
4749 | 9ee6e8bb | pbrook | } |
4750 | 9ee6e8bb | pbrook | NEON_SET_REG(T0, rd, pass); |
4751 | 9ee6e8bb | pbrook | } |
4752 | 9ee6e8bb | pbrook | break;
|
4753 | 9ee6e8bb | pbrook | case 2: /* VMLAL sclar */ |
4754 | 9ee6e8bb | pbrook | case 3: /* VQDMLAL scalar */ |
4755 | 9ee6e8bb | pbrook | case 6: /* VMLSL scalar */ |
4756 | 9ee6e8bb | pbrook | case 7: /* VQDMLSL scalar */ |
4757 | 9ee6e8bb | pbrook | case 10: /* VMULL scalar */ |
4758 | 9ee6e8bb | pbrook | case 11: /* VQDMULL scalar */ |
4759 | 9ee6e8bb | pbrook | if (rd == rn) {
|
4760 | 9ee6e8bb | pbrook | /* Save overlapping operands before they are
|
4761 | 9ee6e8bb | pbrook | clobbered. */
|
4762 | 9ee6e8bb | pbrook | NEON_GET_REG(T0, rn, 1);
|
4763 | 9ee6e8bb | pbrook | gen_neon_movl_scratch_T0(2);
|
4764 | 9ee6e8bb | pbrook | } |
4765 | 9ee6e8bb | pbrook | gen_neon_get_scalar(size, rm); |
4766 | 8f8e3aa4 | pbrook | gen_neon_movl_scratch_T0(3);
|
4767 | 9ee6e8bb | pbrook | for (pass = 0; pass < 2; pass++) { |
4768 | 9ee6e8bb | pbrook | if (pass != 0) { |
4769 | 8f8e3aa4 | pbrook | gen_neon_movl_T0_scratch(3);
|
4770 | 9ee6e8bb | pbrook | } |
4771 | 9ee6e8bb | pbrook | if (pass != 0 && rd == rn) { |
4772 | 9ee6e8bb | pbrook | gen_neon_movl_T1_scratch(2);
|
4773 | 9ee6e8bb | pbrook | } else {
|
4774 | 9ee6e8bb | pbrook | NEON_GET_REG(T1, rn, pass); |
4775 | 9ee6e8bb | pbrook | } |
4776 | 9ee6e8bb | pbrook | switch ((size << 1) | u) { |
4777 | 9ee6e8bb | pbrook | case 0: gen_op_neon_mull_s8(); break; |
4778 | 9ee6e8bb | pbrook | case 1: gen_op_neon_mull_u8(); break; |
4779 | 9ee6e8bb | pbrook | case 2: gen_op_neon_mull_s16(); break; |
4780 | 9ee6e8bb | pbrook | case 3: gen_op_neon_mull_u16(); break; |
4781 | 9ee6e8bb | pbrook | case 4: gen_op_imull_T0_T1(); break; |
4782 | 9ee6e8bb | pbrook | case 5: gen_op_mull_T0_T1(); break; |
4783 | 9ee6e8bb | pbrook | default: abort();
|
4784 | 9ee6e8bb | pbrook | } |
4785 | 9ee6e8bb | pbrook | if (op == 6 || op == 7) { |
4786 | 9ee6e8bb | pbrook | switch (size) {
|
4787 | 9ee6e8bb | pbrook | case 0: gen_op_neon_negl_u16(); break; |
4788 | 9ee6e8bb | pbrook | case 1: gen_op_neon_negl_u32(); break; |
4789 | 9ee6e8bb | pbrook | case 2: gen_op_neon_negl_u64(); break; |
4790 | 9ee6e8bb | pbrook | default: abort();
|
4791 | 9ee6e8bb | pbrook | } |
4792 | 9ee6e8bb | pbrook | } |
4793 | 9ee6e8bb | pbrook | gen_neon_movl_scratch_T0(0);
|
4794 | 9ee6e8bb | pbrook | gen_neon_movl_scratch_T1(1);
|
4795 | 9ee6e8bb | pbrook | NEON_GET_REG(T0, rd, pass * 2);
|
4796 | 9ee6e8bb | pbrook | NEON_GET_REG(T1, rd, pass * 2 + 1); |
4797 | 9ee6e8bb | pbrook | switch (op) {
|
4798 | 9ee6e8bb | pbrook | case 2: case 6: |
4799 | 9ee6e8bb | pbrook | switch (size) {
|
4800 | 9ee6e8bb | pbrook | case 0: gen_op_neon_addl_u16(); break; |
4801 | 9ee6e8bb | pbrook | case 1: gen_op_neon_addl_u32(); break; |
4802 | 9ee6e8bb | pbrook | case 2: gen_op_neon_addl_u64(); break; |
4803 | 9ee6e8bb | pbrook | default: abort();
|
4804 | 9ee6e8bb | pbrook | } |
4805 | 9ee6e8bb | pbrook | break;
|
4806 | 9ee6e8bb | pbrook | case 3: case 7: |
4807 | 9ee6e8bb | pbrook | switch (size) {
|
4808 | 9ee6e8bb | pbrook | case 1: |
4809 | 9ee6e8bb | pbrook | gen_op_neon_addl_saturate_s32(); |
4810 | 9ee6e8bb | pbrook | gen_op_neon_addl_saturate_s32(); |
4811 | 9ee6e8bb | pbrook | break;
|
4812 | 9ee6e8bb | pbrook | case 2: |
4813 | 9ee6e8bb | pbrook | gen_op_neon_addl_saturate_s64(); |
4814 | 9ee6e8bb | pbrook | gen_op_neon_addl_saturate_s64(); |
4815 | 9ee6e8bb | pbrook | break;
|
4816 | 9ee6e8bb | pbrook | default: abort();
|
4817 | 9ee6e8bb | pbrook | } |
4818 | 9ee6e8bb | pbrook | break;
|
4819 | 9ee6e8bb | pbrook | case 10: |
4820 | 9ee6e8bb | pbrook | /* no-op */
|
4821 | 9ee6e8bb | pbrook | break;
|
4822 | 9ee6e8bb | pbrook | case 11: |
4823 | 9ee6e8bb | pbrook | switch (size) {
|
4824 | 9ee6e8bb | pbrook | case 1: gen_op_neon_addl_saturate_s32(); break; |
4825 | 9ee6e8bb | pbrook | case 2: gen_op_neon_addl_saturate_s64(); break; |
4826 | 9ee6e8bb | pbrook | default: abort();
|
4827 | 9ee6e8bb | pbrook | } |
4828 | 9ee6e8bb | pbrook | break;
|
4829 | 9ee6e8bb | pbrook | default:
|
4830 | 9ee6e8bb | pbrook | abort(); |
4831 | 9ee6e8bb | pbrook | } |
4832 | 9ee6e8bb | pbrook | NEON_SET_REG(T0, rd, pass * 2);
|
4833 | 9ee6e8bb | pbrook | NEON_SET_REG(T1, rd, pass * 2 + 1); |
4834 | 9ee6e8bb | pbrook | } |
4835 | 9ee6e8bb | pbrook | break;
|
4836 | 9ee6e8bb | pbrook | default: /* 14 and 15 are RESERVED */ |
4837 | 9ee6e8bb | pbrook | return 1; |
4838 | 9ee6e8bb | pbrook | } |
4839 | 9ee6e8bb | pbrook | } |
4840 | 9ee6e8bb | pbrook | } else { /* size == 3 */ |
4841 | 9ee6e8bb | pbrook | if (!u) {
|
4842 | 9ee6e8bb | pbrook | /* Extract. */
|
4843 | 9ee6e8bb | pbrook | int reg;
|
4844 | 9ee6e8bb | pbrook | imm = (insn >> 8) & 0xf; |
4845 | 9ee6e8bb | pbrook | reg = rn; |
4846 | 9ee6e8bb | pbrook | count = q ? 4 : 2; |
4847 | 9ee6e8bb | pbrook | n = imm >> 2;
|
4848 | 9ee6e8bb | pbrook | NEON_GET_REG(T0, reg, n); |
4849 | 9ee6e8bb | pbrook | for (pass = 0; pass < count; pass++) { |
4850 | 9ee6e8bb | pbrook | n++; |
4851 | 9ee6e8bb | pbrook | if (n > count) {
|
4852 | 9ee6e8bb | pbrook | reg = rm; |
4853 | 9ee6e8bb | pbrook | n -= count; |
4854 | 9ee6e8bb | pbrook | } |
4855 | 9ee6e8bb | pbrook | if (imm & 3) { |
4856 | 9ee6e8bb | pbrook | NEON_GET_REG(T1, reg, n); |
4857 | 9ee6e8bb | pbrook | gen_op_neon_extract((insn << 3) & 0x1f); |
4858 | 9ee6e8bb | pbrook | } |
4859 | 9ee6e8bb | pbrook | /* ??? This is broken if rd and rm overlap */
|
4860 | 9ee6e8bb | pbrook | NEON_SET_REG(T0, rd, pass); |
4861 | 9ee6e8bb | pbrook | if (imm & 3) { |
4862 | 9ee6e8bb | pbrook | gen_op_movl_T0_T1(); |
4863 | 9ee6e8bb | pbrook | } else {
|
4864 | 9ee6e8bb | pbrook | NEON_GET_REG(T0, reg, n); |
4865 | 9ee6e8bb | pbrook | } |
4866 | 9ee6e8bb | pbrook | } |
4867 | 9ee6e8bb | pbrook | } else if ((insn & (1 << 11)) == 0) { |
4868 | 9ee6e8bb | pbrook | /* Two register misc. */
|
4869 | 9ee6e8bb | pbrook | op = ((insn >> 12) & 0x30) | ((insn >> 7) & 0xf); |
4870 | 9ee6e8bb | pbrook | size = (insn >> 18) & 3; |
4871 | 9ee6e8bb | pbrook | switch (op) {
|
4872 | 9ee6e8bb | pbrook | case 0: /* VREV64 */ |
4873 | 9ee6e8bb | pbrook | if (size == 3) |
4874 | 9ee6e8bb | pbrook | return 1; |
4875 | 9ee6e8bb | pbrook | for (pass = 0; pass < (q ? 2 : 1); pass++) { |
4876 | 9ee6e8bb | pbrook | NEON_GET_REG(T0, rm, pass * 2);
|
4877 | 9ee6e8bb | pbrook | NEON_GET_REG(T1, rm, pass * 2 + 1); |
4878 | 9ee6e8bb | pbrook | switch (size) {
|
4879 | b0109805 | pbrook | case 0: tcg_gen_bswap_i32(cpu_T[0], cpu_T[0]); break; |
4880 | 8f01245e | pbrook | case 1: gen_swap_half(cpu_T[0]); break; |
4881 | 9ee6e8bb | pbrook | case 2: /* no-op */ break; |
4882 | 9ee6e8bb | pbrook | default: abort();
|
4883 | 9ee6e8bb | pbrook | } |
4884 | 9ee6e8bb | pbrook | NEON_SET_REG(T0, rd, pass * 2 + 1); |
4885 | 9ee6e8bb | pbrook | if (size == 2) { |
4886 | 9ee6e8bb | pbrook | NEON_SET_REG(T1, rd, pass * 2);
|
4887 | 9ee6e8bb | pbrook | } else {
|
4888 | 9ee6e8bb | pbrook | gen_op_movl_T0_T1(); |
4889 | 9ee6e8bb | pbrook | switch (size) {
|
4890 | b0109805 | pbrook | case 0: tcg_gen_bswap_i32(cpu_T[0], cpu_T[0]); break; |
4891 | 8f01245e | pbrook | case 1: gen_swap_half(cpu_T[0]); break; |
4892 | 9ee6e8bb | pbrook | default: abort();
|
4893 | 9ee6e8bb | pbrook | } |
4894 | 9ee6e8bb | pbrook | NEON_SET_REG(T0, rd, pass * 2);
|
4895 | 9ee6e8bb | pbrook | } |
4896 | 9ee6e8bb | pbrook | } |
4897 | 9ee6e8bb | pbrook | break;
|
4898 | 9ee6e8bb | pbrook | case 4: case 5: /* VPADDL */ |
4899 | 9ee6e8bb | pbrook | case 12: case 13: /* VPADAL */ |
4900 | 9ee6e8bb | pbrook | if (size < 2) |
4901 | 9ee6e8bb | pbrook | goto elementwise;
|
4902 | 9ee6e8bb | pbrook | if (size == 3) |
4903 | 9ee6e8bb | pbrook | return 1; |
4904 | 9ee6e8bb | pbrook | for (pass = 0; pass < (q ? 2 : 1); pass++) { |
4905 | 9ee6e8bb | pbrook | NEON_GET_REG(T0, rm, pass * 2);
|
4906 | 9ee6e8bb | pbrook | NEON_GET_REG(T1, rm, pass * 2 + 1); |
4907 | 9ee6e8bb | pbrook | if (op & 1) |
4908 | 9ee6e8bb | pbrook | gen_op_neon_paddl_u32(); |
4909 | 9ee6e8bb | pbrook | else
|
4910 | 9ee6e8bb | pbrook | gen_op_neon_paddl_s32(); |
4911 | 9ee6e8bb | pbrook | if (op >= 12) { |
4912 | 9ee6e8bb | pbrook | /* Accumulate. */
|
4913 | 9ee6e8bb | pbrook | gen_neon_movl_scratch_T0(0);
|
4914 | 9ee6e8bb | pbrook | gen_neon_movl_scratch_T1(1);
|
4915 | 9ee6e8bb | pbrook | |
4916 | 9ee6e8bb | pbrook | NEON_GET_REG(T0, rd, pass * 2);
|
4917 | 9ee6e8bb | pbrook | NEON_GET_REG(T1, rd, pass * 2 + 1); |
4918 | 9ee6e8bb | pbrook | gen_op_neon_addl_u64(); |
4919 | 9ee6e8bb | pbrook | } |
4920 | 9ee6e8bb | pbrook | NEON_SET_REG(T0, rd, pass * 2);
|
4921 | 9ee6e8bb | pbrook | NEON_SET_REG(T1, rd, pass * 2 + 1); |
4922 | 9ee6e8bb | pbrook | } |
4923 | 9ee6e8bb | pbrook | break;
|
4924 | 9ee6e8bb | pbrook | case 33: /* VTRN */ |
4925 | 9ee6e8bb | pbrook | if (size == 2) { |
4926 | 9ee6e8bb | pbrook | for (n = 0; n < (q ? 4 : 2); n += 2) { |
4927 | 9ee6e8bb | pbrook | NEON_GET_REG(T0, rm, n); |
4928 | 9ee6e8bb | pbrook | NEON_GET_REG(T1, rd, n + 1);
|
4929 | 9ee6e8bb | pbrook | NEON_SET_REG(T1, rm, n); |
4930 | 9ee6e8bb | pbrook | NEON_SET_REG(T0, rd, n + 1);
|
4931 | 9ee6e8bb | pbrook | } |
4932 | 9ee6e8bb | pbrook | } else {
|
4933 | 9ee6e8bb | pbrook | goto elementwise;
|
4934 | 9ee6e8bb | pbrook | } |
4935 | 9ee6e8bb | pbrook | break;
|
4936 | 9ee6e8bb | pbrook | case 34: /* VUZP */ |
4937 | 9ee6e8bb | pbrook | /* Reg Before After
|
4938 | 9ee6e8bb | pbrook | Rd A3 A2 A1 A0 B2 B0 A2 A0
|
4939 | 9ee6e8bb | pbrook | Rm B3 B2 B1 B0 B3 B1 A3 A1
|
4940 | 9ee6e8bb | pbrook | */
|
4941 | 9ee6e8bb | pbrook | if (size == 3) |
4942 | 9ee6e8bb | pbrook | return 1; |
4943 | 9ee6e8bb | pbrook | gen_neon_unzip(rd, q, 0, size);
|
4944 | 9ee6e8bb | pbrook | gen_neon_unzip(rm, q, 4, size);
|
4945 | 9ee6e8bb | pbrook | if (q) {
|
4946 | 9ee6e8bb | pbrook | static int unzip_order_q[8] = |
4947 | 9ee6e8bb | pbrook | {0, 2, 4, 6, 1, 3, 5, 7}; |
4948 | 9ee6e8bb | pbrook | for (n = 0; n < 8; n++) { |
4949 | 9ee6e8bb | pbrook | int reg = (n < 4) ? rd : rm; |
4950 | 9ee6e8bb | pbrook | gen_neon_movl_T0_scratch(unzip_order_q[n]); |
4951 | 9ee6e8bb | pbrook | NEON_SET_REG(T0, reg, n % 4);
|
4952 | 9ee6e8bb | pbrook | } |
4953 | 9ee6e8bb | pbrook | } else {
|
4954 | 9ee6e8bb | pbrook | static int unzip_order[4] = |
4955 | 9ee6e8bb | pbrook | {0, 4, 1, 5}; |
4956 | 9ee6e8bb | pbrook | for (n = 0; n < 4; n++) { |
4957 | 9ee6e8bb | pbrook | int reg = (n < 2) ? rd : rm; |
4958 | 9ee6e8bb | pbrook | gen_neon_movl_T0_scratch(unzip_order[n]); |
4959 | 9ee6e8bb | pbrook | NEON_SET_REG(T0, reg, n % 2);
|
4960 | 9ee6e8bb | pbrook | } |
4961 | 9ee6e8bb | pbrook | } |
4962 | 9ee6e8bb | pbrook | break;
|
4963 | 9ee6e8bb | pbrook | case 35: /* VZIP */ |
4964 | 9ee6e8bb | pbrook | /* Reg Before After
|
4965 | 9ee6e8bb | pbrook | Rd A3 A2 A1 A0 B1 A1 B0 A0
|
4966 | 9ee6e8bb | pbrook | Rm B3 B2 B1 B0 B3 A3 B2 A2
|
4967 | 9ee6e8bb | pbrook | */
|
4968 | 9ee6e8bb | pbrook | if (size == 3) |
4969 | 9ee6e8bb | pbrook | return 1; |
4970 | 9ee6e8bb | pbrook | count = (q ? 4 : 2); |
4971 | 9ee6e8bb | pbrook | for (n = 0; n < count; n++) { |
4972 | 9ee6e8bb | pbrook | NEON_GET_REG(T0, rd, n); |
4973 | 9ee6e8bb | pbrook | NEON_GET_REG(T1, rd, n); |
4974 | 9ee6e8bb | pbrook | switch (size) {
|
4975 | 9ee6e8bb | pbrook | case 0: gen_op_neon_zip_u8(); break; |
4976 | 9ee6e8bb | pbrook | case 1: gen_op_neon_zip_u16(); break; |
4977 | 9ee6e8bb | pbrook | case 2: /* no-op */; break; |
4978 | 9ee6e8bb | pbrook | default: abort();
|
4979 | 9ee6e8bb | pbrook | } |
4980 | 9ee6e8bb | pbrook | gen_neon_movl_scratch_T0(n * 2);
|
4981 | 9ee6e8bb | pbrook | gen_neon_movl_scratch_T1(n * 2 + 1); |
4982 | 9ee6e8bb | pbrook | } |
4983 | 9ee6e8bb | pbrook | for (n = 0; n < count * 2; n++) { |
4984 | 9ee6e8bb | pbrook | int reg = (n < count) ? rd : rm;
|
4985 | 9ee6e8bb | pbrook | gen_neon_movl_T0_scratch(n); |
4986 | 9ee6e8bb | pbrook | NEON_SET_REG(T0, reg, n % count); |
4987 | 9ee6e8bb | pbrook | } |
4988 | 9ee6e8bb | pbrook | break;
|
4989 | 9ee6e8bb | pbrook | case 36: case 37: /* VMOVN, VQMOVUN, VQMOVN */ |
4990 | 9ee6e8bb | pbrook | for (pass = 0; pass < 2; pass++) { |
4991 | 9ee6e8bb | pbrook | if (rd == rm + 1) { |
4992 | 9ee6e8bb | pbrook | n = 1 - pass;
|
4993 | 9ee6e8bb | pbrook | } else {
|
4994 | 9ee6e8bb | pbrook | n = pass; |
4995 | 9ee6e8bb | pbrook | } |
4996 | 9ee6e8bb | pbrook | NEON_GET_REG(T0, rm, n * 2);
|
4997 | 9ee6e8bb | pbrook | NEON_GET_REG(T1, rm, n * 2 + 1); |
4998 | 9ee6e8bb | pbrook | if (op == 36 && q == 0) { |
4999 | 9ee6e8bb | pbrook | switch (size) {
|
5000 | 9ee6e8bb | pbrook | case 0: gen_op_neon_narrow_u8(); break; |
5001 | 9ee6e8bb | pbrook | case 1: gen_op_neon_narrow_u16(); break; |
5002 | 9ee6e8bb | pbrook | case 2: /* no-op */ break; |
5003 | 9ee6e8bb | pbrook | default: return 1; |
5004 | 9ee6e8bb | pbrook | } |
5005 | 9ee6e8bb | pbrook | } else if (q) { |
5006 | 9ee6e8bb | pbrook | switch (size) {
|
5007 | 9ee6e8bb | pbrook | case 0: gen_op_neon_narrow_sat_u8(); break; |
5008 | 9ee6e8bb | pbrook | case 1: gen_op_neon_narrow_sat_u16(); break; |
5009 | 9ee6e8bb | pbrook | case 2: gen_op_neon_narrow_sat_u32(); break; |
5010 | 9ee6e8bb | pbrook | default: return 1; |
5011 | 9ee6e8bb | pbrook | } |
5012 | 9ee6e8bb | pbrook | } else {
|
5013 | 9ee6e8bb | pbrook | switch (size) {
|
5014 | 9ee6e8bb | pbrook | case 0: gen_op_neon_narrow_sat_s8(); break; |
5015 | 9ee6e8bb | pbrook | case 1: gen_op_neon_narrow_sat_s16(); break; |
5016 | 9ee6e8bb | pbrook | case 2: gen_op_neon_narrow_sat_s32(); break; |
5017 | 9ee6e8bb | pbrook | default: return 1; |
5018 | 9ee6e8bb | pbrook | } |
5019 | 9ee6e8bb | pbrook | } |
5020 | 9ee6e8bb | pbrook | NEON_SET_REG(T0, rd, n); |
5021 | 9ee6e8bb | pbrook | } |
5022 | 9ee6e8bb | pbrook | break;
|
5023 | 9ee6e8bb | pbrook | case 38: /* VSHLL */ |
5024 | 9ee6e8bb | pbrook | if (q)
|
5025 | 9ee6e8bb | pbrook | return 1; |
5026 | 9ee6e8bb | pbrook | if (rm == rd) {
|
5027 | 8f8e3aa4 | pbrook | NEON_GET_REG(T0, rm, 1);
|
5028 | 8f8e3aa4 | pbrook | gen_neon_movl_scratch_T0(0);
|
5029 | 9ee6e8bb | pbrook | } |
5030 | 9ee6e8bb | pbrook | for (pass = 0; pass < 2; pass++) { |
5031 | 9ee6e8bb | pbrook | if (pass == 1 && rm == rd) { |
5032 | 8f8e3aa4 | pbrook | gen_neon_movl_T0_scratch(0);
|
5033 | 9ee6e8bb | pbrook | } else {
|
5034 | 9ee6e8bb | pbrook | NEON_GET_REG(T0, rm, pass); |
5035 | 9ee6e8bb | pbrook | } |
5036 | 9ee6e8bb | pbrook | switch (size) {
|
5037 | 9ee6e8bb | pbrook | case 0: gen_op_neon_widen_high_u8(); break; |
5038 | 9ee6e8bb | pbrook | case 1: gen_op_neon_widen_high_u16(); break; |
5039 | 9ee6e8bb | pbrook | case 2: |
5040 | 9ee6e8bb | pbrook | gen_op_movl_T1_T0(); |
5041 | 9ee6e8bb | pbrook | gen_op_movl_T0_im(0);
|
5042 | 9ee6e8bb | pbrook | break;
|
5043 | 9ee6e8bb | pbrook | default: return 1; |
5044 | 9ee6e8bb | pbrook | } |
5045 | 9ee6e8bb | pbrook | NEON_SET_REG(T0, rd, pass * 2);
|
5046 | 9ee6e8bb | pbrook | NEON_SET_REG(T1, rd, pass * 2 + 1); |
5047 | 9ee6e8bb | pbrook | } |
5048 | 9ee6e8bb | pbrook | break;
|
5049 | 9ee6e8bb | pbrook | default:
|
5050 | 9ee6e8bb | pbrook | elementwise:
|
5051 | 9ee6e8bb | pbrook | for (pass = 0; pass < (q ? 4 : 2); pass++) { |
5052 | 9ee6e8bb | pbrook | if (op == 30 || op == 31 || op >= 58) { |
5053 | 4373f3ce | pbrook | tcg_gen_ld_f32(cpu_F0s, cpu_env, |
5054 | 4373f3ce | pbrook | neon_reg_offset(rm, pass)); |
5055 | 9ee6e8bb | pbrook | } else {
|
5056 | 9ee6e8bb | pbrook | NEON_GET_REG(T0, rm, pass); |
5057 | 9ee6e8bb | pbrook | } |
5058 | 9ee6e8bb | pbrook | switch (op) {
|
5059 | 9ee6e8bb | pbrook | case 1: /* VREV32 */ |
5060 | 9ee6e8bb | pbrook | switch (size) {
|
5061 | b0109805 | pbrook | case 0: tcg_gen_bswap_i32(cpu_T[0], cpu_T[0]); break; |
5062 | 8f01245e | pbrook | case 1: gen_swap_half(cpu_T[0]); break; |
5063 | 9ee6e8bb | pbrook | default: return 1; |
5064 | 9ee6e8bb | pbrook | } |
5065 | 9ee6e8bb | pbrook | break;
|
5066 | 9ee6e8bb | pbrook | case 2: /* VREV16 */ |
5067 | 9ee6e8bb | pbrook | if (size != 0) |
5068 | 9ee6e8bb | pbrook | return 1; |
5069 | 3670669c | pbrook | gen_rev16(cpu_T[0]);
|
5070 | 9ee6e8bb | pbrook | break;
|
5071 | 9ee6e8bb | pbrook | case 4: case 5: /* VPADDL */ |
5072 | 9ee6e8bb | pbrook | case 12: case 13: /* VPADAL */ |
5073 | 9ee6e8bb | pbrook | switch ((size << 1) | (op & 1)) { |
5074 | 9ee6e8bb | pbrook | case 0: gen_op_neon_paddl_s8(); break; |
5075 | 9ee6e8bb | pbrook | case 1: gen_op_neon_paddl_u8(); break; |
5076 | 9ee6e8bb | pbrook | case 2: gen_op_neon_paddl_s16(); break; |
5077 | 9ee6e8bb | pbrook | case 3: gen_op_neon_paddl_u16(); break; |
5078 | 9ee6e8bb | pbrook | default: abort();
|
5079 | 9ee6e8bb | pbrook | } |
5080 | 9ee6e8bb | pbrook | if (op >= 12) { |
5081 | 9ee6e8bb | pbrook | /* Accumulate */
|
5082 | 9ee6e8bb | pbrook | NEON_GET_REG(T1, rd, pass); |
5083 | 9ee6e8bb | pbrook | switch (size) {
|
5084 | 9ee6e8bb | pbrook | case 0: gen_op_neon_add_u16(); break; |
5085 | 9ee6e8bb | pbrook | case 1: gen_op_addl_T0_T1(); break; |
5086 | 9ee6e8bb | pbrook | default: abort();
|
5087 | 9ee6e8bb | pbrook | } |
5088 | 9ee6e8bb | pbrook | } |
5089 | 9ee6e8bb | pbrook | break;
|
5090 | 9ee6e8bb | pbrook | case 8: /* CLS */ |
5091 | 9ee6e8bb | pbrook | switch (size) {
|
5092 | 9ee6e8bb | pbrook | case 0: gen_op_neon_cls_s8(); break; |
5093 | 9ee6e8bb | pbrook | case 1: gen_op_neon_cls_s16(); break; |
5094 | 9ee6e8bb | pbrook | case 2: gen_op_neon_cls_s32(); break; |
5095 | 9ee6e8bb | pbrook | default: return 1; |
5096 | 9ee6e8bb | pbrook | } |
5097 | 9ee6e8bb | pbrook | break;
|
5098 | 9ee6e8bb | pbrook | case 9: /* CLZ */ |
5099 | 9ee6e8bb | pbrook | switch (size) {
|
5100 | 9ee6e8bb | pbrook | case 0: gen_op_neon_clz_u8(); break; |
5101 | 9ee6e8bb | pbrook | case 1: gen_op_neon_clz_u16(); break; |
5102 | 1497c961 | pbrook | case 2: gen_helper_clz(cpu_T[0], cpu_T[0]); break; |
5103 | 9ee6e8bb | pbrook | default: return 1; |
5104 | 9ee6e8bb | pbrook | } |
5105 | 9ee6e8bb | pbrook | break;
|
5106 | 9ee6e8bb | pbrook | case 10: /* CNT */ |
5107 | 9ee6e8bb | pbrook | if (size != 0) |
5108 | 9ee6e8bb | pbrook | return 1; |
5109 | 9ee6e8bb | pbrook | gen_op_neon_cnt_u8(); |
5110 | 9ee6e8bb | pbrook | break;
|
5111 | 9ee6e8bb | pbrook | case 11: /* VNOT */ |
5112 | 9ee6e8bb | pbrook | if (size != 0) |
5113 | 9ee6e8bb | pbrook | return 1; |
5114 | 9ee6e8bb | pbrook | gen_op_notl_T0(); |
5115 | 9ee6e8bb | pbrook | break;
|
5116 | 9ee6e8bb | pbrook | case 14: /* VQABS */ |
5117 | 9ee6e8bb | pbrook | switch (size) {
|
5118 | 9ee6e8bb | pbrook | case 0: gen_op_neon_qabs_s8(); break; |
5119 | 9ee6e8bb | pbrook | case 1: gen_op_neon_qabs_s16(); break; |
5120 | 9ee6e8bb | pbrook | case 2: gen_op_neon_qabs_s32(); break; |
5121 | 9ee6e8bb | pbrook | default: return 1; |
5122 | 9ee6e8bb | pbrook | } |
5123 | 9ee6e8bb | pbrook | break;
|
5124 | 9ee6e8bb | pbrook | case 15: /* VQNEG */ |
5125 | 9ee6e8bb | pbrook | switch (size) {
|
5126 | 9ee6e8bb | pbrook | case 0: gen_op_neon_qneg_s8(); break; |
5127 | 9ee6e8bb | pbrook | case 1: gen_op_neon_qneg_s16(); break; |
5128 | 9ee6e8bb | pbrook | case 2: gen_op_neon_qneg_s32(); break; |
5129 | 9ee6e8bb | pbrook | default: return 1; |
5130 | 9ee6e8bb | pbrook | } |
5131 | 9ee6e8bb | pbrook | break;
|
5132 | 9ee6e8bb | pbrook | case 16: case 19: /* VCGT #0, VCLE #0 */ |
5133 | 9ee6e8bb | pbrook | gen_op_movl_T1_im(0);
|
5134 | 9ee6e8bb | pbrook | switch(size) {
|
5135 | 9ee6e8bb | pbrook | case 0: gen_op_neon_cgt_s8(); break; |
5136 | 9ee6e8bb | pbrook | case 1: gen_op_neon_cgt_s16(); break; |
5137 | 9ee6e8bb | pbrook | case 2: gen_op_neon_cgt_s32(); break; |
5138 | 9ee6e8bb | pbrook | default: return 1; |
5139 | 9ee6e8bb | pbrook | } |
5140 | 9ee6e8bb | pbrook | if (op == 19) |
5141 | 9ee6e8bb | pbrook | gen_op_notl_T0(); |
5142 | 9ee6e8bb | pbrook | break;
|
5143 | 9ee6e8bb | pbrook | case 17: case 20: /* VCGE #0, VCLT #0 */ |
5144 | 9ee6e8bb | pbrook | gen_op_movl_T1_im(0);
|
5145 | 9ee6e8bb | pbrook | switch(size) {
|
5146 | 9ee6e8bb | pbrook | case 0: gen_op_neon_cge_s8(); break; |
5147 | 9ee6e8bb | pbrook | case 1: gen_op_neon_cge_s16(); break; |
5148 | 9ee6e8bb | pbrook | case 2: gen_op_neon_cge_s32(); break; |
5149 | 9ee6e8bb | pbrook | default: return 1; |
5150 | 9ee6e8bb | pbrook | } |
5151 | 9ee6e8bb | pbrook | if (op == 20) |
5152 | 9ee6e8bb | pbrook | gen_op_notl_T0(); |
5153 | 9ee6e8bb | pbrook | break;
|
5154 | 9ee6e8bb | pbrook | case 18: /* VCEQ #0 */ |
5155 | 9ee6e8bb | pbrook | gen_op_movl_T1_im(0);
|
5156 | 9ee6e8bb | pbrook | switch(size) {
|
5157 | 9ee6e8bb | pbrook | case 0: gen_op_neon_ceq_u8(); break; |
5158 | 9ee6e8bb | pbrook | case 1: gen_op_neon_ceq_u16(); break; |
5159 | 9ee6e8bb | pbrook | case 2: gen_op_neon_ceq_u32(); break; |
5160 | 9ee6e8bb | pbrook | default: return 1; |
5161 | 9ee6e8bb | pbrook | } |
5162 | 9ee6e8bb | pbrook | break;
|
5163 | 9ee6e8bb | pbrook | case 22: /* VABS */ |
5164 | 9ee6e8bb | pbrook | switch(size) {
|
5165 | 9ee6e8bb | pbrook | case 0: gen_op_neon_abs_s8(); break; |
5166 | 9ee6e8bb | pbrook | case 1: gen_op_neon_abs_s16(); break; |
5167 | 9ee6e8bb | pbrook | case 2: gen_op_neon_abs_s32(); break; |
5168 | 9ee6e8bb | pbrook | default: return 1; |
5169 | 9ee6e8bb | pbrook | } |
5170 | 9ee6e8bb | pbrook | break;
|
5171 | 9ee6e8bb | pbrook | case 23: /* VNEG */ |
5172 | 9ee6e8bb | pbrook | gen_op_movl_T1_im(0);
|
5173 | 9ee6e8bb | pbrook | switch(size) {
|
5174 | 9ee6e8bb | pbrook | case 0: gen_op_neon_rsb_u8(); break; |
5175 | 9ee6e8bb | pbrook | case 1: gen_op_neon_rsb_u16(); break; |
5176 | 9ee6e8bb | pbrook | case 2: gen_op_rsbl_T0_T1(); break; |
5177 | 9ee6e8bb | pbrook | default: return 1; |
5178 | 9ee6e8bb | pbrook | } |
5179 | 9ee6e8bb | pbrook | break;
|
5180 | 9ee6e8bb | pbrook | case 24: case 27: /* Float VCGT #0, Float VCLE #0 */ |
5181 | 9ee6e8bb | pbrook | gen_op_movl_T1_im(0);
|
5182 | 9ee6e8bb | pbrook | gen_op_neon_cgt_f32(); |
5183 | 9ee6e8bb | pbrook | if (op == 27) |
5184 | 9ee6e8bb | pbrook | gen_op_notl_T0(); |
5185 | 9ee6e8bb | pbrook | break;
|
5186 | 9ee6e8bb | pbrook | case 25: case 28: /* Float VCGE #0, Float VCLT #0 */ |
5187 | 9ee6e8bb | pbrook | gen_op_movl_T1_im(0);
|
5188 | 9ee6e8bb | pbrook | gen_op_neon_cge_f32(); |
5189 | 9ee6e8bb | pbrook | if (op == 28) |
5190 | 9ee6e8bb | pbrook | gen_op_notl_T0(); |
5191 | 9ee6e8bb | pbrook | break;
|
5192 | 9ee6e8bb | pbrook | case 26: /* Float VCEQ #0 */ |
5193 | 9ee6e8bb | pbrook | gen_op_movl_T1_im(0);
|
5194 | 9ee6e8bb | pbrook | gen_op_neon_ceq_f32(); |
5195 | 9ee6e8bb | pbrook | break;
|
5196 | 9ee6e8bb | pbrook | case 30: /* Float VABS */ |
5197 | 4373f3ce | pbrook | gen_vfp_abs(0);
|
5198 | 9ee6e8bb | pbrook | break;
|
5199 | 9ee6e8bb | pbrook | case 31: /* Float VNEG */ |
5200 | 4373f3ce | pbrook | gen_vfp_neg(0);
|
5201 | 9ee6e8bb | pbrook | break;
|
5202 | 9ee6e8bb | pbrook | case 32: /* VSWP */ |
5203 | 9ee6e8bb | pbrook | NEON_GET_REG(T1, rd, pass); |
5204 | 9ee6e8bb | pbrook | NEON_SET_REG(T1, rm, pass); |
5205 | 9ee6e8bb | pbrook | break;
|
5206 | 9ee6e8bb | pbrook | case 33: /* VTRN */ |
5207 | 9ee6e8bb | pbrook | NEON_GET_REG(T1, rd, pass); |
5208 | 9ee6e8bb | pbrook | switch (size) {
|
5209 | 9ee6e8bb | pbrook | case 0: gen_op_neon_trn_u8(); break; |
5210 | 9ee6e8bb | pbrook | case 1: gen_op_neon_trn_u16(); break; |
5211 | 9ee6e8bb | pbrook | case 2: abort(); |
5212 | 9ee6e8bb | pbrook | default: return 1; |
5213 | 9ee6e8bb | pbrook | } |
5214 | 9ee6e8bb | pbrook | NEON_SET_REG(T1, rm, pass); |
5215 | 9ee6e8bb | pbrook | break;
|
5216 | 9ee6e8bb | pbrook | case 56: /* Integer VRECPE */ |
5217 | 4373f3ce | pbrook | gen_helper_recpe_u32(cpu_T[0], cpu_T[0], cpu_env); |
5218 | 9ee6e8bb | pbrook | break;
|
5219 | 9ee6e8bb | pbrook | case 57: /* Integer VRSQRTE */ |
5220 | 4373f3ce | pbrook | gen_helper_rsqrte_u32(cpu_T[0], cpu_T[0], cpu_env); |
5221 | 9ee6e8bb | pbrook | break;
|
5222 | 9ee6e8bb | pbrook | case 58: /* Float VRECPE */ |
5223 | 4373f3ce | pbrook | gen_helper_recpe_f32(cpu_F0s, cpu_F0s, cpu_env); |
5224 | 9ee6e8bb | pbrook | break;
|
5225 | 9ee6e8bb | pbrook | case 59: /* Float VRSQRTE */ |
5226 | 4373f3ce | pbrook | gen_helper_rsqrte_f32(cpu_F0s, cpu_F0s, cpu_env); |
5227 | 9ee6e8bb | pbrook | break;
|
5228 | 9ee6e8bb | pbrook | case 60: /* VCVT.F32.S32 */ |
5229 | 4373f3ce | pbrook | gen_vfp_tosiz(0);
|
5230 | 9ee6e8bb | pbrook | break;
|
5231 | 9ee6e8bb | pbrook | case 61: /* VCVT.F32.U32 */ |
5232 | 4373f3ce | pbrook | gen_vfp_touiz(0);
|
5233 | 9ee6e8bb | pbrook | break;
|
5234 | 9ee6e8bb | pbrook | case 62: /* VCVT.S32.F32 */ |
5235 | 4373f3ce | pbrook | gen_vfp_sito(0);
|
5236 | 9ee6e8bb | pbrook | break;
|
5237 | 9ee6e8bb | pbrook | case 63: /* VCVT.U32.F32 */ |
5238 | 4373f3ce | pbrook | gen_vfp_uito(0);
|
5239 | 9ee6e8bb | pbrook | break;
|
5240 | 9ee6e8bb | pbrook | default:
|
5241 | 9ee6e8bb | pbrook | /* Reserved: 21, 29, 39-56 */
|
5242 | 9ee6e8bb | pbrook | return 1; |
5243 | 9ee6e8bb | pbrook | } |
5244 | 9ee6e8bb | pbrook | if (op == 30 || op == 31 || op >= 58) { |
5245 | 4373f3ce | pbrook | tcg_gen_st_f32(cpu_F0s, cpu_env, |
5246 | 4373f3ce | pbrook | neon_reg_offset(rd, pass)); |
5247 | 9ee6e8bb | pbrook | } else {
|
5248 | 9ee6e8bb | pbrook | NEON_SET_REG(T0, rd, pass); |
5249 | 9ee6e8bb | pbrook | } |
5250 | 9ee6e8bb | pbrook | } |
5251 | 9ee6e8bb | pbrook | break;
|
5252 | 9ee6e8bb | pbrook | } |
5253 | 9ee6e8bb | pbrook | } else if ((insn & (1 << 10)) == 0) { |
5254 | 9ee6e8bb | pbrook | /* VTBL, VTBX. */
|
5255 | 9ee6e8bb | pbrook | n = (insn >> 5) & 0x18; |
5256 | 9ee6e8bb | pbrook | if (insn & (1 << 6)) { |
5257 | 8f8e3aa4 | pbrook | tmp = neon_load_reg(rd, 0);
|
5258 | 9ee6e8bb | pbrook | } else {
|
5259 | 8f8e3aa4 | pbrook | tmp = new_tmp(); |
5260 | 8f8e3aa4 | pbrook | tcg_gen_movi_i32(tmp, 0);
|
5261 | 9ee6e8bb | pbrook | } |
5262 | 8f8e3aa4 | pbrook | tmp2 = neon_load_reg(rm, 0);
|
5263 | 8f8e3aa4 | pbrook | gen_helper_neon_tbl(tmp2, tmp2, tmp, tcg_const_i32(rn), |
5264 | 8f8e3aa4 | pbrook | tcg_const_i32(n)); |
5265 | 9ee6e8bb | pbrook | if (insn & (1 << 6)) { |
5266 | 8f8e3aa4 | pbrook | tmp = neon_load_reg(rd, 1);
|
5267 | 9ee6e8bb | pbrook | } else {
|
5268 | 8f8e3aa4 | pbrook | tmp = new_tmp(); |
5269 | 8f8e3aa4 | pbrook | tcg_gen_movi_i32(tmp, 0);
|
5270 | 9ee6e8bb | pbrook | } |
5271 | 8f8e3aa4 | pbrook | tmp3 = neon_load_reg(rm, 1);
|
5272 | 8f8e3aa4 | pbrook | gen_helper_neon_tbl(tmp3, tmp3, tmp, tcg_const_i32(rn), |
5273 | 8f8e3aa4 | pbrook | tcg_const_i32(n)); |
5274 | 8f8e3aa4 | pbrook | neon_store_reg(rd, 0, tmp2);
|
5275 | 8f8e3aa4 | pbrook | neon_store_reg(rd, 1, tmp2);
|
5276 | 9ee6e8bb | pbrook | } else if ((insn & 0x380) == 0) { |
5277 | 9ee6e8bb | pbrook | /* VDUP */
|
5278 | 9ee6e8bb | pbrook | if (insn & (1 << 19)) { |
5279 | 9ee6e8bb | pbrook | NEON_SET_REG(T0, rm, 1);
|
5280 | 9ee6e8bb | pbrook | } else {
|
5281 | 9ee6e8bb | pbrook | NEON_SET_REG(T0, rm, 0);
|
5282 | 9ee6e8bb | pbrook | } |
5283 | 9ee6e8bb | pbrook | if (insn & (1 << 16)) { |
5284 | 9ee6e8bb | pbrook | gen_op_neon_dup_u8(((insn >> 17) & 3) * 8); |
5285 | 9ee6e8bb | pbrook | } else if (insn & (1 << 17)) { |
5286 | 9ee6e8bb | pbrook | if ((insn >> 18) & 1) |
5287 | 9ee6e8bb | pbrook | gen_op_neon_dup_high16(); |
5288 | 9ee6e8bb | pbrook | else
|
5289 | 9ee6e8bb | pbrook | gen_op_neon_dup_low16(); |
5290 | 9ee6e8bb | pbrook | } |
5291 | 9ee6e8bb | pbrook | for (pass = 0; pass < (q ? 4 : 2); pass++) { |
5292 | 9ee6e8bb | pbrook | NEON_SET_REG(T0, rd, pass); |
5293 | 9ee6e8bb | pbrook | } |
5294 | 9ee6e8bb | pbrook | } else {
|
5295 | 9ee6e8bb | pbrook | return 1; |
5296 | 9ee6e8bb | pbrook | } |
5297 | 9ee6e8bb | pbrook | } |
5298 | 9ee6e8bb | pbrook | } |
5299 | 9ee6e8bb | pbrook | return 0; |
5300 | 9ee6e8bb | pbrook | } |
5301 | 9ee6e8bb | pbrook | |
5302 | 9ee6e8bb | pbrook | static int disas_coproc_insn(CPUState * env, DisasContext *s, uint32_t insn) |
5303 | 9ee6e8bb | pbrook | { |
5304 | 9ee6e8bb | pbrook | int cpnum;
|
5305 | 9ee6e8bb | pbrook | |
5306 | 9ee6e8bb | pbrook | cpnum = (insn >> 8) & 0xf; |
5307 | 9ee6e8bb | pbrook | if (arm_feature(env, ARM_FEATURE_XSCALE)
|
5308 | 9ee6e8bb | pbrook | && ((env->cp15.c15_cpar ^ 0x3fff) & (1 << cpnum))) |
5309 | 9ee6e8bb | pbrook | return 1; |
5310 | 9ee6e8bb | pbrook | |
5311 | 9ee6e8bb | pbrook | switch (cpnum) {
|
5312 | 9ee6e8bb | pbrook | case 0: |
5313 | 9ee6e8bb | pbrook | case 1: |
5314 | 9ee6e8bb | pbrook | if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
|
5315 | 9ee6e8bb | pbrook | return disas_iwmmxt_insn(env, s, insn);
|
5316 | 9ee6e8bb | pbrook | } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { |
5317 | 9ee6e8bb | pbrook | return disas_dsp_insn(env, s, insn);
|
5318 | 9ee6e8bb | pbrook | } |
5319 | 9ee6e8bb | pbrook | return 1; |
5320 | 9ee6e8bb | pbrook | case 10: |
5321 | 9ee6e8bb | pbrook | case 11: |
5322 | 9ee6e8bb | pbrook | return disas_vfp_insn (env, s, insn);
|
5323 | 9ee6e8bb | pbrook | case 15: |
5324 | 9ee6e8bb | pbrook | return disas_cp15_insn (env, s, insn);
|
5325 | 9ee6e8bb | pbrook | default:
|
5326 | 9ee6e8bb | pbrook | /* Unknown coprocessor. See if the board has hooked it. */
|
5327 | 9ee6e8bb | pbrook | return disas_cp_insn (env, s, insn);
|
5328 | 9ee6e8bb | pbrook | } |
5329 | 9ee6e8bb | pbrook | } |
5330 | 9ee6e8bb | pbrook | |
5331 | 5e3f878a | pbrook | |
5332 | 5e3f878a | pbrook | /* Store a 64-bit value to a register pair. Clobbers val. */
|
5333 | 5e3f878a | pbrook | static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv val) |
5334 | 5e3f878a | pbrook | { |
5335 | 5e3f878a | pbrook | TCGv tmp; |
5336 | 5e3f878a | pbrook | tmp = new_tmp(); |
5337 | 5e3f878a | pbrook | tcg_gen_trunc_i64_i32(tmp, val); |
5338 | 5e3f878a | pbrook | store_reg(s, rlow, tmp); |
5339 | 5e3f878a | pbrook | tmp = new_tmp(); |
5340 | 5e3f878a | pbrook | tcg_gen_shri_i64(val, val, 32);
|
5341 | 5e3f878a | pbrook | tcg_gen_trunc_i64_i32(tmp, val); |
5342 | 5e3f878a | pbrook | store_reg(s, rhigh, tmp); |
5343 | 5e3f878a | pbrook | } |
5344 | 5e3f878a | pbrook | |
5345 | 5e3f878a | pbrook | /* load a 32-bit value from a register and perform a 64-bit accumulate. */
|
5346 | 5e3f878a | pbrook | static void gen_addq_lo(DisasContext *s, TCGv val, int rlow) |
5347 | 5e3f878a | pbrook | { |
5348 | 5e3f878a | pbrook | TCGv tmp; |
5349 | 5e3f878a | pbrook | TCGv tmp2; |
5350 | 5e3f878a | pbrook | |
5351 | 5e3f878a | pbrook | /* Load 64-bit value rd:rn. */
|
5352 | 5e3f878a | pbrook | tmp = tcg_temp_new(TCG_TYPE_I64); |
5353 | 5e3f878a | pbrook | tmp2 = load_reg(s, rlow); |
5354 | 5e3f878a | pbrook | tcg_gen_extu_i32_i64(tmp, tmp2); |
5355 | 5e3f878a | pbrook | dead_tmp(tmp2); |
5356 | 5e3f878a | pbrook | tcg_gen_add_i64(val, val, tmp); |
5357 | 5e3f878a | pbrook | } |
5358 | 5e3f878a | pbrook | |
5359 | 5e3f878a | pbrook | /* load and add a 64-bit value from a register pair. */
|
5360 | 5e3f878a | pbrook | static void gen_addq(DisasContext *s, TCGv val, int rlow, int rhigh) |
5361 | 5e3f878a | pbrook | { |
5362 | 5e3f878a | pbrook | TCGv tmp; |
5363 | 5e3f878a | pbrook | TCGv tmp2; |
5364 | 5e3f878a | pbrook | |
5365 | 5e3f878a | pbrook | /* Load 64-bit value rd:rn. */
|
5366 | 5e3f878a | pbrook | tmp = tcg_temp_new(TCG_TYPE_I64); |
5367 | 5e3f878a | pbrook | tmp2 = load_reg(s, rhigh); |
5368 | 5e3f878a | pbrook | tcg_gen_extu_i32_i64(tmp, tmp2); |
5369 | 5e3f878a | pbrook | dead_tmp(tmp2); |
5370 | 5e3f878a | pbrook | tcg_gen_shli_i64(tmp, tmp, 32);
|
5371 | 5e3f878a | pbrook | tcg_gen_add_i64(val, val, tmp); |
5372 | 5e3f878a | pbrook | |
5373 | 5e3f878a | pbrook | tmp2 = load_reg(s, rlow); |
5374 | 5e3f878a | pbrook | tcg_gen_extu_i32_i64(tmp, tmp2); |
5375 | 5e3f878a | pbrook | dead_tmp(tmp2); |
5376 | 5e3f878a | pbrook | tcg_gen_add_i64(val, val, tmp); |
5377 | 5e3f878a | pbrook | } |
5378 | 5e3f878a | pbrook | |
5379 | 5e3f878a | pbrook | /* Set N and Z flags from a 64-bit value. */
|
5380 | 5e3f878a | pbrook | static void gen_logicq_cc(TCGv val) |
5381 | 5e3f878a | pbrook | { |
5382 | 5e3f878a | pbrook | TCGv tmp = new_tmp(); |
5383 | 5e3f878a | pbrook | gen_helper_logicq_cc(tmp, val); |
5384 | 5e3f878a | pbrook | store_cpu_field(tmp, NZF); |
5385 | 5e3f878a | pbrook | } |
5386 | 5e3f878a | pbrook | |
5387 | 9ee6e8bb | pbrook | static void disas_arm_insn(CPUState * env, DisasContext *s) |
5388 | 9ee6e8bb | pbrook | { |
5389 | 9ee6e8bb | pbrook | unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh; |
5390 | b26eefb6 | pbrook | TCGv tmp; |
5391 | 3670669c | pbrook | TCGv tmp2; |
5392 | 6ddbc6e4 | pbrook | TCGv tmp3; |
5393 | b0109805 | pbrook | TCGv addr; |
5394 | 9ee6e8bb | pbrook | |
5395 | 9ee6e8bb | pbrook | insn = ldl_code(s->pc); |
5396 | 9ee6e8bb | pbrook | s->pc += 4;
|
5397 | 9ee6e8bb | pbrook | |
5398 | 9ee6e8bb | pbrook | /* M variants do not implement ARM mode. */
|
5399 | 9ee6e8bb | pbrook | if (IS_M(env))
|
5400 | 9ee6e8bb | pbrook | goto illegal_op;
|
5401 | 9ee6e8bb | pbrook | cond = insn >> 28;
|
5402 | 9ee6e8bb | pbrook | if (cond == 0xf){ |
5403 | 9ee6e8bb | pbrook | /* Unconditional instructions. */
|
5404 | 9ee6e8bb | pbrook | if (((insn >> 25) & 7) == 1) { |
5405 | 9ee6e8bb | pbrook | /* NEON Data processing. */
|
5406 | 9ee6e8bb | pbrook | if (!arm_feature(env, ARM_FEATURE_NEON))
|
5407 | 9ee6e8bb | pbrook | goto illegal_op;
|
5408 | 9ee6e8bb | pbrook | |
5409 | 9ee6e8bb | pbrook | if (disas_neon_data_insn(env, s, insn))
|
5410 | 9ee6e8bb | pbrook | goto illegal_op;
|
5411 | 9ee6e8bb | pbrook | return;
|
5412 | 9ee6e8bb | pbrook | } |
5413 | 9ee6e8bb | pbrook | if ((insn & 0x0f100000) == 0x04000000) { |
5414 | 9ee6e8bb | pbrook | /* NEON load/store. */
|
5415 | 9ee6e8bb | pbrook | if (!arm_feature(env, ARM_FEATURE_NEON))
|
5416 | 9ee6e8bb | pbrook | goto illegal_op;
|
5417 | 9ee6e8bb | pbrook | |
5418 | 9ee6e8bb | pbrook | if (disas_neon_ls_insn(env, s, insn))
|
5419 | 9ee6e8bb | pbrook | goto illegal_op;
|
5420 | 9ee6e8bb | pbrook | return;
|
5421 | 9ee6e8bb | pbrook | } |
5422 | 9ee6e8bb | pbrook | if ((insn & 0x0d70f000) == 0x0550f000) |
5423 | 9ee6e8bb | pbrook | return; /* PLD */ |
5424 | 9ee6e8bb | pbrook | else if ((insn & 0x0ffffdff) == 0x01010000) { |
5425 | 9ee6e8bb | pbrook | ARCH(6);
|
5426 | 9ee6e8bb | pbrook | /* setend */
|
5427 | 9ee6e8bb | pbrook | if (insn & (1 << 9)) { |
5428 | 9ee6e8bb | pbrook | /* BE8 mode not implemented. */
|
5429 | 9ee6e8bb | pbrook | goto illegal_op;
|
5430 | 9ee6e8bb | pbrook | } |
5431 | 9ee6e8bb | pbrook | return;
|
5432 | 9ee6e8bb | pbrook | } else if ((insn & 0x0fffff00) == 0x057ff000) { |
5433 | 9ee6e8bb | pbrook | switch ((insn >> 4) & 0xf) { |
5434 | 9ee6e8bb | pbrook | case 1: /* clrex */ |
5435 | 9ee6e8bb | pbrook | ARCH(6K);
|
5436 | 8f8e3aa4 | pbrook | gen_helper_clrex(cpu_env); |
5437 | 9ee6e8bb | pbrook | return;
|
5438 | 9ee6e8bb | pbrook | case 4: /* dsb */ |
5439 | 9ee6e8bb | pbrook | case 5: /* dmb */ |
5440 | 9ee6e8bb | pbrook | case 6: /* isb */ |
5441 | 9ee6e8bb | pbrook | ARCH(7);
|
5442 | 9ee6e8bb | pbrook | /* We don't emulate caches so these are a no-op. */
|
5443 | 9ee6e8bb | pbrook | return;
|
5444 | 9ee6e8bb | pbrook | default:
|
5445 | 9ee6e8bb | pbrook | goto illegal_op;
|
5446 | 9ee6e8bb | pbrook | } |
5447 | 9ee6e8bb | pbrook | } else if ((insn & 0x0e5fffe0) == 0x084d0500) { |
5448 | 9ee6e8bb | pbrook | /* srs */
|
5449 | 9ee6e8bb | pbrook | uint32_t offset; |
5450 | 9ee6e8bb | pbrook | if (IS_USER(s))
|
5451 | 9ee6e8bb | pbrook | goto illegal_op;
|
5452 | 9ee6e8bb | pbrook | ARCH(6);
|
5453 | 9ee6e8bb | pbrook | op1 = (insn & 0x1f);
|
5454 | 9ee6e8bb | pbrook | if (op1 == (env->uncached_cpsr & CPSR_M)) {
|
5455 | b0109805 | pbrook | addr = load_reg(s, 13);
|
5456 | 9ee6e8bb | pbrook | } else {
|
5457 | b0109805 | pbrook | addr = new_tmp(); |
5458 | b0109805 | pbrook | gen_helper_get_r13_banked(addr, cpu_env, tcg_const_i32(op1)); |
5459 | 9ee6e8bb | pbrook | } |
5460 | 9ee6e8bb | pbrook | i = (insn >> 23) & 3; |
5461 | 9ee6e8bb | pbrook | switch (i) {
|
5462 | 9ee6e8bb | pbrook | case 0: offset = -4; break; /* DA */ |
5463 | 9ee6e8bb | pbrook | case 1: offset = -8; break; /* DB */ |
5464 | 9ee6e8bb | pbrook | case 2: offset = 0; break; /* IA */ |
5465 | 9ee6e8bb | pbrook | case 3: offset = 4; break; /* IB */ |
5466 | 9ee6e8bb | pbrook | default: abort();
|
5467 | 9ee6e8bb | pbrook | } |
5468 | 9ee6e8bb | pbrook | if (offset)
|
5469 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, offset); |
5470 | b0109805 | pbrook | tmp = load_reg(s, 14);
|
5471 | b0109805 | pbrook | gen_st32(tmp, addr, 0);
|
5472 | b0109805 | pbrook | tmp = new_tmp(); |
5473 | b0109805 | pbrook | gen_helper_cpsr_read(tmp); |
5474 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, 4);
|
5475 | b0109805 | pbrook | gen_st32(tmp, addr, 0);
|
5476 | 9ee6e8bb | pbrook | if (insn & (1 << 21)) { |
5477 | 9ee6e8bb | pbrook | /* Base writeback. */
|
5478 | 9ee6e8bb | pbrook | switch (i) {
|
5479 | 9ee6e8bb | pbrook | case 0: offset = -8; break; |
5480 | 9ee6e8bb | pbrook | case 1: offset = -4; break; |
5481 | 9ee6e8bb | pbrook | case 2: offset = 4; break; |
5482 | 9ee6e8bb | pbrook | case 3: offset = 0; break; |
5483 | 9ee6e8bb | pbrook | default: abort();
|
5484 | 9ee6e8bb | pbrook | } |
5485 | 9ee6e8bb | pbrook | if (offset)
|
5486 | b0109805 | pbrook | tcg_gen_addi_i32(addr, tmp, offset); |
5487 | 9ee6e8bb | pbrook | if (op1 == (env->uncached_cpsr & CPSR_M)) {
|
5488 | 9ee6e8bb | pbrook | gen_movl_reg_T1(s, 13);
|
5489 | 9ee6e8bb | pbrook | } else {
|
5490 | b0109805 | pbrook | gen_helper_set_r13_banked(cpu_env, tcg_const_i32(op1), cpu_T[1]);
|
5491 | 9ee6e8bb | pbrook | } |
5492 | b0109805 | pbrook | } else {
|
5493 | b0109805 | pbrook | dead_tmp(addr); |
5494 | 9ee6e8bb | pbrook | } |
5495 | 9ee6e8bb | pbrook | } else if ((insn & 0x0e5fffe0) == 0x081d0a00) { |
5496 | 9ee6e8bb | pbrook | /* rfe */
|
5497 | 9ee6e8bb | pbrook | uint32_t offset; |
5498 | 9ee6e8bb | pbrook | if (IS_USER(s))
|
5499 | 9ee6e8bb | pbrook | goto illegal_op;
|
5500 | 9ee6e8bb | pbrook | ARCH(6);
|
5501 | 9ee6e8bb | pbrook | rn = (insn >> 16) & 0xf; |
5502 | b0109805 | pbrook | addr = load_reg(s, rn); |
5503 | 9ee6e8bb | pbrook | i = (insn >> 23) & 3; |
5504 | 9ee6e8bb | pbrook | switch (i) {
|
5505 | b0109805 | pbrook | case 0: offset = -4; break; /* DA */ |
5506 | b0109805 | pbrook | case 1: offset = -8; break; /* DB */ |
5507 | b0109805 | pbrook | case 2: offset = 0; break; /* IA */ |
5508 | b0109805 | pbrook | case 3: offset = 4; break; /* IB */ |
5509 | 9ee6e8bb | pbrook | default: abort();
|
5510 | 9ee6e8bb | pbrook | } |
5511 | 9ee6e8bb | pbrook | if (offset)
|
5512 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, offset); |
5513 | b0109805 | pbrook | /* Load PC into tmp and CPSR into tmp2. */
|
5514 | b0109805 | pbrook | tmp = gen_ld32(addr, 0);
|
5515 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, 4);
|
5516 | b0109805 | pbrook | tmp2 = gen_ld32(addr, 0);
|
5517 | 9ee6e8bb | pbrook | if (insn & (1 << 21)) { |
5518 | 9ee6e8bb | pbrook | /* Base writeback. */
|
5519 | 9ee6e8bb | pbrook | switch (i) {
|
5520 | b0109805 | pbrook | case 0: offset = -8; break; |
5521 | b0109805 | pbrook | case 1: offset = -4; break; |
5522 | b0109805 | pbrook | case 2: offset = 4; break; |
5523 | b0109805 | pbrook | case 3: offset = 0; break; |
5524 | 9ee6e8bb | pbrook | default: abort();
|
5525 | 9ee6e8bb | pbrook | } |
5526 | 9ee6e8bb | pbrook | if (offset)
|
5527 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, offset); |
5528 | b0109805 | pbrook | store_reg(s, rn, addr); |
5529 | b0109805 | pbrook | } else {
|
5530 | b0109805 | pbrook | dead_tmp(addr); |
5531 | 9ee6e8bb | pbrook | } |
5532 | b0109805 | pbrook | gen_rfe(s, tmp, tmp2); |
5533 | 9ee6e8bb | pbrook | } else if ((insn & 0x0e000000) == 0x0a000000) { |
5534 | 9ee6e8bb | pbrook | /* branch link and change to thumb (blx <offset>) */
|
5535 | 9ee6e8bb | pbrook | int32_t offset; |
5536 | 9ee6e8bb | pbrook | |
5537 | 9ee6e8bb | pbrook | val = (uint32_t)s->pc; |
5538 | d9ba4830 | pbrook | tmp = new_tmp(); |
5539 | d9ba4830 | pbrook | tcg_gen_movi_i32(tmp, val); |
5540 | d9ba4830 | pbrook | store_reg(s, 14, tmp);
|
5541 | 9ee6e8bb | pbrook | /* Sign-extend the 24-bit offset */
|
5542 | 9ee6e8bb | pbrook | offset = (((int32_t)insn) << 8) >> 8; |
5543 | 9ee6e8bb | pbrook | /* offset * 4 + bit24 * 2 + (thumb bit) */
|
5544 | 9ee6e8bb | pbrook | val += (offset << 2) | ((insn >> 23) & 2) | 1; |
5545 | 9ee6e8bb | pbrook | /* pipeline offset */
|
5546 | 9ee6e8bb | pbrook | val += 4;
|
5547 | d9ba4830 | pbrook | gen_bx_im(s, val); |
5548 | 9ee6e8bb | pbrook | return;
|
5549 | 9ee6e8bb | pbrook | } else if ((insn & 0x0e000f00) == 0x0c000100) { |
5550 | 9ee6e8bb | pbrook | if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
|
5551 | 9ee6e8bb | pbrook | /* iWMMXt register transfer. */
|
5552 | 9ee6e8bb | pbrook | if (env->cp15.c15_cpar & (1 << 1)) |
5553 | 9ee6e8bb | pbrook | if (!disas_iwmmxt_insn(env, s, insn))
|
5554 | 9ee6e8bb | pbrook | return;
|
5555 | 9ee6e8bb | pbrook | } |
5556 | 9ee6e8bb | pbrook | } else if ((insn & 0x0fe00000) == 0x0c400000) { |
5557 | 9ee6e8bb | pbrook | /* Coprocessor double register transfer. */
|
5558 | 9ee6e8bb | pbrook | } else if ((insn & 0x0f000010) == 0x0e000010) { |
5559 | 9ee6e8bb | pbrook | /* Additional coprocessor register transfer. */
|
5560 | 9ee6e8bb | pbrook | } else if ((insn & 0x0ff10010) == 0x01000000) { |
5561 | 9ee6e8bb | pbrook | uint32_t mask; |
5562 | 9ee6e8bb | pbrook | uint32_t val; |
5563 | 9ee6e8bb | pbrook | /* cps (privileged) */
|
5564 | 9ee6e8bb | pbrook | if (IS_USER(s))
|
5565 | 9ee6e8bb | pbrook | return;
|
5566 | 9ee6e8bb | pbrook | mask = val = 0;
|
5567 | 9ee6e8bb | pbrook | if (insn & (1 << 19)) { |
5568 | 9ee6e8bb | pbrook | if (insn & (1 << 8)) |
5569 | 9ee6e8bb | pbrook | mask |= CPSR_A; |
5570 | 9ee6e8bb | pbrook | if (insn & (1 << 7)) |
5571 | 9ee6e8bb | pbrook | mask |= CPSR_I; |
5572 | 9ee6e8bb | pbrook | if (insn & (1 << 6)) |
5573 | 9ee6e8bb | pbrook | mask |= CPSR_F; |
5574 | 9ee6e8bb | pbrook | if (insn & (1 << 18)) |
5575 | 9ee6e8bb | pbrook | val |= mask; |
5576 | 9ee6e8bb | pbrook | } |
5577 | 9ee6e8bb | pbrook | if (insn & (1 << 14)) { |
5578 | 9ee6e8bb | pbrook | mask |= CPSR_M; |
5579 | 9ee6e8bb | pbrook | val |= (insn & 0x1f);
|
5580 | 9ee6e8bb | pbrook | } |
5581 | 9ee6e8bb | pbrook | if (mask) {
|
5582 | 9ee6e8bb | pbrook | gen_op_movl_T0_im(val); |
5583 | 9ee6e8bb | pbrook | gen_set_psr_T0(s, mask, 0);
|
5584 | 9ee6e8bb | pbrook | } |
5585 | 9ee6e8bb | pbrook | return;
|
5586 | 9ee6e8bb | pbrook | } |
5587 | 9ee6e8bb | pbrook | goto illegal_op;
|
5588 | 9ee6e8bb | pbrook | } |
5589 | 9ee6e8bb | pbrook | if (cond != 0xe) { |
5590 | 9ee6e8bb | pbrook | /* if not always execute, we generate a conditional jump to
|
5591 | 9ee6e8bb | pbrook | next instruction */
|
5592 | 9ee6e8bb | pbrook | s->condlabel = gen_new_label(); |
5593 | d9ba4830 | pbrook | gen_test_cc(cond ^ 1, s->condlabel);
|
5594 | 9ee6e8bb | pbrook | s->condjmp = 1;
|
5595 | 9ee6e8bb | pbrook | } |
5596 | 9ee6e8bb | pbrook | if ((insn & 0x0f900000) == 0x03000000) { |
5597 | 9ee6e8bb | pbrook | if ((insn & (1 << 21)) == 0) { |
5598 | 9ee6e8bb | pbrook | ARCH(6T2);
|
5599 | 9ee6e8bb | pbrook | rd = (insn >> 12) & 0xf; |
5600 | 9ee6e8bb | pbrook | val = ((insn >> 4) & 0xf000) | (insn & 0xfff); |
5601 | 9ee6e8bb | pbrook | if ((insn & (1 << 22)) == 0) { |
5602 | 9ee6e8bb | pbrook | /* MOVW */
|
5603 | 5e3f878a | pbrook | tmp = new_tmp(); |
5604 | 5e3f878a | pbrook | tcg_gen_movi_i32(tmp, val); |
5605 | 9ee6e8bb | pbrook | } else {
|
5606 | 9ee6e8bb | pbrook | /* MOVT */
|
5607 | 5e3f878a | pbrook | tmp = load_reg(s, rd); |
5608 | 5e3f878a | pbrook | tcg_gen_andi_i32(tmp, tmp, 0xffff);
|
5609 | 5e3f878a | pbrook | tcg_gen_ori_i32(tmp, tmp, val << 16);
|
5610 | 9ee6e8bb | pbrook | } |
5611 | 5e3f878a | pbrook | store_reg(s, rd, tmp); |
5612 | 9ee6e8bb | pbrook | } else {
|
5613 | 9ee6e8bb | pbrook | if (((insn >> 12) & 0xf) != 0xf) |
5614 | 9ee6e8bb | pbrook | goto illegal_op;
|
5615 | 9ee6e8bb | pbrook | if (((insn >> 16) & 0xf) == 0) { |
5616 | 9ee6e8bb | pbrook | gen_nop_hint(s, insn & 0xff);
|
5617 | 9ee6e8bb | pbrook | } else {
|
5618 | 9ee6e8bb | pbrook | /* CPSR = immediate */
|
5619 | 9ee6e8bb | pbrook | val = insn & 0xff;
|
5620 | 9ee6e8bb | pbrook | shift = ((insn >> 8) & 0xf) * 2; |
5621 | 9ee6e8bb | pbrook | if (shift)
|
5622 | 9ee6e8bb | pbrook | val = (val >> shift) | (val << (32 - shift));
|
5623 | 9ee6e8bb | pbrook | gen_op_movl_T0_im(val); |
5624 | 9ee6e8bb | pbrook | i = ((insn & (1 << 22)) != 0); |
5625 | 9ee6e8bb | pbrook | if (gen_set_psr_T0(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i)) |
5626 | 9ee6e8bb | pbrook | goto illegal_op;
|
5627 | 9ee6e8bb | pbrook | } |
5628 | 9ee6e8bb | pbrook | } |
5629 | 9ee6e8bb | pbrook | } else if ((insn & 0x0f900000) == 0x01000000 |
5630 | 9ee6e8bb | pbrook | && (insn & 0x00000090) != 0x00000090) { |
5631 | 9ee6e8bb | pbrook | /* miscellaneous instructions */
|
5632 | 9ee6e8bb | pbrook | op1 = (insn >> 21) & 3; |
5633 | 9ee6e8bb | pbrook | sh = (insn >> 4) & 0xf; |
5634 | 9ee6e8bb | pbrook | rm = insn & 0xf;
|
5635 | 9ee6e8bb | pbrook | switch (sh) {
|
5636 | 9ee6e8bb | pbrook | case 0x0: /* move program status register */ |
5637 | 9ee6e8bb | pbrook | if (op1 & 1) { |
5638 | 9ee6e8bb | pbrook | /* PSR = reg */
|
5639 | 9ee6e8bb | pbrook | gen_movl_T0_reg(s, rm); |
5640 | 9ee6e8bb | pbrook | i = ((op1 & 2) != 0); |
5641 | 9ee6e8bb | pbrook | if (gen_set_psr_T0(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i)) |
5642 | 9ee6e8bb | pbrook | goto illegal_op;
|
5643 | 9ee6e8bb | pbrook | } else {
|
5644 | 9ee6e8bb | pbrook | /* reg = PSR */
|
5645 | 9ee6e8bb | pbrook | rd = (insn >> 12) & 0xf; |
5646 | 9ee6e8bb | pbrook | if (op1 & 2) { |
5647 | 9ee6e8bb | pbrook | if (IS_USER(s))
|
5648 | 9ee6e8bb | pbrook | goto illegal_op;
|
5649 | d9ba4830 | pbrook | tmp = load_cpu_field(spsr); |
5650 | 9ee6e8bb | pbrook | } else {
|
5651 | d9ba4830 | pbrook | tmp = new_tmp(); |
5652 | d9ba4830 | pbrook | gen_helper_cpsr_read(tmp); |
5653 | 9ee6e8bb | pbrook | } |
5654 | d9ba4830 | pbrook | store_reg(s, rd, tmp); |
5655 | 9ee6e8bb | pbrook | } |
5656 | 9ee6e8bb | pbrook | break;
|
5657 | 9ee6e8bb | pbrook | case 0x1: |
5658 | 9ee6e8bb | pbrook | if (op1 == 1) { |
5659 | 9ee6e8bb | pbrook | /* branch/exchange thumb (bx). */
|
5660 | d9ba4830 | pbrook | tmp = load_reg(s, rm); |
5661 | d9ba4830 | pbrook | gen_bx(s, tmp); |
5662 | 9ee6e8bb | pbrook | } else if (op1 == 3) { |
5663 | 9ee6e8bb | pbrook | /* clz */
|
5664 | 9ee6e8bb | pbrook | rd = (insn >> 12) & 0xf; |
5665 | 1497c961 | pbrook | tmp = load_reg(s, rm); |
5666 | 1497c961 | pbrook | gen_helper_clz(tmp, tmp); |
5667 | 1497c961 | pbrook | store_reg(s, rd, tmp); |
5668 | 9ee6e8bb | pbrook | } else {
|
5669 | 9ee6e8bb | pbrook | goto illegal_op;
|
5670 | 9ee6e8bb | pbrook | } |
5671 | 9ee6e8bb | pbrook | break;
|
5672 | 9ee6e8bb | pbrook | case 0x2: |
5673 | 9ee6e8bb | pbrook | if (op1 == 1) { |
5674 | 9ee6e8bb | pbrook | ARCH(5J); /* bxj */ |
5675 | 9ee6e8bb | pbrook | /* Trivial implementation equivalent to bx. */
|
5676 | d9ba4830 | pbrook | tmp = load_reg(s, rm); |
5677 | d9ba4830 | pbrook | gen_bx(s, tmp); |
5678 | 9ee6e8bb | pbrook | } else {
|
5679 | 9ee6e8bb | pbrook | goto illegal_op;
|
5680 | 9ee6e8bb | pbrook | } |
5681 | 9ee6e8bb | pbrook | break;
|
5682 | 9ee6e8bb | pbrook | case 0x3: |
5683 | 9ee6e8bb | pbrook | if (op1 != 1) |
5684 | 9ee6e8bb | pbrook | goto illegal_op;
|
5685 | 9ee6e8bb | pbrook | |
5686 | 9ee6e8bb | pbrook | /* branch link/exchange thumb (blx) */
|
5687 | d9ba4830 | pbrook | tmp = load_reg(s, rm); |
5688 | d9ba4830 | pbrook | tmp2 = new_tmp(); |
5689 | d9ba4830 | pbrook | tcg_gen_movi_i32(tmp2, s->pc); |
5690 | d9ba4830 | pbrook | store_reg(s, 14, tmp2);
|
5691 | d9ba4830 | pbrook | gen_bx(s, tmp); |
5692 | 9ee6e8bb | pbrook | break;
|
5693 | 9ee6e8bb | pbrook | case 0x5: /* saturating add/subtract */ |
5694 | 9ee6e8bb | pbrook | rd = (insn >> 12) & 0xf; |
5695 | 9ee6e8bb | pbrook | rn = (insn >> 16) & 0xf; |
5696 | 5e3f878a | pbrook | tmp = load_reg(s, rn); |
5697 | 5e3f878a | pbrook | tmp2 = load_reg(s, rn); |
5698 | 9ee6e8bb | pbrook | if (op1 & 2) |
5699 | 5e3f878a | pbrook | gen_helper_double_saturate(tmp2, tmp2); |
5700 | 9ee6e8bb | pbrook | if (op1 & 1) |
5701 | 5e3f878a | pbrook | gen_helper_sub_saturate(tmp, tmp, tmp2); |
5702 | 9ee6e8bb | pbrook | else
|
5703 | 5e3f878a | pbrook | gen_helper_add_saturate(tmp, tmp, tmp2); |
5704 | 5e3f878a | pbrook | dead_tmp(tmp2); |
5705 | 5e3f878a | pbrook | store_reg(s, rd, tmp); |
5706 | 9ee6e8bb | pbrook | break;
|
5707 | 9ee6e8bb | pbrook | case 7: /* bkpt */ |
5708 | 9ee6e8bb | pbrook | gen_set_condexec(s); |
5709 | 5e3f878a | pbrook | gen_set_pc_im(s->pc - 4);
|
5710 | d9ba4830 | pbrook | gen_exception(EXCP_BKPT); |
5711 | 9ee6e8bb | pbrook | s->is_jmp = DISAS_JUMP; |
5712 | 9ee6e8bb | pbrook | break;
|
5713 | 9ee6e8bb | pbrook | case 0x8: /* signed multiply */ |
5714 | 9ee6e8bb | pbrook | case 0xa: |
5715 | 9ee6e8bb | pbrook | case 0xc: |
5716 | 9ee6e8bb | pbrook | case 0xe: |
5717 | 9ee6e8bb | pbrook | rs = (insn >> 8) & 0xf; |
5718 | 9ee6e8bb | pbrook | rn = (insn >> 12) & 0xf; |
5719 | 9ee6e8bb | pbrook | rd = (insn >> 16) & 0xf; |
5720 | 9ee6e8bb | pbrook | if (op1 == 1) { |
5721 | 9ee6e8bb | pbrook | /* (32 * 16) >> 16 */
|
5722 | 5e3f878a | pbrook | tmp = load_reg(s, rm); |
5723 | 5e3f878a | pbrook | tmp2 = load_reg(s, rs); |
5724 | 9ee6e8bb | pbrook | if (sh & 4) |
5725 | 5e3f878a | pbrook | tcg_gen_sari_i32(tmp2, tmp2, 16);
|
5726 | 9ee6e8bb | pbrook | else
|
5727 | 5e3f878a | pbrook | gen_sxth(tmp2); |
5728 | 5e3f878a | pbrook | tmp2 = gen_muls_i64_i32(tmp, tmp2); |
5729 | 5e3f878a | pbrook | tcg_gen_shri_i64(tmp2, tmp2, 16);
|
5730 | 5e3f878a | pbrook | tmp = new_tmp(); |
5731 | 5e3f878a | pbrook | tcg_gen_trunc_i64_i32(tmp, tmp2); |
5732 | 9ee6e8bb | pbrook | if ((sh & 2) == 0) { |
5733 | 5e3f878a | pbrook | tmp2 = load_reg(s, rn); |
5734 | 5e3f878a | pbrook | gen_helper_add_setq(tmp, tmp, tmp2); |
5735 | 5e3f878a | pbrook | dead_tmp(tmp2); |
5736 | 9ee6e8bb | pbrook | } |
5737 | 5e3f878a | pbrook | store_reg(s, rd, tmp); |
5738 | 9ee6e8bb | pbrook | } else {
|
5739 | 9ee6e8bb | pbrook | /* 16 * 16 */
|
5740 | 5e3f878a | pbrook | tmp = load_reg(s, rm); |
5741 | 5e3f878a | pbrook | tmp2 = load_reg(s, rs); |
5742 | 5e3f878a | pbrook | gen_mulxy(tmp, tmp2, sh & 2, sh & 4); |
5743 | 5e3f878a | pbrook | dead_tmp(tmp2); |
5744 | 9ee6e8bb | pbrook | if (op1 == 2) { |
5745 | 5e3f878a | pbrook | tmp = tcg_temp_new(TCG_TYPE_I64); |
5746 | 5e3f878a | pbrook | tcg_gen_ext_i32_i64(tmp, cpu_T[0]);
|
5747 | 5e3f878a | pbrook | gen_addq(s, tmp, rn, rd); |
5748 | 5e3f878a | pbrook | gen_storeq_reg(s, rn, rd, tmp); |
5749 | 9ee6e8bb | pbrook | } else {
|
5750 | 9ee6e8bb | pbrook | if (op1 == 0) { |
5751 | 5e3f878a | pbrook | tmp2 = load_reg(s, rn); |
5752 | 5e3f878a | pbrook | gen_helper_add_setq(tmp, tmp, tmp2); |
5753 | 5e3f878a | pbrook | dead_tmp(tmp2); |
5754 | 9ee6e8bb | pbrook | } |
5755 | 5e3f878a | pbrook | store_reg(s, rd, tmp); |
5756 | 9ee6e8bb | pbrook | } |
5757 | 9ee6e8bb | pbrook | } |
5758 | 9ee6e8bb | pbrook | break;
|
5759 | 9ee6e8bb | pbrook | default:
|
5760 | 9ee6e8bb | pbrook | goto illegal_op;
|
5761 | 9ee6e8bb | pbrook | } |
5762 | 9ee6e8bb | pbrook | } else if (((insn & 0x0e000000) == 0 && |
5763 | 9ee6e8bb | pbrook | (insn & 0x00000090) != 0x90) || |
5764 | 9ee6e8bb | pbrook | ((insn & 0x0e000000) == (1 << 25))) { |
5765 | 9ee6e8bb | pbrook | int set_cc, logic_cc, shiftop;
|
5766 | 9ee6e8bb | pbrook | |
5767 | 9ee6e8bb | pbrook | op1 = (insn >> 21) & 0xf; |
5768 | 9ee6e8bb | pbrook | set_cc = (insn >> 20) & 1; |
5769 | 9ee6e8bb | pbrook | logic_cc = table_logic_cc[op1] & set_cc; |
5770 | 9ee6e8bb | pbrook | |
5771 | 9ee6e8bb | pbrook | /* data processing instruction */
|
5772 | 9ee6e8bb | pbrook | if (insn & (1 << 25)) { |
5773 | 9ee6e8bb | pbrook | /* immediate operand */
|
5774 | 9ee6e8bb | pbrook | val = insn & 0xff;
|
5775 | 9ee6e8bb | pbrook | shift = ((insn >> 8) & 0xf) * 2; |
5776 | 9ee6e8bb | pbrook | if (shift)
|
5777 | 9ee6e8bb | pbrook | val = (val >> shift) | (val << (32 - shift));
|
5778 | 9ee6e8bb | pbrook | gen_op_movl_T1_im(val); |
5779 | 9ee6e8bb | pbrook | if (logic_cc && shift)
|
5780 | b26eefb6 | pbrook | gen_set_CF_bit31(cpu_T[1]);
|
5781 | 9ee6e8bb | pbrook | } else {
|
5782 | 9ee6e8bb | pbrook | /* register */
|
5783 | 9ee6e8bb | pbrook | rm = (insn) & 0xf;
|
5784 | 9ee6e8bb | pbrook | gen_movl_T1_reg(s, rm); |
5785 | 9ee6e8bb | pbrook | shiftop = (insn >> 5) & 3; |
5786 | 9ee6e8bb | pbrook | if (!(insn & (1 << 4))) { |
5787 | 9ee6e8bb | pbrook | shift = (insn >> 7) & 0x1f; |
5788 | 9a119ff6 | pbrook | gen_arm_shift_im(cpu_T[1], shiftop, shift, logic_cc);
|
5789 | 9ee6e8bb | pbrook | } else {
|
5790 | 9ee6e8bb | pbrook | rs = (insn >> 8) & 0xf; |
5791 | 8984bd2e | pbrook | tmp = load_reg(s, rs); |
5792 | 8984bd2e | pbrook | gen_arm_shift_reg(cpu_T[1], shiftop, tmp, logic_cc);
|
5793 | 9ee6e8bb | pbrook | } |
5794 | 9ee6e8bb | pbrook | } |
5795 | 9ee6e8bb | pbrook | if (op1 != 0x0f && op1 != 0x0d) { |
5796 | 9ee6e8bb | pbrook | rn = (insn >> 16) & 0xf; |
5797 | 9ee6e8bb | pbrook | gen_movl_T0_reg(s, rn); |
5798 | 9ee6e8bb | pbrook | } |
5799 | 9ee6e8bb | pbrook | rd = (insn >> 12) & 0xf; |
5800 | 9ee6e8bb | pbrook | switch(op1) {
|
5801 | 9ee6e8bb | pbrook | case 0x00: |
5802 | 9ee6e8bb | pbrook | gen_op_andl_T0_T1(); |
5803 | 9ee6e8bb | pbrook | gen_movl_reg_T0(s, rd); |
5804 | 9ee6e8bb | pbrook | if (logic_cc)
|
5805 | 9ee6e8bb | pbrook | gen_op_logic_T0_cc(); |
5806 | 9ee6e8bb | pbrook | break;
|
5807 | 9ee6e8bb | pbrook | case 0x01: |
5808 | 9ee6e8bb | pbrook | gen_op_xorl_T0_T1(); |
5809 | 9ee6e8bb | pbrook | gen_movl_reg_T0(s, rd); |
5810 | 9ee6e8bb | pbrook | if (logic_cc)
|
5811 | 9ee6e8bb | pbrook | gen_op_logic_T0_cc(); |
5812 | 9ee6e8bb | pbrook | break;
|
5813 | 9ee6e8bb | pbrook | case 0x02: |
5814 | 9ee6e8bb | pbrook | if (set_cc && rd == 15) { |
5815 | 9ee6e8bb | pbrook | /* SUBS r15, ... is used for exception return. */
|
5816 | 9ee6e8bb | pbrook | if (IS_USER(s))
|
5817 | 9ee6e8bb | pbrook | goto illegal_op;
|
5818 | 9ee6e8bb | pbrook | gen_op_subl_T0_T1_cc(); |
5819 | 9ee6e8bb | pbrook | gen_exception_return(s); |
5820 | 9ee6e8bb | pbrook | } else {
|
5821 | 9ee6e8bb | pbrook | if (set_cc)
|
5822 | 9ee6e8bb | pbrook | gen_op_subl_T0_T1_cc(); |
5823 | 9ee6e8bb | pbrook | else
|
5824 | 9ee6e8bb | pbrook | gen_op_subl_T0_T1(); |
5825 | 9ee6e8bb | pbrook | gen_movl_reg_T0(s, rd); |
5826 | 9ee6e8bb | pbrook | } |
5827 | 9ee6e8bb | pbrook | break;
|
5828 | 9ee6e8bb | pbrook | case 0x03: |
5829 | 9ee6e8bb | pbrook | if (set_cc)
|
5830 | 9ee6e8bb | pbrook | gen_op_rsbl_T0_T1_cc(); |
5831 | 9ee6e8bb | pbrook | else
|
5832 | 9ee6e8bb | pbrook | gen_op_rsbl_T0_T1(); |
5833 | 9ee6e8bb | pbrook | gen_movl_reg_T0(s, rd); |
5834 | 9ee6e8bb | pbrook | break;
|
5835 | 9ee6e8bb | pbrook | case 0x04: |
5836 | 9ee6e8bb | pbrook | if (set_cc)
|
5837 | 9ee6e8bb | pbrook | gen_op_addl_T0_T1_cc(); |
5838 | 9ee6e8bb | pbrook | else
|
5839 | 9ee6e8bb | pbrook | gen_op_addl_T0_T1(); |
5840 | 9ee6e8bb | pbrook | gen_movl_reg_T0(s, rd); |
5841 | 9ee6e8bb | pbrook | break;
|
5842 | 9ee6e8bb | pbrook | case 0x05: |
5843 | 9ee6e8bb | pbrook | if (set_cc)
|
5844 | 9ee6e8bb | pbrook | gen_op_adcl_T0_T1_cc(); |
5845 | 9ee6e8bb | pbrook | else
|
5846 | b26eefb6 | pbrook | gen_adc_T0_T1(); |
5847 | 9ee6e8bb | pbrook | gen_movl_reg_T0(s, rd); |
5848 | 9ee6e8bb | pbrook | break;
|
5849 | 9ee6e8bb | pbrook | case 0x06: |
5850 | 9ee6e8bb | pbrook | if (set_cc)
|
5851 | 9ee6e8bb | pbrook | gen_op_sbcl_T0_T1_cc(); |
5852 | 9ee6e8bb | pbrook | else
|
5853 | 3670669c | pbrook | gen_sbc_T0_T1(); |
5854 | 9ee6e8bb | pbrook | gen_movl_reg_T0(s, rd); |
5855 | 9ee6e8bb | pbrook | break;
|
5856 | 9ee6e8bb | pbrook | case 0x07: |
5857 | 9ee6e8bb | pbrook | if (set_cc)
|
5858 | 9ee6e8bb | pbrook | gen_op_rscl_T0_T1_cc(); |
5859 | 9ee6e8bb | pbrook | else
|
5860 | 3670669c | pbrook | gen_rsc_T0_T1(); |
5861 | 9ee6e8bb | pbrook | gen_movl_reg_T0(s, rd); |
5862 | 9ee6e8bb | pbrook | break;
|
5863 | 9ee6e8bb | pbrook | case 0x08: |
5864 | 9ee6e8bb | pbrook | if (set_cc) {
|
5865 | 9ee6e8bb | pbrook | gen_op_andl_T0_T1(); |
5866 | 9ee6e8bb | pbrook | gen_op_logic_T0_cc(); |
5867 | 9ee6e8bb | pbrook | } |
5868 | 9ee6e8bb | pbrook | break;
|
5869 | 9ee6e8bb | pbrook | case 0x09: |
5870 | 9ee6e8bb | pbrook | if (set_cc) {
|
5871 | 9ee6e8bb | pbrook | gen_op_xorl_T0_T1(); |
5872 | 9ee6e8bb | pbrook | gen_op_logic_T0_cc(); |
5873 | 9ee6e8bb | pbrook | } |
5874 | 9ee6e8bb | pbrook | break;
|
5875 | 9ee6e8bb | pbrook | case 0x0a: |
5876 | 9ee6e8bb | pbrook | if (set_cc) {
|
5877 | 9ee6e8bb | pbrook | gen_op_subl_T0_T1_cc(); |
5878 | 9ee6e8bb | pbrook | } |
5879 | 9ee6e8bb | pbrook | break;
|
5880 | 9ee6e8bb | pbrook | case 0x0b: |
5881 | 9ee6e8bb | pbrook | if (set_cc) {
|
5882 | 9ee6e8bb | pbrook | gen_op_addl_T0_T1_cc(); |
5883 | 9ee6e8bb | pbrook | } |
5884 | 9ee6e8bb | pbrook | break;
|
5885 | 9ee6e8bb | pbrook | case 0x0c: |
5886 | 9ee6e8bb | pbrook | gen_op_orl_T0_T1(); |
5887 | 9ee6e8bb | pbrook | gen_movl_reg_T0(s, rd); |
5888 | 9ee6e8bb | pbrook | if (logic_cc)
|
5889 | 9ee6e8bb | pbrook | gen_op_logic_T0_cc(); |
5890 | 9ee6e8bb | pbrook | break;
|
5891 | 9ee6e8bb | pbrook | case 0x0d: |
5892 | 9ee6e8bb | pbrook | if (logic_cc && rd == 15) { |
5893 | 9ee6e8bb | pbrook | /* MOVS r15, ... is used for exception return. */
|
5894 | 9ee6e8bb | pbrook | if (IS_USER(s))
|
5895 | 9ee6e8bb | pbrook | goto illegal_op;
|
5896 | 9ee6e8bb | pbrook | gen_op_movl_T0_T1(); |
5897 | 9ee6e8bb | pbrook | gen_exception_return(s); |
5898 | 9ee6e8bb | pbrook | } else {
|
5899 | 9ee6e8bb | pbrook | gen_movl_reg_T1(s, rd); |
5900 | 9ee6e8bb | pbrook | if (logic_cc)
|
5901 | 9ee6e8bb | pbrook | gen_op_logic_T1_cc(); |
5902 | 9ee6e8bb | pbrook | } |
5903 | 9ee6e8bb | pbrook | break;
|
5904 | 9ee6e8bb | pbrook | case 0x0e: |
5905 | 9ee6e8bb | pbrook | gen_op_bicl_T0_T1(); |
5906 | 9ee6e8bb | pbrook | gen_movl_reg_T0(s, rd); |
5907 | 9ee6e8bb | pbrook | if (logic_cc)
|
5908 | 9ee6e8bb | pbrook | gen_op_logic_T0_cc(); |
5909 | 9ee6e8bb | pbrook | break;
|
5910 | 9ee6e8bb | pbrook | default:
|
5911 | 9ee6e8bb | pbrook | case 0x0f: |
5912 | 9ee6e8bb | pbrook | gen_op_notl_T1(); |
5913 | 9ee6e8bb | pbrook | gen_movl_reg_T1(s, rd); |
5914 | 9ee6e8bb | pbrook | if (logic_cc)
|
5915 | 9ee6e8bb | pbrook | gen_op_logic_T1_cc(); |
5916 | 9ee6e8bb | pbrook | break;
|
5917 | 9ee6e8bb | pbrook | } |
5918 | 9ee6e8bb | pbrook | } else {
|
5919 | 9ee6e8bb | pbrook | /* other instructions */
|
5920 | 9ee6e8bb | pbrook | op1 = (insn >> 24) & 0xf; |
5921 | 9ee6e8bb | pbrook | switch(op1) {
|
5922 | 9ee6e8bb | pbrook | case 0x0: |
5923 | 9ee6e8bb | pbrook | case 0x1: |
5924 | 9ee6e8bb | pbrook | /* multiplies, extra load/stores */
|
5925 | 9ee6e8bb | pbrook | sh = (insn >> 5) & 3; |
5926 | 9ee6e8bb | pbrook | if (sh == 0) { |
5927 | 9ee6e8bb | pbrook | if (op1 == 0x0) { |
5928 | 9ee6e8bb | pbrook | rd = (insn >> 16) & 0xf; |
5929 | 9ee6e8bb | pbrook | rn = (insn >> 12) & 0xf; |
5930 | 9ee6e8bb | pbrook | rs = (insn >> 8) & 0xf; |
5931 | 9ee6e8bb | pbrook | rm = (insn) & 0xf;
|
5932 | 9ee6e8bb | pbrook | op1 = (insn >> 20) & 0xf; |
5933 | 9ee6e8bb | pbrook | switch (op1) {
|
5934 | 9ee6e8bb | pbrook | case 0: case 1: case 2: case 3: case 6: |
5935 | 9ee6e8bb | pbrook | /* 32 bit mul */
|
5936 | 5e3f878a | pbrook | tmp = load_reg(s, rs); |
5937 | 5e3f878a | pbrook | tmp2 = load_reg(s, rm); |
5938 | 5e3f878a | pbrook | tcg_gen_mul_i32(tmp, tmp, tmp2); |
5939 | 5e3f878a | pbrook | dead_tmp(tmp2); |
5940 | 9ee6e8bb | pbrook | if (insn & (1 << 22)) { |
5941 | 9ee6e8bb | pbrook | /* Subtract (mls) */
|
5942 | 9ee6e8bb | pbrook | ARCH(6T2);
|
5943 | 5e3f878a | pbrook | tmp2 = load_reg(s, rn); |
5944 | 5e3f878a | pbrook | tcg_gen_sub_i32(tmp, tmp2, tmp); |
5945 | 5e3f878a | pbrook | dead_tmp(tmp2); |
5946 | 9ee6e8bb | pbrook | } else if (insn & (1 << 21)) { |
5947 | 9ee6e8bb | pbrook | /* Add */
|
5948 | 5e3f878a | pbrook | tmp2 = load_reg(s, rn); |
5949 | 5e3f878a | pbrook | tcg_gen_add_i32(tmp, tmp, tmp2); |
5950 | 5e3f878a | pbrook | dead_tmp(tmp2); |
5951 | 9ee6e8bb | pbrook | } |
5952 | 9ee6e8bb | pbrook | if (insn & (1 << 20)) |
5953 | 5e3f878a | pbrook | gen_logic_CC(tmp); |
5954 | 5e3f878a | pbrook | store_reg(s, rd, tmp); |
5955 | 9ee6e8bb | pbrook | break;
|
5956 | 9ee6e8bb | pbrook | default:
|
5957 | 9ee6e8bb | pbrook | /* 64 bit mul */
|
5958 | 5e3f878a | pbrook | tmp = load_reg(s, rs); |
5959 | 5e3f878a | pbrook | tmp2 = load_reg(s, rm); |
5960 | 9ee6e8bb | pbrook | if (insn & (1 << 22)) |
5961 | 5e3f878a | pbrook | tmp = gen_muls_i64_i32(tmp, tmp2); |
5962 | 9ee6e8bb | pbrook | else
|
5963 | 5e3f878a | pbrook | tmp = gen_mulu_i64_i32(tmp, tmp2); |
5964 | 9ee6e8bb | pbrook | if (insn & (1 << 21)) /* mult accumulate */ |
5965 | 5e3f878a | pbrook | gen_addq(s, tmp, rn, rd); |
5966 | 9ee6e8bb | pbrook | if (!(insn & (1 << 23))) { /* double accumulate */ |
5967 | 9ee6e8bb | pbrook | ARCH(6);
|
5968 | 5e3f878a | pbrook | gen_addq_lo(s, tmp, rn); |
5969 | 5e3f878a | pbrook | gen_addq_lo(s, tmp, rd); |
5970 | 9ee6e8bb | pbrook | } |
5971 | 9ee6e8bb | pbrook | if (insn & (1 << 20)) |
5972 | 5e3f878a | pbrook | gen_logicq_cc(tmp); |
5973 | 5e3f878a | pbrook | gen_storeq_reg(s, rn, rd, tmp); |
5974 | 9ee6e8bb | pbrook | break;
|
5975 | 9ee6e8bb | pbrook | } |
5976 | 9ee6e8bb | pbrook | } else {
|
5977 | 9ee6e8bb | pbrook | rn = (insn >> 16) & 0xf; |
5978 | 9ee6e8bb | pbrook | rd = (insn >> 12) & 0xf; |
5979 | 9ee6e8bb | pbrook | if (insn & (1 << 23)) { |
5980 | 9ee6e8bb | pbrook | /* load/store exclusive */
|
5981 | 9ee6e8bb | pbrook | gen_movl_T1_reg(s, rn); |
5982 | 9ee6e8bb | pbrook | if (insn & (1 << 20)) { |
5983 | 8f8e3aa4 | pbrook | gen_helper_mark_exclusive(cpu_env, cpu_T[1]);
|
5984 | 8f8e3aa4 | pbrook | tmp = gen_ld32(addr, IS_USER(s)); |
5985 | 8f8e3aa4 | pbrook | store_reg(s, rd, tmp); |
5986 | 9ee6e8bb | pbrook | } else {
|
5987 | 8f8e3aa4 | pbrook | int label = gen_new_label();
|
5988 | 9ee6e8bb | pbrook | rm = insn & 0xf;
|
5989 | 8f8e3aa4 | pbrook | gen_helper_test_exclusive(cpu_T[0], cpu_env, addr);
|
5990 | 8f8e3aa4 | pbrook | tcg_gen_brcond_i32(TCG_COND_NE, cpu_T[0],
|
5991 | 8f8e3aa4 | pbrook | tcg_const_i32(0), label);
|
5992 | 8f8e3aa4 | pbrook | tmp = load_reg(s,rm); |
5993 | 8f8e3aa4 | pbrook | gen_st32(tmp, cpu_T[1], IS_USER(s));
|
5994 | 8f8e3aa4 | pbrook | gen_movl_reg_T0(s, rd); |
5995 | 9ee6e8bb | pbrook | } |
5996 | 9ee6e8bb | pbrook | } else {
|
5997 | 9ee6e8bb | pbrook | /* SWP instruction */
|
5998 | 9ee6e8bb | pbrook | rm = (insn) & 0xf;
|
5999 | 9ee6e8bb | pbrook | |
6000 | 8984bd2e | pbrook | /* ??? This is not really atomic. However we know
|
6001 | 8984bd2e | pbrook | we never have multiple CPUs running in parallel,
|
6002 | 8984bd2e | pbrook | so it is good enough. */
|
6003 | 8984bd2e | pbrook | addr = load_reg(s, rn); |
6004 | 8984bd2e | pbrook | tmp = load_reg(s, rm); |
6005 | 9ee6e8bb | pbrook | if (insn & (1 << 22)) { |
6006 | 8984bd2e | pbrook | tmp2 = gen_ld8u(addr, IS_USER(s)); |
6007 | 8984bd2e | pbrook | gen_st8(tmp, addr, IS_USER(s)); |
6008 | 9ee6e8bb | pbrook | } else {
|
6009 | 8984bd2e | pbrook | tmp2 = gen_ld32(addr, IS_USER(s)); |
6010 | 8984bd2e | pbrook | gen_st32(tmp, addr, IS_USER(s)); |
6011 | 9ee6e8bb | pbrook | } |
6012 | 8984bd2e | pbrook | dead_tmp(addr); |
6013 | 8984bd2e | pbrook | store_reg(s, rd, tmp2); |
6014 | 9ee6e8bb | pbrook | } |
6015 | 9ee6e8bb | pbrook | } |
6016 | 9ee6e8bb | pbrook | } else {
|
6017 | 9ee6e8bb | pbrook | int address_offset;
|
6018 | 9ee6e8bb | pbrook | int load;
|
6019 | 9ee6e8bb | pbrook | /* Misc load/store */
|
6020 | 9ee6e8bb | pbrook | rn = (insn >> 16) & 0xf; |
6021 | 9ee6e8bb | pbrook | rd = (insn >> 12) & 0xf; |
6022 | b0109805 | pbrook | addr = load_reg(s, rn); |
6023 | 9ee6e8bb | pbrook | if (insn & (1 << 24)) |
6024 | b0109805 | pbrook | gen_add_datah_offset(s, insn, 0, addr);
|
6025 | 9ee6e8bb | pbrook | address_offset = 0;
|
6026 | 9ee6e8bb | pbrook | if (insn & (1 << 20)) { |
6027 | 9ee6e8bb | pbrook | /* load */
|
6028 | 9ee6e8bb | pbrook | switch(sh) {
|
6029 | 9ee6e8bb | pbrook | case 1: |
6030 | b0109805 | pbrook | tmp = gen_ld16u(addr, IS_USER(s)); |
6031 | 9ee6e8bb | pbrook | break;
|
6032 | 9ee6e8bb | pbrook | case 2: |
6033 | b0109805 | pbrook | tmp = gen_ld8s(addr, IS_USER(s)); |
6034 | 9ee6e8bb | pbrook | break;
|
6035 | 9ee6e8bb | pbrook | default:
|
6036 | 9ee6e8bb | pbrook | case 3: |
6037 | b0109805 | pbrook | tmp = gen_ld16s(addr, IS_USER(s)); |
6038 | 9ee6e8bb | pbrook | break;
|
6039 | 9ee6e8bb | pbrook | } |
6040 | 9ee6e8bb | pbrook | load = 1;
|
6041 | 9ee6e8bb | pbrook | } else if (sh & 2) { |
6042 | 9ee6e8bb | pbrook | /* doubleword */
|
6043 | 9ee6e8bb | pbrook | if (sh & 1) { |
6044 | 9ee6e8bb | pbrook | /* store */
|
6045 | b0109805 | pbrook | tmp = load_reg(s, rd); |
6046 | b0109805 | pbrook | gen_st32(tmp, addr, IS_USER(s)); |
6047 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, 4);
|
6048 | b0109805 | pbrook | tmp = load_reg(s, rd + 1);
|
6049 | b0109805 | pbrook | gen_st32(tmp, addr, IS_USER(s)); |
6050 | 9ee6e8bb | pbrook | load = 0;
|
6051 | 9ee6e8bb | pbrook | } else {
|
6052 | 9ee6e8bb | pbrook | /* load */
|
6053 | b0109805 | pbrook | tmp = gen_ld32(addr, IS_USER(s)); |
6054 | b0109805 | pbrook | store_reg(s, rd, tmp); |
6055 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, 4);
|
6056 | b0109805 | pbrook | tmp = gen_ld32(addr, IS_USER(s)); |
6057 | 9ee6e8bb | pbrook | rd++; |
6058 | 9ee6e8bb | pbrook | load = 1;
|
6059 | 9ee6e8bb | pbrook | } |
6060 | 9ee6e8bb | pbrook | address_offset = -4;
|
6061 | 9ee6e8bb | pbrook | } else {
|
6062 | 9ee6e8bb | pbrook | /* store */
|
6063 | b0109805 | pbrook | tmp = load_reg(s, rd); |
6064 | b0109805 | pbrook | gen_st16(tmp, addr, IS_USER(s)); |
6065 | 9ee6e8bb | pbrook | load = 0;
|
6066 | 9ee6e8bb | pbrook | } |
6067 | 9ee6e8bb | pbrook | /* Perform base writeback before the loaded value to
|
6068 | 9ee6e8bb | pbrook | ensure correct behavior with overlapping index registers.
|
6069 | 9ee6e8bb | pbrook | ldrd with base writeback is is undefined if the
|
6070 | 9ee6e8bb | pbrook | destination and index registers overlap. */
|
6071 | 9ee6e8bb | pbrook | if (!(insn & (1 << 24))) { |
6072 | b0109805 | pbrook | gen_add_datah_offset(s, insn, address_offset, addr); |
6073 | b0109805 | pbrook | store_reg(s, rn, addr); |
6074 | 9ee6e8bb | pbrook | } else if (insn & (1 << 21)) { |
6075 | 9ee6e8bb | pbrook | if (address_offset)
|
6076 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, address_offset); |
6077 | b0109805 | pbrook | store_reg(s, rn, addr); |
6078 | b0109805 | pbrook | } else {
|
6079 | b0109805 | pbrook | dead_tmp(addr); |
6080 | 9ee6e8bb | pbrook | } |
6081 | 9ee6e8bb | pbrook | if (load) {
|
6082 | 9ee6e8bb | pbrook | /* Complete the load. */
|
6083 | b0109805 | pbrook | store_reg(s, rd, tmp); |
6084 | 9ee6e8bb | pbrook | } |
6085 | 9ee6e8bb | pbrook | } |
6086 | 9ee6e8bb | pbrook | break;
|
6087 | 9ee6e8bb | pbrook | case 0x4: |
6088 | 9ee6e8bb | pbrook | case 0x5: |
6089 | 9ee6e8bb | pbrook | goto do_ldst;
|
6090 | 9ee6e8bb | pbrook | case 0x6: |
6091 | 9ee6e8bb | pbrook | case 0x7: |
6092 | 9ee6e8bb | pbrook | if (insn & (1 << 4)) { |
6093 | 9ee6e8bb | pbrook | ARCH(6);
|
6094 | 9ee6e8bb | pbrook | /* Armv6 Media instructions. */
|
6095 | 9ee6e8bb | pbrook | rm = insn & 0xf;
|
6096 | 9ee6e8bb | pbrook | rn = (insn >> 16) & 0xf; |
6097 | 2c0262af | bellard | rd = (insn >> 12) & 0xf; |
6098 | 9ee6e8bb | pbrook | rs = (insn >> 8) & 0xf; |
6099 | 9ee6e8bb | pbrook | switch ((insn >> 23) & 3) { |
6100 | 9ee6e8bb | pbrook | case 0: /* Parallel add/subtract. */ |
6101 | 9ee6e8bb | pbrook | op1 = (insn >> 20) & 7; |
6102 | 6ddbc6e4 | pbrook | tmp = load_reg(s, rn); |
6103 | 6ddbc6e4 | pbrook | tmp2 = load_reg(s, rm); |
6104 | 9ee6e8bb | pbrook | sh = (insn >> 5) & 7; |
6105 | 9ee6e8bb | pbrook | if ((op1 & 3) == 0 || sh == 5 || sh == 6) |
6106 | 9ee6e8bb | pbrook | goto illegal_op;
|
6107 | 6ddbc6e4 | pbrook | gen_arm_parallel_addsub(op1, sh, tmp, tmp2); |
6108 | 6ddbc6e4 | pbrook | dead_tmp(tmp2); |
6109 | 6ddbc6e4 | pbrook | store_reg(s, rd, tmp); |
6110 | 9ee6e8bb | pbrook | break;
|
6111 | 9ee6e8bb | pbrook | case 1: |
6112 | 9ee6e8bb | pbrook | if ((insn & 0x00700020) == 0) { |
6113 | 9ee6e8bb | pbrook | /* Hafword pack. */
|
6114 | 3670669c | pbrook | tmp = load_reg(s, rn); |
6115 | 3670669c | pbrook | tmp2 = load_reg(s, rm); |
6116 | 9ee6e8bb | pbrook | shift = (insn >> 7) & 0x1f; |
6117 | 9ee6e8bb | pbrook | if (shift)
|
6118 | 3670669c | pbrook | tcg_gen_shli_i32(tmp2, tmp2, shift); |
6119 | 3670669c | pbrook | if (insn & (1 << 6)) { |
6120 | 3670669c | pbrook | /* pkhtb */
|
6121 | 3670669c | pbrook | tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
|
6122 | 3670669c | pbrook | tcg_gen_andi_i32(tmp2, tmp2, 0xffff);
|
6123 | 3670669c | pbrook | } else {
|
6124 | 3670669c | pbrook | /* pkhbt */
|
6125 | 3670669c | pbrook | tcg_gen_andi_i32(tmp, tmp, 0xffff);
|
6126 | 3670669c | pbrook | tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
|
6127 | 3670669c | pbrook | } |
6128 | 3670669c | pbrook | tcg_gen_or_i32(tmp, tmp, tmp2); |
6129 | 3670669c | pbrook | store_reg(s, rd, tmp); |
6130 | 9ee6e8bb | pbrook | } else if ((insn & 0x00200020) == 0x00200000) { |
6131 | 9ee6e8bb | pbrook | /* [us]sat */
|
6132 | 6ddbc6e4 | pbrook | tmp = load_reg(s, rm); |
6133 | 9ee6e8bb | pbrook | shift = (insn >> 7) & 0x1f; |
6134 | 9ee6e8bb | pbrook | if (insn & (1 << 6)) { |
6135 | 9ee6e8bb | pbrook | if (shift == 0) |
6136 | 9ee6e8bb | pbrook | shift = 31;
|
6137 | 6ddbc6e4 | pbrook | tcg_gen_sari_i32(tmp, tmp, shift); |
6138 | 9ee6e8bb | pbrook | } else {
|
6139 | 6ddbc6e4 | pbrook | tcg_gen_shli_i32(tmp, tmp, shift); |
6140 | 9ee6e8bb | pbrook | } |
6141 | 9ee6e8bb | pbrook | sh = (insn >> 16) & 0x1f; |
6142 | 9ee6e8bb | pbrook | if (sh != 0) { |
6143 | 9ee6e8bb | pbrook | if (insn & (1 << 22)) |
6144 | 6ddbc6e4 | pbrook | gen_helper_usat(tmp, tmp, tcg_const_i32(sh)); |
6145 | 9ee6e8bb | pbrook | else
|
6146 | 6ddbc6e4 | pbrook | gen_helper_ssat(tmp, tmp, tcg_const_i32(sh)); |
6147 | 9ee6e8bb | pbrook | } |
6148 | 6ddbc6e4 | pbrook | store_reg(s, rd, tmp); |
6149 | 9ee6e8bb | pbrook | } else if ((insn & 0x00300fe0) == 0x00200f20) { |
6150 | 9ee6e8bb | pbrook | /* [us]sat16 */
|
6151 | 6ddbc6e4 | pbrook | tmp = load_reg(s, rm); |
6152 | 9ee6e8bb | pbrook | sh = (insn >> 16) & 0x1f; |
6153 | 9ee6e8bb | pbrook | if (sh != 0) { |
6154 | 9ee6e8bb | pbrook | if (insn & (1 << 22)) |
6155 | 6ddbc6e4 | pbrook | gen_helper_usat16(tmp, tmp, tcg_const_i32(sh)); |
6156 | 9ee6e8bb | pbrook | else
|
6157 | 6ddbc6e4 | pbrook | gen_helper_ssat16(tmp, tmp, tcg_const_i32(sh)); |
6158 | 9ee6e8bb | pbrook | } |
6159 | 6ddbc6e4 | pbrook | store_reg(s, rd, tmp); |
6160 | 9ee6e8bb | pbrook | } else if ((insn & 0x00700fe0) == 0x00000fa0) { |
6161 | 9ee6e8bb | pbrook | /* Select bytes. */
|
6162 | 6ddbc6e4 | pbrook | tmp = load_reg(s, rn); |
6163 | 6ddbc6e4 | pbrook | tmp2 = load_reg(s, rm); |
6164 | 6ddbc6e4 | pbrook | tmp3 = new_tmp(); |
6165 | 6ddbc6e4 | pbrook | tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE)); |
6166 | 6ddbc6e4 | pbrook | gen_helper_sel_flags(tmp, tmp3, tmp, tmp2); |
6167 | 6ddbc6e4 | pbrook | dead_tmp(tmp3); |
6168 | 6ddbc6e4 | pbrook | dead_tmp(tmp2); |
6169 | 6ddbc6e4 | pbrook | store_reg(s, rd, tmp); |
6170 | 9ee6e8bb | pbrook | } else if ((insn & 0x000003e0) == 0x00000060) { |
6171 | 5e3f878a | pbrook | tmp = load_reg(s, rm); |
6172 | 9ee6e8bb | pbrook | shift = (insn >> 10) & 3; |
6173 | 9ee6e8bb | pbrook | /* ??? In many cases it's not neccessary to do a
|
6174 | 9ee6e8bb | pbrook | rotate, a shift is sufficient. */
|
6175 | 9ee6e8bb | pbrook | if (shift != 0) |
6176 | 5e3f878a | pbrook | tcg_gen_rori_i32(tmp, tmp, shift * 8);
|
6177 | 9ee6e8bb | pbrook | op1 = (insn >> 20) & 7; |
6178 | 9ee6e8bb | pbrook | switch (op1) {
|
6179 | 5e3f878a | pbrook | case 0: gen_sxtb16(tmp); break; |
6180 | 5e3f878a | pbrook | case 2: gen_sxtb(tmp); break; |
6181 | 5e3f878a | pbrook | case 3: gen_sxth(tmp); break; |
6182 | 5e3f878a | pbrook | case 4: gen_uxtb16(tmp); break; |
6183 | 5e3f878a | pbrook | case 6: gen_uxtb(tmp); break; |
6184 | 5e3f878a | pbrook | case 7: gen_uxth(tmp); break; |
6185 | 9ee6e8bb | pbrook | default: goto illegal_op; |
6186 | 9ee6e8bb | pbrook | } |
6187 | 9ee6e8bb | pbrook | if (rn != 15) { |
6188 | 5e3f878a | pbrook | tmp2 = load_reg(s, rn); |
6189 | 9ee6e8bb | pbrook | if ((op1 & 3) == 0) { |
6190 | 5e3f878a | pbrook | gen_add16(tmp, tmp2); |
6191 | 9ee6e8bb | pbrook | } else {
|
6192 | 5e3f878a | pbrook | tcg_gen_add_i32(tmp, tmp, tmp2); |
6193 | 5e3f878a | pbrook | dead_tmp(tmp2); |
6194 | 9ee6e8bb | pbrook | } |
6195 | 9ee6e8bb | pbrook | } |
6196 | 5e3f878a | pbrook | store_reg(s, rd, tmp2); |
6197 | 9ee6e8bb | pbrook | } else if ((insn & 0x003f0f60) == 0x003f0f20) { |
6198 | 9ee6e8bb | pbrook | /* rev */
|
6199 | b0109805 | pbrook | tmp = load_reg(s, rm); |
6200 | 9ee6e8bb | pbrook | if (insn & (1 << 22)) { |
6201 | 9ee6e8bb | pbrook | if (insn & (1 << 7)) { |
6202 | b0109805 | pbrook | gen_revsh(tmp); |
6203 | 9ee6e8bb | pbrook | } else {
|
6204 | 9ee6e8bb | pbrook | ARCH(6T2);
|
6205 | b0109805 | pbrook | gen_helper_rbit(tmp, tmp); |
6206 | 9ee6e8bb | pbrook | } |
6207 | 9ee6e8bb | pbrook | } else {
|
6208 | 9ee6e8bb | pbrook | if (insn & (1 << 7)) |
6209 | b0109805 | pbrook | gen_rev16(tmp); |
6210 | 9ee6e8bb | pbrook | else
|
6211 | b0109805 | pbrook | tcg_gen_bswap_i32(tmp, tmp); |
6212 | 9ee6e8bb | pbrook | } |
6213 | b0109805 | pbrook | store_reg(s, rd, tmp); |
6214 | 9ee6e8bb | pbrook | } else {
|
6215 | 9ee6e8bb | pbrook | goto illegal_op;
|
6216 | 9ee6e8bb | pbrook | } |
6217 | 9ee6e8bb | pbrook | break;
|
6218 | 9ee6e8bb | pbrook | case 2: /* Multiplies (Type 3). */ |
6219 | 5e3f878a | pbrook | tmp = load_reg(s, rm); |
6220 | 5e3f878a | pbrook | tmp2 = load_reg(s, rs); |
6221 | 9ee6e8bb | pbrook | if (insn & (1 << 20)) { |
6222 | 9ee6e8bb | pbrook | /* Signed multiply most significant [accumulate]. */
|
6223 | 5e3f878a | pbrook | tmp2 = gen_muls_i64_i32(tmp, tmp2); |
6224 | 9ee6e8bb | pbrook | if (insn & (1 << 5)) |
6225 | 5e3f878a | pbrook | tcg_gen_addi_i64(tmp2, tmp2, 0x80000000u);
|
6226 | 5e3f878a | pbrook | tcg_gen_shri_i64(tmp2, tmp2, 32);
|
6227 | 5e3f878a | pbrook | tmp = new_tmp(); |
6228 | 5e3f878a | pbrook | tcg_gen_trunc_i64_i32(tmp, tmp2); |
6229 | 9ee6e8bb | pbrook | if (rn != 15) { |
6230 | 5e3f878a | pbrook | tmp2 = load_reg(s, rn); |
6231 | 9ee6e8bb | pbrook | if (insn & (1 << 6)) { |
6232 | 5e3f878a | pbrook | tcg_gen_sub_i32(tmp, tmp, tmp2); |
6233 | 9ee6e8bb | pbrook | } else {
|
6234 | 5e3f878a | pbrook | tcg_gen_add_i32(tmp, tmp, tmp2); |
6235 | 9ee6e8bb | pbrook | } |
6236 | 5e3f878a | pbrook | dead_tmp(tmp2); |
6237 | 9ee6e8bb | pbrook | } |
6238 | 5e3f878a | pbrook | store_reg(s, rd, tmp); |
6239 | 9ee6e8bb | pbrook | } else {
|
6240 | 9ee6e8bb | pbrook | if (insn & (1 << 5)) |
6241 | 5e3f878a | pbrook | gen_swap_half(tmp2); |
6242 | 5e3f878a | pbrook | gen_smul_dual(tmp, tmp2); |
6243 | 5e3f878a | pbrook | /* This addition cannot overflow. */
|
6244 | 5e3f878a | pbrook | if (insn & (1 << 6)) { |
6245 | 5e3f878a | pbrook | tcg_gen_sub_i32(tmp, tmp, tmp2); |
6246 | 5e3f878a | pbrook | } else {
|
6247 | 5e3f878a | pbrook | tcg_gen_add_i32(tmp, tmp, tmp2); |
6248 | 5e3f878a | pbrook | } |
6249 | 5e3f878a | pbrook | dead_tmp(tmp2); |
6250 | 9ee6e8bb | pbrook | if (insn & (1 << 22)) { |
6251 | 5e3f878a | pbrook | /* smlald, smlsld */
|
6252 | 5e3f878a | pbrook | tmp2 = tcg_temp_new(TCG_TYPE_I64); |
6253 | 5e3f878a | pbrook | tcg_gen_ext_i32_i64(tmp2, tmp); |
6254 | 5e3f878a | pbrook | dead_tmp(tmp); |
6255 | 5e3f878a | pbrook | gen_addq(s, tmp2, rn, rd); |
6256 | 5e3f878a | pbrook | gen_storeq_reg(s, rn, rd, tmp2); |
6257 | 9ee6e8bb | pbrook | } else {
|
6258 | 5e3f878a | pbrook | /* smuad, smusd, smlad, smlsd */
|
6259 | 9ee6e8bb | pbrook | if (rn != 15) |
6260 | 9ee6e8bb | pbrook | { |
6261 | 5e3f878a | pbrook | tmp2 = load_reg(s, rn); |
6262 | 5e3f878a | pbrook | gen_helper_add_setq(tmp, tmp, tmp2); |
6263 | 5e3f878a | pbrook | dead_tmp(tmp2); |
6264 | 9ee6e8bb | pbrook | } |
6265 | 5e3f878a | pbrook | store_reg(s, rd, tmp); |
6266 | 9ee6e8bb | pbrook | } |
6267 | 9ee6e8bb | pbrook | } |
6268 | 9ee6e8bb | pbrook | break;
|
6269 | 9ee6e8bb | pbrook | case 3: |
6270 | 9ee6e8bb | pbrook | op1 = ((insn >> 17) & 0x38) | ((insn >> 5) & 7); |
6271 | 9ee6e8bb | pbrook | switch (op1) {
|
6272 | 9ee6e8bb | pbrook | case 0: /* Unsigned sum of absolute differences. */ |
6273 | 6ddbc6e4 | pbrook | ARCH(6);
|
6274 | 6ddbc6e4 | pbrook | tmp = load_reg(s, rm); |
6275 | 6ddbc6e4 | pbrook | tmp2 = load_reg(s, rs); |
6276 | 6ddbc6e4 | pbrook | gen_helper_usad8(tmp, tmp, tmp2); |
6277 | 6ddbc6e4 | pbrook | dead_tmp(tmp2); |
6278 | 9ee6e8bb | pbrook | if (rn != 15) { |
6279 | 6ddbc6e4 | pbrook | tmp2 = load_reg(s, rn); |
6280 | 6ddbc6e4 | pbrook | tcg_gen_add_i32(tmp, tmp, tmp2); |
6281 | 6ddbc6e4 | pbrook | dead_tmp(tmp2); |
6282 | 9ee6e8bb | pbrook | } |
6283 | 6ddbc6e4 | pbrook | store_reg(s, rd, tmp); |
6284 | 9ee6e8bb | pbrook | break;
|
6285 | 9ee6e8bb | pbrook | case 0x20: case 0x24: case 0x28: case 0x2c: |
6286 | 9ee6e8bb | pbrook | /* Bitfield insert/clear. */
|
6287 | 9ee6e8bb | pbrook | ARCH(6T2);
|
6288 | 9ee6e8bb | pbrook | shift = (insn >> 7) & 0x1f; |
6289 | 9ee6e8bb | pbrook | i = (insn >> 16) & 0x1f; |
6290 | 9ee6e8bb | pbrook | i = i + 1 - shift;
|
6291 | 9ee6e8bb | pbrook | if (rm == 15) { |
6292 | 5e3f878a | pbrook | tmp = new_tmp(); |
6293 | 5e3f878a | pbrook | tcg_gen_movi_i32(tmp, 0);
|
6294 | 9ee6e8bb | pbrook | } else {
|
6295 | 5e3f878a | pbrook | tmp = load_reg(s, rm); |
6296 | 9ee6e8bb | pbrook | } |
6297 | 9ee6e8bb | pbrook | if (i != 32) { |
6298 | 5e3f878a | pbrook | tmp2 = load_reg(s, rd); |
6299 | 8f8e3aa4 | pbrook | gen_bfi(tmp, tmp2, tmp, shift, (1u << i) - 1); |
6300 | 5e3f878a | pbrook | dead_tmp(tmp2); |
6301 | 9ee6e8bb | pbrook | } |
6302 | 5e3f878a | pbrook | store_reg(s, rd, tmp); |
6303 | 9ee6e8bb | pbrook | break;
|
6304 | 9ee6e8bb | pbrook | case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */ |
6305 | 9ee6e8bb | pbrook | case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */ |
6306 | 5e3f878a | pbrook | tmp = load_reg(s, rm); |
6307 | 9ee6e8bb | pbrook | shift = (insn >> 7) & 0x1f; |
6308 | 9ee6e8bb | pbrook | i = ((insn >> 16) & 0x1f) + 1; |
6309 | 9ee6e8bb | pbrook | if (shift + i > 32) |
6310 | 9ee6e8bb | pbrook | goto illegal_op;
|
6311 | 9ee6e8bb | pbrook | if (i < 32) { |
6312 | 9ee6e8bb | pbrook | if (op1 & 0x20) { |
6313 | 5e3f878a | pbrook | gen_ubfx(tmp, shift, (1u << i) - 1); |
6314 | 9ee6e8bb | pbrook | } else {
|
6315 | 5e3f878a | pbrook | gen_sbfx(tmp, shift, i); |
6316 | 9ee6e8bb | pbrook | } |
6317 | 9ee6e8bb | pbrook | } |
6318 | 5e3f878a | pbrook | store_reg(s, rd, tmp); |
6319 | 9ee6e8bb | pbrook | break;
|
6320 | 9ee6e8bb | pbrook | default:
|
6321 | 9ee6e8bb | pbrook | goto illegal_op;
|
6322 | 9ee6e8bb | pbrook | } |
6323 | 9ee6e8bb | pbrook | break;
|
6324 | 9ee6e8bb | pbrook | } |
6325 | 9ee6e8bb | pbrook | break;
|
6326 | 9ee6e8bb | pbrook | } |
6327 | 9ee6e8bb | pbrook | do_ldst:
|
6328 | 9ee6e8bb | pbrook | /* Check for undefined extension instructions
|
6329 | 9ee6e8bb | pbrook | * per the ARM Bible IE:
|
6330 | 9ee6e8bb | pbrook | * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx
|
6331 | 9ee6e8bb | pbrook | */
|
6332 | 9ee6e8bb | pbrook | sh = (0xf << 20) | (0xf << 4); |
6333 | 9ee6e8bb | pbrook | if (op1 == 0x7 && ((insn & sh) == sh)) |
6334 | 9ee6e8bb | pbrook | { |
6335 | 9ee6e8bb | pbrook | goto illegal_op;
|
6336 | 9ee6e8bb | pbrook | } |
6337 | 9ee6e8bb | pbrook | /* load/store byte/word */
|
6338 | 9ee6e8bb | pbrook | rn = (insn >> 16) & 0xf; |
6339 | 9ee6e8bb | pbrook | rd = (insn >> 12) & 0xf; |
6340 | b0109805 | pbrook | tmp2 = load_reg(s, rn); |
6341 | 9ee6e8bb | pbrook | i = (IS_USER(s) || (insn & 0x01200000) == 0x00200000); |
6342 | 9ee6e8bb | pbrook | if (insn & (1 << 24)) |
6343 | b0109805 | pbrook | gen_add_data_offset(s, insn, tmp2); |
6344 | 9ee6e8bb | pbrook | if (insn & (1 << 20)) { |
6345 | 9ee6e8bb | pbrook | /* load */
|
6346 | 9ee6e8bb | pbrook | s->is_mem = 1;
|
6347 | 9ee6e8bb | pbrook | if (insn & (1 << 22)) { |
6348 | b0109805 | pbrook | tmp = gen_ld8u(tmp2, i); |
6349 | 9ee6e8bb | pbrook | } else {
|
6350 | b0109805 | pbrook | tmp = gen_ld32(tmp2, i); |
6351 | 9ee6e8bb | pbrook | } |
6352 | 9ee6e8bb | pbrook | } else {
|
6353 | 9ee6e8bb | pbrook | /* store */
|
6354 | b0109805 | pbrook | tmp = load_reg(s, rd); |
6355 | 9ee6e8bb | pbrook | if (insn & (1 << 22)) |
6356 | b0109805 | pbrook | gen_st8(tmp, tmp2, i); |
6357 | 9ee6e8bb | pbrook | else
|
6358 | b0109805 | pbrook | gen_st32(tmp, tmp2, i); |
6359 | 9ee6e8bb | pbrook | } |
6360 | 9ee6e8bb | pbrook | if (!(insn & (1 << 24))) { |
6361 | b0109805 | pbrook | gen_add_data_offset(s, insn, tmp2); |
6362 | b0109805 | pbrook | store_reg(s, rn, tmp2); |
6363 | b0109805 | pbrook | } else if (insn & (1 << 21)) { |
6364 | b0109805 | pbrook | store_reg(s, rn, tmp2); |
6365 | b0109805 | pbrook | } else {
|
6366 | b0109805 | pbrook | dead_tmp(tmp2); |
6367 | 9ee6e8bb | pbrook | } |
6368 | 9ee6e8bb | pbrook | if (insn & (1 << 20)) { |
6369 | 9ee6e8bb | pbrook | /* Complete the load. */
|
6370 | 9ee6e8bb | pbrook | if (rd == 15) |
6371 | b0109805 | pbrook | gen_bx(s, tmp); |
6372 | 9ee6e8bb | pbrook | else
|
6373 | b0109805 | pbrook | store_reg(s, rd, tmp); |
6374 | 9ee6e8bb | pbrook | } |
6375 | 9ee6e8bb | pbrook | break;
|
6376 | 9ee6e8bb | pbrook | case 0x08: |
6377 | 9ee6e8bb | pbrook | case 0x09: |
6378 | 9ee6e8bb | pbrook | { |
6379 | 9ee6e8bb | pbrook | int j, n, user, loaded_base;
|
6380 | b0109805 | pbrook | TCGv loaded_var; |
6381 | 9ee6e8bb | pbrook | /* load/store multiple words */
|
6382 | 9ee6e8bb | pbrook | /* XXX: store correct base if write back */
|
6383 | 9ee6e8bb | pbrook | user = 0;
|
6384 | 9ee6e8bb | pbrook | if (insn & (1 << 22)) { |
6385 | 9ee6e8bb | pbrook | if (IS_USER(s))
|
6386 | 9ee6e8bb | pbrook | goto illegal_op; /* only usable in supervisor mode */ |
6387 | 9ee6e8bb | pbrook | |
6388 | 9ee6e8bb | pbrook | if ((insn & (1 << 15)) == 0) |
6389 | 9ee6e8bb | pbrook | user = 1;
|
6390 | 9ee6e8bb | pbrook | } |
6391 | 9ee6e8bb | pbrook | rn = (insn >> 16) & 0xf; |
6392 | b0109805 | pbrook | addr = load_reg(s, rn); |
6393 | 9ee6e8bb | pbrook | |
6394 | 9ee6e8bb | pbrook | /* compute total size */
|
6395 | 9ee6e8bb | pbrook | loaded_base = 0;
|
6396 | 9ee6e8bb | pbrook | n = 0;
|
6397 | 9ee6e8bb | pbrook | for(i=0;i<16;i++) { |
6398 | 9ee6e8bb | pbrook | if (insn & (1 << i)) |
6399 | 9ee6e8bb | pbrook | n++; |
6400 | 9ee6e8bb | pbrook | } |
6401 | 9ee6e8bb | pbrook | /* XXX: test invalid n == 0 case ? */
|
6402 | 9ee6e8bb | pbrook | if (insn & (1 << 23)) { |
6403 | 9ee6e8bb | pbrook | if (insn & (1 << 24)) { |
6404 | 9ee6e8bb | pbrook | /* pre increment */
|
6405 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, 4);
|
6406 | 9ee6e8bb | pbrook | } else {
|
6407 | 9ee6e8bb | pbrook | /* post increment */
|
6408 | 9ee6e8bb | pbrook | } |
6409 | 9ee6e8bb | pbrook | } else {
|
6410 | 9ee6e8bb | pbrook | if (insn & (1 << 24)) { |
6411 | 9ee6e8bb | pbrook | /* pre decrement */
|
6412 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, -(n * 4));
|
6413 | 9ee6e8bb | pbrook | } else {
|
6414 | 9ee6e8bb | pbrook | /* post decrement */
|
6415 | 9ee6e8bb | pbrook | if (n != 1) |
6416 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, -((n - 1) * 4)); |
6417 | 9ee6e8bb | pbrook | } |
6418 | 9ee6e8bb | pbrook | } |
6419 | 9ee6e8bb | pbrook | j = 0;
|
6420 | 9ee6e8bb | pbrook | for(i=0;i<16;i++) { |
6421 | 9ee6e8bb | pbrook | if (insn & (1 << i)) { |
6422 | 9ee6e8bb | pbrook | if (insn & (1 << 20)) { |
6423 | 9ee6e8bb | pbrook | /* load */
|
6424 | b0109805 | pbrook | tmp = gen_ld32(addr, IS_USER(s)); |
6425 | 9ee6e8bb | pbrook | if (i == 15) { |
6426 | b0109805 | pbrook | gen_bx(s, tmp); |
6427 | 9ee6e8bb | pbrook | } else if (user) { |
6428 | b0109805 | pbrook | gen_helper_set_user_reg(tcg_const_i32(i), tmp); |
6429 | b0109805 | pbrook | dead_tmp(tmp); |
6430 | 9ee6e8bb | pbrook | } else if (i == rn) { |
6431 | b0109805 | pbrook | loaded_var = tmp; |
6432 | 9ee6e8bb | pbrook | loaded_base = 1;
|
6433 | 9ee6e8bb | pbrook | } else {
|
6434 | b0109805 | pbrook | store_reg(s, i, tmp); |
6435 | 9ee6e8bb | pbrook | } |
6436 | 9ee6e8bb | pbrook | } else {
|
6437 | 9ee6e8bb | pbrook | /* store */
|
6438 | 9ee6e8bb | pbrook | if (i == 15) { |
6439 | 9ee6e8bb | pbrook | /* special case: r15 = PC + 8 */
|
6440 | 9ee6e8bb | pbrook | val = (long)s->pc + 4; |
6441 | b0109805 | pbrook | tmp = new_tmp(); |
6442 | b0109805 | pbrook | tcg_gen_movi_i32(tmp, val); |
6443 | 9ee6e8bb | pbrook | } else if (user) { |
6444 | b0109805 | pbrook | tmp = new_tmp(); |
6445 | b0109805 | pbrook | gen_helper_get_user_reg(tmp, tcg_const_i32(i)); |
6446 | 9ee6e8bb | pbrook | } else {
|
6447 | b0109805 | pbrook | tmp = load_reg(s, i); |
6448 | 9ee6e8bb | pbrook | } |
6449 | b0109805 | pbrook | gen_st32(tmp, addr, IS_USER(s)); |
6450 | 9ee6e8bb | pbrook | } |
6451 | 9ee6e8bb | pbrook | j++; |
6452 | 9ee6e8bb | pbrook | /* no need to add after the last transfer */
|
6453 | 9ee6e8bb | pbrook | if (j != n)
|
6454 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, 4);
|
6455 | 9ee6e8bb | pbrook | } |
6456 | 9ee6e8bb | pbrook | } |
6457 | 9ee6e8bb | pbrook | if (insn & (1 << 21)) { |
6458 | 9ee6e8bb | pbrook | /* write back */
|
6459 | 9ee6e8bb | pbrook | if (insn & (1 << 23)) { |
6460 | 9ee6e8bb | pbrook | if (insn & (1 << 24)) { |
6461 | 9ee6e8bb | pbrook | /* pre increment */
|
6462 | 9ee6e8bb | pbrook | } else {
|
6463 | 9ee6e8bb | pbrook | /* post increment */
|
6464 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, 4);
|
6465 | 9ee6e8bb | pbrook | } |
6466 | 9ee6e8bb | pbrook | } else {
|
6467 | 9ee6e8bb | pbrook | if (insn & (1 << 24)) { |
6468 | 9ee6e8bb | pbrook | /* pre decrement */
|
6469 | 9ee6e8bb | pbrook | if (n != 1) |
6470 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, -((n - 1) * 4)); |
6471 | 9ee6e8bb | pbrook | } else {
|
6472 | 9ee6e8bb | pbrook | /* post decrement */
|
6473 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, -(n * 4));
|
6474 | 9ee6e8bb | pbrook | } |
6475 | 9ee6e8bb | pbrook | } |
6476 | b0109805 | pbrook | store_reg(s, rn, addr); |
6477 | b0109805 | pbrook | } else {
|
6478 | b0109805 | pbrook | dead_tmp(addr); |
6479 | 9ee6e8bb | pbrook | } |
6480 | 9ee6e8bb | pbrook | if (loaded_base) {
|
6481 | b0109805 | pbrook | store_reg(s, rn, loaded_var); |
6482 | 9ee6e8bb | pbrook | } |
6483 | 9ee6e8bb | pbrook | if ((insn & (1 << 22)) && !user) { |
6484 | 9ee6e8bb | pbrook | /* Restore CPSR from SPSR. */
|
6485 | d9ba4830 | pbrook | tmp = load_cpu_field(spsr); |
6486 | d9ba4830 | pbrook | gen_set_cpsr(tmp, 0xffffffff);
|
6487 | d9ba4830 | pbrook | dead_tmp(tmp); |
6488 | 9ee6e8bb | pbrook | s->is_jmp = DISAS_UPDATE; |
6489 | 9ee6e8bb | pbrook | } |
6490 | 9ee6e8bb | pbrook | } |
6491 | 9ee6e8bb | pbrook | break;
|
6492 | 9ee6e8bb | pbrook | case 0xa: |
6493 | 9ee6e8bb | pbrook | case 0xb: |
6494 | 9ee6e8bb | pbrook | { |
6495 | 9ee6e8bb | pbrook | int32_t offset; |
6496 | 9ee6e8bb | pbrook | |
6497 | 9ee6e8bb | pbrook | /* branch (and link) */
|
6498 | 9ee6e8bb | pbrook | val = (int32_t)s->pc; |
6499 | 9ee6e8bb | pbrook | if (insn & (1 << 24)) { |
6500 | 5e3f878a | pbrook | tmp = new_tmp(); |
6501 | 5e3f878a | pbrook | tcg_gen_movi_i32(tmp, val); |
6502 | 5e3f878a | pbrook | store_reg(s, 14, tmp);
|
6503 | 9ee6e8bb | pbrook | } |
6504 | 9ee6e8bb | pbrook | offset = (((int32_t)insn << 8) >> 8); |
6505 | 9ee6e8bb | pbrook | val += (offset << 2) + 4; |
6506 | 9ee6e8bb | pbrook | gen_jmp(s, val); |
6507 | 9ee6e8bb | pbrook | } |
6508 | 9ee6e8bb | pbrook | break;
|
6509 | 9ee6e8bb | pbrook | case 0xc: |
6510 | 9ee6e8bb | pbrook | case 0xd: |
6511 | 9ee6e8bb | pbrook | case 0xe: |
6512 | 9ee6e8bb | pbrook | /* Coprocessor. */
|
6513 | 9ee6e8bb | pbrook | if (disas_coproc_insn(env, s, insn))
|
6514 | 9ee6e8bb | pbrook | goto illegal_op;
|
6515 | 9ee6e8bb | pbrook | break;
|
6516 | 9ee6e8bb | pbrook | case 0xf: |
6517 | 9ee6e8bb | pbrook | /* swi */
|
6518 | 5e3f878a | pbrook | gen_set_pc_im(s->pc); |
6519 | 9ee6e8bb | pbrook | s->is_jmp = DISAS_SWI; |
6520 | 9ee6e8bb | pbrook | break;
|
6521 | 9ee6e8bb | pbrook | default:
|
6522 | 9ee6e8bb | pbrook | illegal_op:
|
6523 | 9ee6e8bb | pbrook | gen_set_condexec(s); |
6524 | 5e3f878a | pbrook | gen_set_pc_im(s->pc - 4);
|
6525 | d9ba4830 | pbrook | gen_exception(EXCP_UDEF); |
6526 | 9ee6e8bb | pbrook | s->is_jmp = DISAS_JUMP; |
6527 | 9ee6e8bb | pbrook | break;
|
6528 | 9ee6e8bb | pbrook | } |
6529 | 9ee6e8bb | pbrook | } |
6530 | 9ee6e8bb | pbrook | } |
6531 | 9ee6e8bb | pbrook | |
6532 | 9ee6e8bb | pbrook | /* Return true if this is a Thumb-2 logical op. */
|
6533 | 9ee6e8bb | pbrook | static int |
6534 | 9ee6e8bb | pbrook | thumb2_logic_op(int op)
|
6535 | 9ee6e8bb | pbrook | { |
6536 | 9ee6e8bb | pbrook | return (op < 8); |
6537 | 9ee6e8bb | pbrook | } |
6538 | 9ee6e8bb | pbrook | |
6539 | 9ee6e8bb | pbrook | /* Generate code for a Thumb-2 data processing operation. If CONDS is nonzero
|
6540 | 9ee6e8bb | pbrook | then set condition code flags based on the result of the operation.
|
6541 | 9ee6e8bb | pbrook | If SHIFTER_OUT is nonzero then set the carry flag for logical operations
|
6542 | 9ee6e8bb | pbrook | to the high bit of T1.
|
6543 | 9ee6e8bb | pbrook | Returns zero if the opcode is valid. */
|
6544 | 9ee6e8bb | pbrook | |
6545 | 9ee6e8bb | pbrook | static int |
6546 | 9ee6e8bb | pbrook | gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out) |
6547 | 9ee6e8bb | pbrook | { |
6548 | 9ee6e8bb | pbrook | int logic_cc;
|
6549 | 9ee6e8bb | pbrook | |
6550 | 9ee6e8bb | pbrook | logic_cc = 0;
|
6551 | 9ee6e8bb | pbrook | switch (op) {
|
6552 | 9ee6e8bb | pbrook | case 0: /* and */ |
6553 | 9ee6e8bb | pbrook | gen_op_andl_T0_T1(); |
6554 | 9ee6e8bb | pbrook | logic_cc = conds; |
6555 | 9ee6e8bb | pbrook | break;
|
6556 | 9ee6e8bb | pbrook | case 1: /* bic */ |
6557 | 9ee6e8bb | pbrook | gen_op_bicl_T0_T1(); |
6558 | 9ee6e8bb | pbrook | logic_cc = conds; |
6559 | 9ee6e8bb | pbrook | break;
|
6560 | 9ee6e8bb | pbrook | case 2: /* orr */ |
6561 | 9ee6e8bb | pbrook | gen_op_orl_T0_T1(); |
6562 | 9ee6e8bb | pbrook | logic_cc = conds; |
6563 | 9ee6e8bb | pbrook | break;
|
6564 | 9ee6e8bb | pbrook | case 3: /* orn */ |
6565 | 9ee6e8bb | pbrook | gen_op_notl_T1(); |
6566 | 9ee6e8bb | pbrook | gen_op_orl_T0_T1(); |
6567 | 9ee6e8bb | pbrook | logic_cc = conds; |
6568 | 9ee6e8bb | pbrook | break;
|
6569 | 9ee6e8bb | pbrook | case 4: /* eor */ |
6570 | 9ee6e8bb | pbrook | gen_op_xorl_T0_T1(); |
6571 | 9ee6e8bb | pbrook | logic_cc = conds; |
6572 | 9ee6e8bb | pbrook | break;
|
6573 | 9ee6e8bb | pbrook | case 8: /* add */ |
6574 | 9ee6e8bb | pbrook | if (conds)
|
6575 | 9ee6e8bb | pbrook | gen_op_addl_T0_T1_cc(); |
6576 | 9ee6e8bb | pbrook | else
|
6577 | 9ee6e8bb | pbrook | gen_op_addl_T0_T1(); |
6578 | 9ee6e8bb | pbrook | break;
|
6579 | 9ee6e8bb | pbrook | case 10: /* adc */ |
6580 | 9ee6e8bb | pbrook | if (conds)
|
6581 | 9ee6e8bb | pbrook | gen_op_adcl_T0_T1_cc(); |
6582 | 9ee6e8bb | pbrook | else
|
6583 | b26eefb6 | pbrook | gen_adc_T0_T1(); |
6584 | 9ee6e8bb | pbrook | break;
|
6585 | 9ee6e8bb | pbrook | case 11: /* sbc */ |
6586 | 9ee6e8bb | pbrook | if (conds)
|
6587 | 9ee6e8bb | pbrook | gen_op_sbcl_T0_T1_cc(); |
6588 | 9ee6e8bb | pbrook | else
|
6589 | 3670669c | pbrook | gen_sbc_T0_T1(); |
6590 | 9ee6e8bb | pbrook | break;
|
6591 | 9ee6e8bb | pbrook | case 13: /* sub */ |
6592 | 9ee6e8bb | pbrook | if (conds)
|
6593 | 9ee6e8bb | pbrook | gen_op_subl_T0_T1_cc(); |
6594 | 9ee6e8bb | pbrook | else
|
6595 | 9ee6e8bb | pbrook | gen_op_subl_T0_T1(); |
6596 | 9ee6e8bb | pbrook | break;
|
6597 | 9ee6e8bb | pbrook | case 14: /* rsb */ |
6598 | 9ee6e8bb | pbrook | if (conds)
|
6599 | 9ee6e8bb | pbrook | gen_op_rsbl_T0_T1_cc(); |
6600 | 9ee6e8bb | pbrook | else
|
6601 | 9ee6e8bb | pbrook | gen_op_rsbl_T0_T1(); |
6602 | 9ee6e8bb | pbrook | break;
|
6603 | 9ee6e8bb | pbrook | default: /* 5, 6, 7, 9, 12, 15. */ |
6604 | 9ee6e8bb | pbrook | return 1; |
6605 | 9ee6e8bb | pbrook | } |
6606 | 9ee6e8bb | pbrook | if (logic_cc) {
|
6607 | 9ee6e8bb | pbrook | gen_op_logic_T0_cc(); |
6608 | 9ee6e8bb | pbrook | if (shifter_out)
|
6609 | b26eefb6 | pbrook | gen_set_CF_bit31(cpu_T[1]);
|
6610 | 9ee6e8bb | pbrook | } |
6611 | 9ee6e8bb | pbrook | return 0; |
6612 | 9ee6e8bb | pbrook | } |
6613 | 9ee6e8bb | pbrook | |
6614 | 9ee6e8bb | pbrook | /* Translate a 32-bit thumb instruction. Returns nonzero if the instruction
|
6615 | 9ee6e8bb | pbrook | is not legal. */
|
6616 | 9ee6e8bb | pbrook | static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) |
6617 | 9ee6e8bb | pbrook | { |
6618 | b0109805 | pbrook | uint32_t insn, imm, shift, offset; |
6619 | 9ee6e8bb | pbrook | uint32_t rd, rn, rm, rs; |
6620 | b26eefb6 | pbrook | TCGv tmp; |
6621 | 6ddbc6e4 | pbrook | TCGv tmp2; |
6622 | 6ddbc6e4 | pbrook | TCGv tmp3; |
6623 | b0109805 | pbrook | TCGv addr; |
6624 | 9ee6e8bb | pbrook | int op;
|
6625 | 9ee6e8bb | pbrook | int shiftop;
|
6626 | 9ee6e8bb | pbrook | int conds;
|
6627 | 9ee6e8bb | pbrook | int logic_cc;
|
6628 | 9ee6e8bb | pbrook | |
6629 | 9ee6e8bb | pbrook | if (!(arm_feature(env, ARM_FEATURE_THUMB2)
|
6630 | 9ee6e8bb | pbrook | || arm_feature (env, ARM_FEATURE_M))) { |
6631 | 9ee6e8bb | pbrook | /* Thumb-1 cores may need to tread bl and blx as a pair of
|
6632 | 9ee6e8bb | pbrook | 16-bit instructions to get correct prefetch abort behavior. */
|
6633 | 9ee6e8bb | pbrook | insn = insn_hw1; |
6634 | 9ee6e8bb | pbrook | if ((insn & (1 << 12)) == 0) { |
6635 | 9ee6e8bb | pbrook | /* Second half of blx. */
|
6636 | 9ee6e8bb | pbrook | offset = ((insn & 0x7ff) << 1); |
6637 | d9ba4830 | pbrook | tmp = load_reg(s, 14);
|
6638 | d9ba4830 | pbrook | tcg_gen_addi_i32(tmp, tmp, offset); |
6639 | d9ba4830 | pbrook | tcg_gen_andi_i32(tmp, tmp, 0xfffffffc);
|
6640 | 9ee6e8bb | pbrook | |
6641 | d9ba4830 | pbrook | tmp2 = new_tmp(); |
6642 | b0109805 | pbrook | tcg_gen_movi_i32(tmp2, s->pc | 1);
|
6643 | d9ba4830 | pbrook | store_reg(s, 14, tmp2);
|
6644 | d9ba4830 | pbrook | gen_bx(s, tmp); |
6645 | 9ee6e8bb | pbrook | return 0; |
6646 | 9ee6e8bb | pbrook | } |
6647 | 9ee6e8bb | pbrook | if (insn & (1 << 11)) { |
6648 | 9ee6e8bb | pbrook | /* Second half of bl. */
|
6649 | 9ee6e8bb | pbrook | offset = ((insn & 0x7ff) << 1) | 1; |
6650 | d9ba4830 | pbrook | tmp = load_reg(s, 14);
|
6651 | d9ba4830 | pbrook | tcg_gen_addi_i32(tmp, tmp, 14);
|
6652 | 9ee6e8bb | pbrook | |
6653 | d9ba4830 | pbrook | tmp2 = new_tmp(); |
6654 | b0109805 | pbrook | tcg_gen_movi_i32(tmp2, s->pc | 1);
|
6655 | d9ba4830 | pbrook | store_reg(s, 14, tmp2);
|
6656 | d9ba4830 | pbrook | gen_bx(s, tmp); |
6657 | 9ee6e8bb | pbrook | return 0; |
6658 | 9ee6e8bb | pbrook | } |
6659 | 9ee6e8bb | pbrook | if ((s->pc & ~TARGET_PAGE_MASK) == 0) { |
6660 | 9ee6e8bb | pbrook | /* Instruction spans a page boundary. Implement it as two
|
6661 | 9ee6e8bb | pbrook | 16-bit instructions in case the second half causes an
|
6662 | 9ee6e8bb | pbrook | prefetch abort. */
|
6663 | 9ee6e8bb | pbrook | offset = ((int32_t)insn << 21) >> 9; |
6664 | b0109805 | pbrook | gen_op_movl_T0_im(s->pc + 2 + offset);
|
6665 | 9ee6e8bb | pbrook | gen_movl_reg_T0(s, 14);
|
6666 | 9ee6e8bb | pbrook | return 0; |
6667 | 9ee6e8bb | pbrook | } |
6668 | 9ee6e8bb | pbrook | /* Fall through to 32-bit decode. */
|
6669 | 9ee6e8bb | pbrook | } |
6670 | 9ee6e8bb | pbrook | |
6671 | 9ee6e8bb | pbrook | insn = lduw_code(s->pc); |
6672 | 9ee6e8bb | pbrook | s->pc += 2;
|
6673 | 9ee6e8bb | pbrook | insn |= (uint32_t)insn_hw1 << 16;
|
6674 | 9ee6e8bb | pbrook | |
6675 | 9ee6e8bb | pbrook | if ((insn & 0xf800e800) != 0xf000e800) { |
6676 | 9ee6e8bb | pbrook | ARCH(6T2);
|
6677 | 9ee6e8bb | pbrook | } |
6678 | 9ee6e8bb | pbrook | |
6679 | 9ee6e8bb | pbrook | rn = (insn >> 16) & 0xf; |
6680 | 9ee6e8bb | pbrook | rs = (insn >> 12) & 0xf; |
6681 | 9ee6e8bb | pbrook | rd = (insn >> 8) & 0xf; |
6682 | 9ee6e8bb | pbrook | rm = insn & 0xf;
|
6683 | 9ee6e8bb | pbrook | switch ((insn >> 25) & 0xf) { |
6684 | 9ee6e8bb | pbrook | case 0: case 1: case 2: case 3: |
6685 | 9ee6e8bb | pbrook | /* 16-bit instructions. Should never happen. */
|
6686 | 9ee6e8bb | pbrook | abort(); |
6687 | 9ee6e8bb | pbrook | case 4: |
6688 | 9ee6e8bb | pbrook | if (insn & (1 << 22)) { |
6689 | 9ee6e8bb | pbrook | /* Other load/store, table branch. */
|
6690 | 9ee6e8bb | pbrook | if (insn & 0x01200000) { |
6691 | 9ee6e8bb | pbrook | /* Load/store doubleword. */
|
6692 | 9ee6e8bb | pbrook | if (rn == 15) { |
6693 | b0109805 | pbrook | addr = new_tmp(); |
6694 | b0109805 | pbrook | tcg_gen_movi_i32(addr, s->pc & ~3);
|
6695 | 9ee6e8bb | pbrook | } else {
|
6696 | b0109805 | pbrook | addr = load_reg(s, rn); |
6697 | 9ee6e8bb | pbrook | } |
6698 | 9ee6e8bb | pbrook | offset = (insn & 0xff) * 4; |
6699 | 9ee6e8bb | pbrook | if ((insn & (1 << 23)) == 0) |
6700 | 9ee6e8bb | pbrook | offset = -offset; |
6701 | 9ee6e8bb | pbrook | if (insn & (1 << 24)) { |
6702 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, offset); |
6703 | 9ee6e8bb | pbrook | offset = 0;
|
6704 | 9ee6e8bb | pbrook | } |
6705 | 9ee6e8bb | pbrook | if (insn & (1 << 20)) { |
6706 | 9ee6e8bb | pbrook | /* ldrd */
|
6707 | b0109805 | pbrook | tmp = gen_ld32(addr, IS_USER(s)); |
6708 | b0109805 | pbrook | store_reg(s, rs, tmp); |
6709 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, 4);
|
6710 | b0109805 | pbrook | tmp = gen_ld32(addr, IS_USER(s)); |
6711 | b0109805 | pbrook | store_reg(s, rd, tmp); |
6712 | 9ee6e8bb | pbrook | } else {
|
6713 | 9ee6e8bb | pbrook | /* strd */
|
6714 | b0109805 | pbrook | tmp = load_reg(s, rs); |
6715 | b0109805 | pbrook | gen_st32(tmp, addr, IS_USER(s)); |
6716 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, 4);
|
6717 | b0109805 | pbrook | tmp = load_reg(s, rd); |
6718 | b0109805 | pbrook | gen_st32(tmp, addr, IS_USER(s)); |
6719 | 9ee6e8bb | pbrook | } |
6720 | 9ee6e8bb | pbrook | if (insn & (1 << 21)) { |
6721 | 9ee6e8bb | pbrook | /* Base writeback. */
|
6722 | 9ee6e8bb | pbrook | if (rn == 15) |
6723 | 9ee6e8bb | pbrook | goto illegal_op;
|
6724 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, offset - 4);
|
6725 | b0109805 | pbrook | store_reg(s, rn, addr); |
6726 | b0109805 | pbrook | } else {
|
6727 | b0109805 | pbrook | dead_tmp(addr); |
6728 | 9ee6e8bb | pbrook | } |
6729 | 9ee6e8bb | pbrook | } else if ((insn & (1 << 23)) == 0) { |
6730 | 9ee6e8bb | pbrook | /* Load/store exclusive word. */
|
6731 | 2c0262af | bellard | gen_movl_T1_reg(s, rn); |
6732 | 2c0262af | bellard | if (insn & (1 << 20)) { |
6733 | 8f8e3aa4 | pbrook | gen_helper_mark_exclusive(cpu_env, cpu_T[1]);
|
6734 | 8f8e3aa4 | pbrook | tmp = gen_ld32(addr, IS_USER(s)); |
6735 | 8f8e3aa4 | pbrook | store_reg(s, rd, tmp); |
6736 | 9ee6e8bb | pbrook | } else {
|
6737 | 8f8e3aa4 | pbrook | int label = gen_new_label();
|
6738 | 8f8e3aa4 | pbrook | gen_helper_test_exclusive(cpu_T[0], cpu_env, addr);
|
6739 | 8f8e3aa4 | pbrook | tcg_gen_brcond_i32(TCG_COND_NE, cpu_T[0],
|
6740 | 8f8e3aa4 | pbrook | tcg_const_i32(0), label);
|
6741 | 8f8e3aa4 | pbrook | tmp = load_reg(s, rs); |
6742 | 8f8e3aa4 | pbrook | gen_st32(tmp, cpu_T[1], IS_USER(s));
|
6743 | 8f8e3aa4 | pbrook | gen_set_label(label); |
6744 | 8f8e3aa4 | pbrook | gen_movl_reg_T0(s, rd); |
6745 | 9ee6e8bb | pbrook | } |
6746 | 9ee6e8bb | pbrook | } else if ((insn & (1 << 6)) == 0) { |
6747 | 9ee6e8bb | pbrook | /* Table Branch. */
|
6748 | 9ee6e8bb | pbrook | if (rn == 15) { |
6749 | b0109805 | pbrook | addr = new_tmp(); |
6750 | b0109805 | pbrook | tcg_gen_movi_i32(addr, s->pc); |
6751 | 9ee6e8bb | pbrook | } else {
|
6752 | b0109805 | pbrook | addr = load_reg(s, rn); |
6753 | 9ee6e8bb | pbrook | } |
6754 | b26eefb6 | pbrook | tmp = load_reg(s, rm); |
6755 | b0109805 | pbrook | tcg_gen_add_i32(addr, addr, tmp); |
6756 | 9ee6e8bb | pbrook | if (insn & (1 << 4)) { |
6757 | 9ee6e8bb | pbrook | /* tbh */
|
6758 | b0109805 | pbrook | tcg_gen_add_i32(addr, addr, tmp); |
6759 | b26eefb6 | pbrook | dead_tmp(tmp); |
6760 | b0109805 | pbrook | tmp = gen_ld16u(addr, IS_USER(s)); |
6761 | 9ee6e8bb | pbrook | } else { /* tbb */ |
6762 | b26eefb6 | pbrook | dead_tmp(tmp); |
6763 | b0109805 | pbrook | tmp = gen_ld8u(addr, IS_USER(s)); |
6764 | 9ee6e8bb | pbrook | } |
6765 | b0109805 | pbrook | dead_tmp(addr); |
6766 | b0109805 | pbrook | tcg_gen_shli_i32(tmp, tmp, 1);
|
6767 | b0109805 | pbrook | tcg_gen_addi_i32(tmp, tmp, s->pc); |
6768 | b0109805 | pbrook | store_reg(s, 15, tmp);
|
6769 | 9ee6e8bb | pbrook | } else {
|
6770 | 9ee6e8bb | pbrook | /* Load/store exclusive byte/halfword/doubleword. */
|
6771 | 8f8e3aa4 | pbrook | /* ??? These are not really atomic. However we know
|
6772 | 8f8e3aa4 | pbrook | we never have multiple CPUs running in parallel,
|
6773 | 8f8e3aa4 | pbrook | so it is good enough. */
|
6774 | 9ee6e8bb | pbrook | op = (insn >> 4) & 0x3; |
6775 | 8f8e3aa4 | pbrook | /* Must use a global reg for the address because we have
|
6776 | 8f8e3aa4 | pbrook | a conditional branch in the store instruction. */
|
6777 | 9ee6e8bb | pbrook | gen_movl_T1_reg(s, rn); |
6778 | 8f8e3aa4 | pbrook | addr = cpu_T[1];
|
6779 | 9ee6e8bb | pbrook | if (insn & (1 << 20)) { |
6780 | 8f8e3aa4 | pbrook | gen_helper_mark_exclusive(cpu_env, addr); |
6781 | 9ee6e8bb | pbrook | switch (op) {
|
6782 | 9ee6e8bb | pbrook | case 0: |
6783 | 8f8e3aa4 | pbrook | tmp = gen_ld8u(addr, IS_USER(s)); |
6784 | 9ee6e8bb | pbrook | break;
|
6785 | 2c0262af | bellard | case 1: |
6786 | 8f8e3aa4 | pbrook | tmp = gen_ld16u(addr, IS_USER(s)); |
6787 | 2c0262af | bellard | break;
|
6788 | 9ee6e8bb | pbrook | case 3: |
6789 | 8f8e3aa4 | pbrook | tmp = gen_ld32(addr, IS_USER(s)); |
6790 | 8f8e3aa4 | pbrook | tcg_gen_addi_i32(addr, addr, 4);
|
6791 | 8f8e3aa4 | pbrook | tmp2 = gen_ld32(addr, IS_USER(s)); |
6792 | 8f8e3aa4 | pbrook | store_reg(s, rd, tmp2); |
6793 | 2c0262af | bellard | break;
|
6794 | 2c0262af | bellard | default:
|
6795 | 9ee6e8bb | pbrook | goto illegal_op;
|
6796 | 9ee6e8bb | pbrook | } |
6797 | 8f8e3aa4 | pbrook | store_reg(s, rs, tmp); |
6798 | 9ee6e8bb | pbrook | } else {
|
6799 | 8f8e3aa4 | pbrook | int label = gen_new_label();
|
6800 | 8f8e3aa4 | pbrook | /* Must use a global that is not killed by the branch. */
|
6801 | 8f8e3aa4 | pbrook | gen_helper_test_exclusive(cpu_T[0], cpu_env, addr);
|
6802 | 8f8e3aa4 | pbrook | tcg_gen_brcond_i32(TCG_COND_NE, cpu_T[0], tcg_const_i32(0), |
6803 | 8f8e3aa4 | pbrook | label); |
6804 | 8f8e3aa4 | pbrook | tmp = load_reg(s, rs); |
6805 | 9ee6e8bb | pbrook | switch (op) {
|
6806 | 9ee6e8bb | pbrook | case 0: |
6807 | 8f8e3aa4 | pbrook | gen_st8(tmp, addr, IS_USER(s)); |
6808 | 9ee6e8bb | pbrook | break;
|
6809 | 9ee6e8bb | pbrook | case 1: |
6810 | 8f8e3aa4 | pbrook | gen_st16(tmp, addr, IS_USER(s)); |
6811 | 9ee6e8bb | pbrook | break;
|
6812 | 2c0262af | bellard | case 3: |
6813 | 8f8e3aa4 | pbrook | gen_st32(tmp, addr, IS_USER(s)); |
6814 | 8f8e3aa4 | pbrook | tcg_gen_addi_i32(addr, addr, 4);
|
6815 | 8f8e3aa4 | pbrook | tmp = load_reg(s, rd); |
6816 | 8f8e3aa4 | pbrook | gen_st32(tmp, addr, IS_USER(s)); |
6817 | 2c0262af | bellard | break;
|
6818 | 9ee6e8bb | pbrook | default:
|
6819 | 9ee6e8bb | pbrook | goto illegal_op;
|
6820 | 2c0262af | bellard | } |
6821 | 8f8e3aa4 | pbrook | gen_set_label(label); |
6822 | 9ee6e8bb | pbrook | gen_movl_reg_T0(s, rm); |
6823 | 9ee6e8bb | pbrook | } |
6824 | 9ee6e8bb | pbrook | } |
6825 | 9ee6e8bb | pbrook | } else {
|
6826 | 9ee6e8bb | pbrook | /* Load/store multiple, RFE, SRS. */
|
6827 | 9ee6e8bb | pbrook | if (((insn >> 23) & 1) == ((insn >> 24) & 1)) { |
6828 | 9ee6e8bb | pbrook | /* Not available in user mode. */
|
6829 | b0109805 | pbrook | if (IS_USER(s))
|
6830 | 9ee6e8bb | pbrook | goto illegal_op;
|
6831 | 9ee6e8bb | pbrook | if (insn & (1 << 20)) { |
6832 | 9ee6e8bb | pbrook | /* rfe */
|
6833 | b0109805 | pbrook | addr = load_reg(s, rn); |
6834 | b0109805 | pbrook | if ((insn & (1 << 24)) == 0) |
6835 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, -8);
|
6836 | b0109805 | pbrook | /* Load PC into tmp and CPSR into tmp2. */
|
6837 | b0109805 | pbrook | tmp = gen_ld32(addr, 0);
|
6838 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, 4);
|
6839 | b0109805 | pbrook | tmp2 = gen_ld32(addr, 0);
|
6840 | 9ee6e8bb | pbrook | if (insn & (1 << 21)) { |
6841 | 9ee6e8bb | pbrook | /* Base writeback. */
|
6842 | b0109805 | pbrook | if (insn & (1 << 24)) { |
6843 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, 4);
|
6844 | b0109805 | pbrook | } else {
|
6845 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, -4);
|
6846 | b0109805 | pbrook | } |
6847 | b0109805 | pbrook | store_reg(s, rn, addr); |
6848 | b0109805 | pbrook | } else {
|
6849 | b0109805 | pbrook | dead_tmp(addr); |
6850 | 9ee6e8bb | pbrook | } |
6851 | b0109805 | pbrook | gen_rfe(s, tmp, tmp2); |
6852 | 9ee6e8bb | pbrook | } else {
|
6853 | 9ee6e8bb | pbrook | /* srs */
|
6854 | 9ee6e8bb | pbrook | op = (insn & 0x1f);
|
6855 | 9ee6e8bb | pbrook | if (op == (env->uncached_cpsr & CPSR_M)) {
|
6856 | b0109805 | pbrook | addr = load_reg(s, 13);
|
6857 | 9ee6e8bb | pbrook | } else {
|
6858 | b0109805 | pbrook | addr = new_tmp(); |
6859 | b0109805 | pbrook | gen_helper_get_r13_banked(addr, cpu_env, tcg_const_i32(op)); |
6860 | 9ee6e8bb | pbrook | } |
6861 | 9ee6e8bb | pbrook | if ((insn & (1 << 24)) == 0) { |
6862 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, -8);
|
6863 | 9ee6e8bb | pbrook | } |
6864 | b0109805 | pbrook | tmp = load_reg(s, 14);
|
6865 | b0109805 | pbrook | gen_st32(tmp, addr, 0);
|
6866 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, 4);
|
6867 | b0109805 | pbrook | tmp = new_tmp(); |
6868 | b0109805 | pbrook | gen_helper_cpsr_read(tmp); |
6869 | b0109805 | pbrook | gen_st32(tmp, addr, 0);
|
6870 | 9ee6e8bb | pbrook | if (insn & (1 << 21)) { |
6871 | 9ee6e8bb | pbrook | if ((insn & (1 << 24)) == 0) { |
6872 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, -4);
|
6873 | 9ee6e8bb | pbrook | } else {
|
6874 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, 4);
|
6875 | 9ee6e8bb | pbrook | } |
6876 | 9ee6e8bb | pbrook | if (op == (env->uncached_cpsr & CPSR_M)) {
|
6877 | b0109805 | pbrook | store_reg(s, 13, addr);
|
6878 | 9ee6e8bb | pbrook | } else {
|
6879 | b0109805 | pbrook | gen_helper_set_r13_banked(cpu_env, |
6880 | b0109805 | pbrook | tcg_const_i32(op), addr); |
6881 | 9ee6e8bb | pbrook | } |
6882 | b0109805 | pbrook | } else {
|
6883 | b0109805 | pbrook | dead_tmp(addr); |
6884 | 9ee6e8bb | pbrook | } |
6885 | 9ee6e8bb | pbrook | } |
6886 | 9ee6e8bb | pbrook | } else {
|
6887 | 9ee6e8bb | pbrook | int i;
|
6888 | 9ee6e8bb | pbrook | /* Load/store multiple. */
|
6889 | b0109805 | pbrook | addr = load_reg(s, rn); |
6890 | 9ee6e8bb | pbrook | offset = 0;
|
6891 | 9ee6e8bb | pbrook | for (i = 0; i < 16; i++) { |
6892 | 9ee6e8bb | pbrook | if (insn & (1 << i)) |
6893 | 9ee6e8bb | pbrook | offset += 4;
|
6894 | 9ee6e8bb | pbrook | } |
6895 | 9ee6e8bb | pbrook | if (insn & (1 << 24)) { |
6896 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, -offset); |
6897 | 9ee6e8bb | pbrook | } |
6898 | 9ee6e8bb | pbrook | |
6899 | 9ee6e8bb | pbrook | for (i = 0; i < 16; i++) { |
6900 | 9ee6e8bb | pbrook | if ((insn & (1 << i)) == 0) |
6901 | 9ee6e8bb | pbrook | continue;
|
6902 | 9ee6e8bb | pbrook | if (insn & (1 << 20)) { |
6903 | 9ee6e8bb | pbrook | /* Load. */
|
6904 | b0109805 | pbrook | tmp = gen_ld32(addr, IS_USER(s)); |
6905 | 9ee6e8bb | pbrook | if (i == 15) { |
6906 | b0109805 | pbrook | gen_bx(s, tmp); |
6907 | 9ee6e8bb | pbrook | } else {
|
6908 | b0109805 | pbrook | store_reg(s, i, tmp); |
6909 | 9ee6e8bb | pbrook | } |
6910 | 9ee6e8bb | pbrook | } else {
|
6911 | 9ee6e8bb | pbrook | /* Store. */
|
6912 | b0109805 | pbrook | tmp = load_reg(s, i); |
6913 | b0109805 | pbrook | gen_st32(tmp, addr, IS_USER(s)); |
6914 | 9ee6e8bb | pbrook | } |
6915 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, 4);
|
6916 | 9ee6e8bb | pbrook | } |
6917 | 9ee6e8bb | pbrook | if (insn & (1 << 21)) { |
6918 | 9ee6e8bb | pbrook | /* Base register writeback. */
|
6919 | 9ee6e8bb | pbrook | if (insn & (1 << 24)) { |
6920 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, -offset); |
6921 | 9ee6e8bb | pbrook | } |
6922 | 9ee6e8bb | pbrook | /* Fault if writeback register is in register list. */
|
6923 | 9ee6e8bb | pbrook | if (insn & (1 << rn)) |
6924 | 9ee6e8bb | pbrook | goto illegal_op;
|
6925 | b0109805 | pbrook | store_reg(s, rn, addr); |
6926 | b0109805 | pbrook | } else {
|
6927 | b0109805 | pbrook | dead_tmp(addr); |
6928 | 9ee6e8bb | pbrook | } |
6929 | 9ee6e8bb | pbrook | } |
6930 | 9ee6e8bb | pbrook | } |
6931 | 9ee6e8bb | pbrook | break;
|
6932 | 9ee6e8bb | pbrook | case 5: /* Data processing register constant shift. */ |
6933 | 9ee6e8bb | pbrook | if (rn == 15) |
6934 | 9ee6e8bb | pbrook | gen_op_movl_T0_im(0);
|
6935 | 9ee6e8bb | pbrook | else
|
6936 | 9ee6e8bb | pbrook | gen_movl_T0_reg(s, rn); |
6937 | 9ee6e8bb | pbrook | gen_movl_T1_reg(s, rm); |
6938 | 9ee6e8bb | pbrook | op = (insn >> 21) & 0xf; |
6939 | 9ee6e8bb | pbrook | shiftop = (insn >> 4) & 3; |
6940 | 9ee6e8bb | pbrook | shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c); |
6941 | 9ee6e8bb | pbrook | conds = (insn & (1 << 20)) != 0; |
6942 | 9ee6e8bb | pbrook | logic_cc = (conds && thumb2_logic_op(op)); |
6943 | 9a119ff6 | pbrook | gen_arm_shift_im(cpu_T[1], shiftop, shift, logic_cc);
|
6944 | 9ee6e8bb | pbrook | if (gen_thumb2_data_op(s, op, conds, 0)) |
6945 | 9ee6e8bb | pbrook | goto illegal_op;
|
6946 | 9ee6e8bb | pbrook | if (rd != 15) |
6947 | 9ee6e8bb | pbrook | gen_movl_reg_T0(s, rd); |
6948 | 9ee6e8bb | pbrook | break;
|
6949 | 9ee6e8bb | pbrook | case 13: /* Misc data processing. */ |
6950 | 9ee6e8bb | pbrook | op = ((insn >> 22) & 6) | ((insn >> 7) & 1); |
6951 | 9ee6e8bb | pbrook | if (op < 4 && (insn & 0xf000) != 0xf000) |
6952 | 9ee6e8bb | pbrook | goto illegal_op;
|
6953 | 9ee6e8bb | pbrook | switch (op) {
|
6954 | 9ee6e8bb | pbrook | case 0: /* Register controlled shift. */ |
6955 | 8984bd2e | pbrook | tmp = load_reg(s, rn); |
6956 | 8984bd2e | pbrook | tmp2 = load_reg(s, rm); |
6957 | 9ee6e8bb | pbrook | if ((insn & 0x70) != 0) |
6958 | 9ee6e8bb | pbrook | goto illegal_op;
|
6959 | 9ee6e8bb | pbrook | op = (insn >> 21) & 3; |
6960 | 8984bd2e | pbrook | logic_cc = (insn & (1 << 20)) != 0; |
6961 | 8984bd2e | pbrook | gen_arm_shift_reg(tmp, op, tmp2, logic_cc); |
6962 | 8984bd2e | pbrook | if (logic_cc)
|
6963 | 8984bd2e | pbrook | gen_logic_CC(tmp); |
6964 | 8984bd2e | pbrook | store_reg(s, rd, tmp); |
6965 | 9ee6e8bb | pbrook | break;
|
6966 | 9ee6e8bb | pbrook | case 1: /* Sign/zero extend. */ |
6967 | 5e3f878a | pbrook | tmp = load_reg(s, rm); |
6968 | 9ee6e8bb | pbrook | shift = (insn >> 4) & 3; |
6969 | 9ee6e8bb | pbrook | /* ??? In many cases it's not neccessary to do a
|
6970 | 9ee6e8bb | pbrook | rotate, a shift is sufficient. */
|
6971 | 9ee6e8bb | pbrook | if (shift != 0) |
6972 | 5e3f878a | pbrook | tcg_gen_rori_i32(tmp, tmp, shift * 8);
|
6973 | 9ee6e8bb | pbrook | op = (insn >> 20) & 7; |
6974 | 9ee6e8bb | pbrook | switch (op) {
|
6975 | 5e3f878a | pbrook | case 0: gen_sxth(tmp); break; |
6976 | 5e3f878a | pbrook | case 1: gen_uxth(tmp); break; |
6977 | 5e3f878a | pbrook | case 2: gen_sxtb16(tmp); break; |
6978 | 5e3f878a | pbrook | case 3: gen_uxtb16(tmp); break; |
6979 | 5e3f878a | pbrook | case 4: gen_sxtb(tmp); break; |
6980 | 5e3f878a | pbrook | case 5: gen_uxtb(tmp); break; |
6981 | 9ee6e8bb | pbrook | default: goto illegal_op; |
6982 | 9ee6e8bb | pbrook | } |
6983 | 9ee6e8bb | pbrook | if (rn != 15) { |
6984 | 5e3f878a | pbrook | tmp2 = load_reg(s, rn); |
6985 | 9ee6e8bb | pbrook | if ((op >> 1) == 1) { |
6986 | 5e3f878a | pbrook | gen_add16(tmp, tmp2); |
6987 | 9ee6e8bb | pbrook | } else {
|
6988 | 5e3f878a | pbrook | tcg_gen_add_i32(tmp, tmp, tmp2); |
6989 | 5e3f878a | pbrook | dead_tmp(tmp2); |
6990 | 9ee6e8bb | pbrook | } |
6991 | 9ee6e8bb | pbrook | } |
6992 | 5e3f878a | pbrook | store_reg(s, rd, tmp); |
6993 | 9ee6e8bb | pbrook | break;
|
6994 | 9ee6e8bb | pbrook | case 2: /* SIMD add/subtract. */ |
6995 | 9ee6e8bb | pbrook | op = (insn >> 20) & 7; |
6996 | 9ee6e8bb | pbrook | shift = (insn >> 4) & 7; |
6997 | 9ee6e8bb | pbrook | if ((op & 3) == 3 || (shift & 3) == 3) |
6998 | 9ee6e8bb | pbrook | goto illegal_op;
|
6999 | 6ddbc6e4 | pbrook | tmp = load_reg(s, rn); |
7000 | 6ddbc6e4 | pbrook | tmp2 = load_reg(s, rm); |
7001 | 6ddbc6e4 | pbrook | gen_thumb2_parallel_addsub(op, shift, tmp, tmp2); |
7002 | 6ddbc6e4 | pbrook | dead_tmp(tmp2); |
7003 | 6ddbc6e4 | pbrook | store_reg(s, rd, tmp); |
7004 | 9ee6e8bb | pbrook | break;
|
7005 | 9ee6e8bb | pbrook | case 3: /* Other data processing. */ |
7006 | 9ee6e8bb | pbrook | op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7); |
7007 | 9ee6e8bb | pbrook | if (op < 4) { |
7008 | 9ee6e8bb | pbrook | /* Saturating add/subtract. */
|
7009 | d9ba4830 | pbrook | tmp = load_reg(s, rn); |
7010 | d9ba4830 | pbrook | tmp2 = load_reg(s, rm); |
7011 | 9ee6e8bb | pbrook | if (op & 2) |
7012 | d9ba4830 | pbrook | gen_helper_double_saturate(tmp, tmp); |
7013 | 9ee6e8bb | pbrook | if (op & 1) |
7014 | d9ba4830 | pbrook | gen_helper_sub_saturate(tmp, tmp2, tmp); |
7015 | 9ee6e8bb | pbrook | else
|
7016 | d9ba4830 | pbrook | gen_helper_add_saturate(tmp, tmp, tmp2); |
7017 | d9ba4830 | pbrook | dead_tmp(tmp2); |
7018 | 9ee6e8bb | pbrook | } else {
|
7019 | d9ba4830 | pbrook | tmp = load_reg(s, rn); |
7020 | 9ee6e8bb | pbrook | switch (op) {
|
7021 | 9ee6e8bb | pbrook | case 0x0a: /* rbit */ |
7022 | d9ba4830 | pbrook | gen_helper_rbit(tmp, tmp); |
7023 | 9ee6e8bb | pbrook | break;
|
7024 | 9ee6e8bb | pbrook | case 0x08: /* rev */ |
7025 | d9ba4830 | pbrook | tcg_gen_bswap_i32(tmp, tmp); |
7026 | 9ee6e8bb | pbrook | break;
|
7027 | 9ee6e8bb | pbrook | case 0x09: /* rev16 */ |
7028 | d9ba4830 | pbrook | gen_rev16(tmp); |
7029 | 9ee6e8bb | pbrook | break;
|
7030 | 9ee6e8bb | pbrook | case 0x0b: /* revsh */ |
7031 | d9ba4830 | pbrook | gen_revsh(tmp); |
7032 | 9ee6e8bb | pbrook | break;
|
7033 | 9ee6e8bb | pbrook | case 0x10: /* sel */ |
7034 | d9ba4830 | pbrook | tmp2 = load_reg(s, rm); |
7035 | 6ddbc6e4 | pbrook | tmp3 = new_tmp(); |
7036 | 6ddbc6e4 | pbrook | tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE)); |
7037 | d9ba4830 | pbrook | gen_helper_sel_flags(tmp, tmp3, tmp, tmp2); |
7038 | 6ddbc6e4 | pbrook | dead_tmp(tmp3); |
7039 | d9ba4830 | pbrook | dead_tmp(tmp2); |
7040 | 9ee6e8bb | pbrook | break;
|
7041 | 9ee6e8bb | pbrook | case 0x18: /* clz */ |
7042 | d9ba4830 | pbrook | gen_helper_clz(tmp, tmp); |
7043 | 9ee6e8bb | pbrook | break;
|
7044 | 9ee6e8bb | pbrook | default:
|
7045 | 9ee6e8bb | pbrook | goto illegal_op;
|
7046 | 9ee6e8bb | pbrook | } |
7047 | 9ee6e8bb | pbrook | } |
7048 | d9ba4830 | pbrook | store_reg(s, rd, tmp); |
7049 | 9ee6e8bb | pbrook | break;
|
7050 | 9ee6e8bb | pbrook | case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */ |
7051 | 9ee6e8bb | pbrook | op = (insn >> 4) & 0xf; |
7052 | d9ba4830 | pbrook | tmp = load_reg(s, rn); |
7053 | d9ba4830 | pbrook | tmp2 = load_reg(s, rm); |
7054 | 9ee6e8bb | pbrook | switch ((insn >> 20) & 7) { |
7055 | 9ee6e8bb | pbrook | case 0: /* 32 x 32 -> 32 */ |
7056 | d9ba4830 | pbrook | tcg_gen_mul_i32(tmp, tmp, tmp2); |
7057 | d9ba4830 | pbrook | dead_tmp(tmp2); |
7058 | 9ee6e8bb | pbrook | if (rs != 15) { |
7059 | d9ba4830 | pbrook | tmp2 = load_reg(s, rs); |
7060 | 9ee6e8bb | pbrook | if (op)
|
7061 | d9ba4830 | pbrook | tcg_gen_sub_i32(tmp, tmp2, tmp); |
7062 | 9ee6e8bb | pbrook | else
|
7063 | d9ba4830 | pbrook | tcg_gen_add_i32(tmp, tmp, tmp2); |
7064 | d9ba4830 | pbrook | dead_tmp(tmp2); |
7065 | 9ee6e8bb | pbrook | } |
7066 | 9ee6e8bb | pbrook | break;
|
7067 | 9ee6e8bb | pbrook | case 1: /* 16 x 16 -> 32 */ |
7068 | d9ba4830 | pbrook | gen_mulxy(tmp, tmp2, op & 2, op & 1); |
7069 | d9ba4830 | pbrook | dead_tmp(tmp2); |
7070 | 9ee6e8bb | pbrook | if (rs != 15) { |
7071 | d9ba4830 | pbrook | tmp2 = load_reg(s, rs); |
7072 | d9ba4830 | pbrook | gen_helper_add_setq(tmp, tmp, tmp2); |
7073 | d9ba4830 | pbrook | dead_tmp(tmp2); |
7074 | 9ee6e8bb | pbrook | } |
7075 | 9ee6e8bb | pbrook | break;
|
7076 | 9ee6e8bb | pbrook | case 2: /* Dual multiply add. */ |
7077 | 9ee6e8bb | pbrook | case 4: /* Dual multiply subtract. */ |
7078 | 9ee6e8bb | pbrook | if (op)
|
7079 | d9ba4830 | pbrook | gen_swap_half(tmp2); |
7080 | d9ba4830 | pbrook | gen_smul_dual(tmp, tmp2); |
7081 | 9ee6e8bb | pbrook | /* This addition cannot overflow. */
|
7082 | 9ee6e8bb | pbrook | if (insn & (1 << 22)) { |
7083 | d9ba4830 | pbrook | tcg_gen_sub_i32(tmp, tmp, tmp2); |
7084 | 9ee6e8bb | pbrook | } else {
|
7085 | d9ba4830 | pbrook | tcg_gen_add_i32(tmp, tmp, tmp2); |
7086 | 9ee6e8bb | pbrook | } |
7087 | d9ba4830 | pbrook | dead_tmp(tmp2); |
7088 | 9ee6e8bb | pbrook | if (rs != 15) |
7089 | 9ee6e8bb | pbrook | { |
7090 | d9ba4830 | pbrook | tmp2 = load_reg(s, rs); |
7091 | d9ba4830 | pbrook | gen_helper_add_setq(tmp, tmp, tmp2); |
7092 | d9ba4830 | pbrook | dead_tmp(tmp2); |
7093 | 9ee6e8bb | pbrook | } |
7094 | 9ee6e8bb | pbrook | break;
|
7095 | 9ee6e8bb | pbrook | case 3: /* 32 * 16 -> 32msb */ |
7096 | 9ee6e8bb | pbrook | if (op)
|
7097 | d9ba4830 | pbrook | tcg_gen_sari_i32(tmp2, tmp2, 16);
|
7098 | 9ee6e8bb | pbrook | else
|
7099 | d9ba4830 | pbrook | gen_sxth(tmp2); |
7100 | 5e3f878a | pbrook | tmp2 = gen_muls_i64_i32(tmp, tmp2); |
7101 | 5e3f878a | pbrook | tcg_gen_shri_i64(tmp2, tmp2, 16);
|
7102 | 5e3f878a | pbrook | tmp = new_tmp(); |
7103 | 5e3f878a | pbrook | tcg_gen_trunc_i64_i32(tmp, tmp2); |
7104 | 9ee6e8bb | pbrook | if (rs != 15) |
7105 | 9ee6e8bb | pbrook | { |
7106 | d9ba4830 | pbrook | tmp2 = load_reg(s, rs); |
7107 | d9ba4830 | pbrook | gen_helper_add_setq(tmp, tmp, tmp2); |
7108 | d9ba4830 | pbrook | dead_tmp(tmp2); |
7109 | 9ee6e8bb | pbrook | } |
7110 | 9ee6e8bb | pbrook | break;
|
7111 | 9ee6e8bb | pbrook | case 5: case 6: /* 32 * 32 -> 32msb */ |
7112 | d9ba4830 | pbrook | gen_imull(tmp, tmp2); |
7113 | d9ba4830 | pbrook | if (insn & (1 << 5)) { |
7114 | d9ba4830 | pbrook | gen_roundqd(tmp, tmp2); |
7115 | d9ba4830 | pbrook | dead_tmp(tmp2); |
7116 | d9ba4830 | pbrook | } else {
|
7117 | d9ba4830 | pbrook | dead_tmp(tmp); |
7118 | d9ba4830 | pbrook | tmp = tmp2; |
7119 | d9ba4830 | pbrook | } |
7120 | 9ee6e8bb | pbrook | if (rs != 15) { |
7121 | d9ba4830 | pbrook | tmp2 = load_reg(s, rs); |
7122 | 9ee6e8bb | pbrook | if (insn & (1 << 21)) { |
7123 | d9ba4830 | pbrook | tcg_gen_add_i32(tmp, tmp, tmp2); |
7124 | 99c475ab | bellard | } else {
|
7125 | d9ba4830 | pbrook | tcg_gen_sub_i32(tmp, tmp2, tmp); |
7126 | 99c475ab | bellard | } |
7127 | d9ba4830 | pbrook | dead_tmp(tmp2); |
7128 | 2c0262af | bellard | } |
7129 | 9ee6e8bb | pbrook | break;
|
7130 | 9ee6e8bb | pbrook | case 7: /* Unsigned sum of absolute differences. */ |
7131 | d9ba4830 | pbrook | gen_helper_usad8(tmp, tmp, tmp2); |
7132 | d9ba4830 | pbrook | dead_tmp(tmp2); |
7133 | 9ee6e8bb | pbrook | if (rs != 15) { |
7134 | d9ba4830 | pbrook | tmp2 = load_reg(s, rs); |
7135 | d9ba4830 | pbrook | tcg_gen_add_i32(tmp, tmp, tmp2); |
7136 | d9ba4830 | pbrook | dead_tmp(tmp2); |
7137 | 5fd46862 | pbrook | } |
7138 | 9ee6e8bb | pbrook | break;
|
7139 | 2c0262af | bellard | } |
7140 | d9ba4830 | pbrook | store_reg(s, rd, tmp); |
7141 | 2c0262af | bellard | break;
|
7142 | 9ee6e8bb | pbrook | case 6: case 7: /* 64-bit multiply, Divide. */ |
7143 | 9ee6e8bb | pbrook | op = ((insn >> 4) & 0xf) | ((insn >> 16) & 0x70); |
7144 | 5e3f878a | pbrook | tmp = load_reg(s, rn); |
7145 | 5e3f878a | pbrook | tmp2 = load_reg(s, rm); |
7146 | 9ee6e8bb | pbrook | if ((op & 0x50) == 0x10) { |
7147 | 9ee6e8bb | pbrook | /* sdiv, udiv */
|
7148 | 9ee6e8bb | pbrook | if (!arm_feature(env, ARM_FEATURE_DIV))
|
7149 | 9ee6e8bb | pbrook | goto illegal_op;
|
7150 | 9ee6e8bb | pbrook | if (op & 0x20) |
7151 | 5e3f878a | pbrook | gen_helper_udiv(tmp, tmp, tmp2); |
7152 | 2c0262af | bellard | else
|
7153 | 5e3f878a | pbrook | gen_helper_sdiv(tmp, tmp, tmp2); |
7154 | 5e3f878a | pbrook | dead_tmp(tmp2); |
7155 | 5e3f878a | pbrook | store_reg(s, rd, tmp); |
7156 | 9ee6e8bb | pbrook | } else if ((op & 0xe) == 0xc) { |
7157 | 9ee6e8bb | pbrook | /* Dual multiply accumulate long. */
|
7158 | 9ee6e8bb | pbrook | if (op & 1) |
7159 | 5e3f878a | pbrook | gen_swap_half(tmp2); |
7160 | 5e3f878a | pbrook | gen_smul_dual(tmp, tmp2); |
7161 | 9ee6e8bb | pbrook | if (op & 0x10) { |
7162 | 5e3f878a | pbrook | tcg_gen_sub_i32(tmp, tmp, tmp2); |
7163 | b5ff1b31 | bellard | } else {
|
7164 | 5e3f878a | pbrook | tcg_gen_add_i32(tmp, tmp, tmp2); |
7165 | b5ff1b31 | bellard | } |
7166 | 5e3f878a | pbrook | dead_tmp(tmp2); |
7167 | 5e3f878a | pbrook | tmp2 = tcg_temp_new(TCG_TYPE_I64); |
7168 | 5e3f878a | pbrook | gen_addq(s, tmp, rs, rd); |
7169 | 5e3f878a | pbrook | gen_storeq_reg(s, rs, rd, tmp); |
7170 | 2c0262af | bellard | } else {
|
7171 | 9ee6e8bb | pbrook | if (op & 0x20) { |
7172 | 9ee6e8bb | pbrook | /* Unsigned 64-bit multiply */
|
7173 | 5e3f878a | pbrook | tmp = gen_mulu_i64_i32(tmp, tmp2); |
7174 | b5ff1b31 | bellard | } else {
|
7175 | 9ee6e8bb | pbrook | if (op & 8) { |
7176 | 9ee6e8bb | pbrook | /* smlalxy */
|
7177 | 5e3f878a | pbrook | gen_mulxy(tmp, tmp2, op & 2, op & 1); |
7178 | 5e3f878a | pbrook | dead_tmp(tmp2); |
7179 | 5e3f878a | pbrook | tmp2 = tcg_temp_new(TCG_TYPE_I64); |
7180 | 5e3f878a | pbrook | tcg_gen_ext_i32_i64(tmp2, tmp); |
7181 | 5e3f878a | pbrook | dead_tmp(tmp); |
7182 | 5e3f878a | pbrook | tmp = tmp2; |
7183 | 9ee6e8bb | pbrook | } else {
|
7184 | 9ee6e8bb | pbrook | /* Signed 64-bit multiply */
|
7185 | 5e3f878a | pbrook | tmp = gen_muls_i64_i32(tmp, tmp2); |
7186 | 9ee6e8bb | pbrook | } |
7187 | b5ff1b31 | bellard | } |
7188 | 9ee6e8bb | pbrook | if (op & 4) { |
7189 | 9ee6e8bb | pbrook | /* umaal */
|
7190 | 5e3f878a | pbrook | gen_addq_lo(s, tmp, rs); |
7191 | 5e3f878a | pbrook | gen_addq_lo(s, tmp, rd); |
7192 | 9ee6e8bb | pbrook | } else if (op & 0x40) { |
7193 | 9ee6e8bb | pbrook | /* 64-bit accumulate. */
|
7194 | 5e3f878a | pbrook | gen_addq(s, tmp, rs, rd); |
7195 | 9ee6e8bb | pbrook | } |
7196 | 5e3f878a | pbrook | gen_storeq_reg(s, rs, rd, tmp); |
7197 | 5fd46862 | pbrook | } |
7198 | 2c0262af | bellard | break;
|
7199 | 9ee6e8bb | pbrook | } |
7200 | 9ee6e8bb | pbrook | break;
|
7201 | 9ee6e8bb | pbrook | case 6: case 7: case 14: case 15: |
7202 | 9ee6e8bb | pbrook | /* Coprocessor. */
|
7203 | 9ee6e8bb | pbrook | if (((insn >> 24) & 3) == 3) { |
7204 | 9ee6e8bb | pbrook | /* Translate into the equivalent ARM encoding. */
|
7205 | 9ee6e8bb | pbrook | insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4); |
7206 | 9ee6e8bb | pbrook | if (disas_neon_data_insn(env, s, insn))
|
7207 | 9ee6e8bb | pbrook | goto illegal_op;
|
7208 | 9ee6e8bb | pbrook | } else {
|
7209 | 9ee6e8bb | pbrook | if (insn & (1 << 28)) |
7210 | 9ee6e8bb | pbrook | goto illegal_op;
|
7211 | 9ee6e8bb | pbrook | if (disas_coproc_insn (env, s, insn))
|
7212 | 9ee6e8bb | pbrook | goto illegal_op;
|
7213 | 9ee6e8bb | pbrook | } |
7214 | 9ee6e8bb | pbrook | break;
|
7215 | 9ee6e8bb | pbrook | case 8: case 9: case 10: case 11: |
7216 | 9ee6e8bb | pbrook | if (insn & (1 << 15)) { |
7217 | 9ee6e8bb | pbrook | /* Branches, misc control. */
|
7218 | 9ee6e8bb | pbrook | if (insn & 0x5000) { |
7219 | 9ee6e8bb | pbrook | /* Unconditional branch. */
|
7220 | 9ee6e8bb | pbrook | /* signextend(hw1[10:0]) -> offset[:12]. */
|
7221 | 9ee6e8bb | pbrook | offset = ((int32_t)insn << 5) >> 9 & ~(int32_t)0xfff; |
7222 | 9ee6e8bb | pbrook | /* hw1[10:0] -> offset[11:1]. */
|
7223 | 9ee6e8bb | pbrook | offset |= (insn & 0x7ff) << 1; |
7224 | 9ee6e8bb | pbrook | /* (~hw2[13, 11] ^ offset[24]) -> offset[23,22]
|
7225 | 9ee6e8bb | pbrook | offset[24:22] already have the same value because of the
|
7226 | 9ee6e8bb | pbrook | sign extension above. */
|
7227 | 9ee6e8bb | pbrook | offset ^= ((~insn) & (1 << 13)) << 10; |
7228 | 9ee6e8bb | pbrook | offset ^= ((~insn) & (1 << 11)) << 11; |
7229 | 9ee6e8bb | pbrook | |
7230 | 9ee6e8bb | pbrook | if (insn & (1 << 14)) { |
7231 | 9ee6e8bb | pbrook | /* Branch and link. */
|
7232 | b0109805 | pbrook | gen_op_movl_T1_im(s->pc | 1);
|
7233 | 9ee6e8bb | pbrook | gen_movl_reg_T1(s, 14);
|
7234 | b5ff1b31 | bellard | } |
7235 | 3b46e624 | ths | |
7236 | b0109805 | pbrook | offset += s->pc; |
7237 | 9ee6e8bb | pbrook | if (insn & (1 << 12)) { |
7238 | 9ee6e8bb | pbrook | /* b/bl */
|
7239 | b0109805 | pbrook | gen_jmp(s, offset); |
7240 | 9ee6e8bb | pbrook | } else {
|
7241 | 9ee6e8bb | pbrook | /* blx */
|
7242 | b0109805 | pbrook | offset &= ~(uint32_t)2;
|
7243 | b0109805 | pbrook | gen_bx_im(s, offset); |
7244 | 2c0262af | bellard | } |
7245 | 9ee6e8bb | pbrook | } else if (((insn >> 23) & 7) == 7) { |
7246 | 9ee6e8bb | pbrook | /* Misc control */
|
7247 | 9ee6e8bb | pbrook | if (insn & (1 << 13)) |
7248 | 9ee6e8bb | pbrook | goto illegal_op;
|
7249 | 9ee6e8bb | pbrook | |
7250 | 9ee6e8bb | pbrook | if (insn & (1 << 26)) { |
7251 | 9ee6e8bb | pbrook | /* Secure monitor call (v6Z) */
|
7252 | 9ee6e8bb | pbrook | goto illegal_op; /* not implemented. */ |
7253 | 2c0262af | bellard | } else {
|
7254 | 9ee6e8bb | pbrook | op = (insn >> 20) & 7; |
7255 | 9ee6e8bb | pbrook | switch (op) {
|
7256 | 9ee6e8bb | pbrook | case 0: /* msr cpsr. */ |
7257 | 9ee6e8bb | pbrook | if (IS_M(env)) {
|
7258 | 8984bd2e | pbrook | tmp = load_reg(s, rn); |
7259 | 8984bd2e | pbrook | addr = tcg_const_i32(insn & 0xff);
|
7260 | 8984bd2e | pbrook | gen_helper_v7m_msr(cpu_env, addr, tmp); |
7261 | 9ee6e8bb | pbrook | gen_lookup_tb(s); |
7262 | 9ee6e8bb | pbrook | break;
|
7263 | 9ee6e8bb | pbrook | } |
7264 | 9ee6e8bb | pbrook | /* fall through */
|
7265 | 9ee6e8bb | pbrook | case 1: /* msr spsr. */ |
7266 | 9ee6e8bb | pbrook | if (IS_M(env))
|
7267 | 9ee6e8bb | pbrook | goto illegal_op;
|
7268 | 9ee6e8bb | pbrook | gen_movl_T0_reg(s, rn); |
7269 | 9ee6e8bb | pbrook | if (gen_set_psr_T0(s,
|
7270 | 9ee6e8bb | pbrook | msr_mask(env, s, (insn >> 8) & 0xf, op == 1), |
7271 | 9ee6e8bb | pbrook | op == 1))
|
7272 | 9ee6e8bb | pbrook | goto illegal_op;
|
7273 | 9ee6e8bb | pbrook | break;
|
7274 | 9ee6e8bb | pbrook | case 2: /* cps, nop-hint. */ |
7275 | 9ee6e8bb | pbrook | if (((insn >> 8) & 7) == 0) { |
7276 | 9ee6e8bb | pbrook | gen_nop_hint(s, insn & 0xff);
|
7277 | 9ee6e8bb | pbrook | } |
7278 | 9ee6e8bb | pbrook | /* Implemented as NOP in user mode. */
|
7279 | 9ee6e8bb | pbrook | if (IS_USER(s))
|
7280 | 9ee6e8bb | pbrook | break;
|
7281 | 9ee6e8bb | pbrook | offset = 0;
|
7282 | 9ee6e8bb | pbrook | imm = 0;
|
7283 | 9ee6e8bb | pbrook | if (insn & (1 << 10)) { |
7284 | 9ee6e8bb | pbrook | if (insn & (1 << 7)) |
7285 | 9ee6e8bb | pbrook | offset |= CPSR_A; |
7286 | 9ee6e8bb | pbrook | if (insn & (1 << 6)) |
7287 | 9ee6e8bb | pbrook | offset |= CPSR_I; |
7288 | 9ee6e8bb | pbrook | if (insn & (1 << 5)) |
7289 | 9ee6e8bb | pbrook | offset |= CPSR_F; |
7290 | 9ee6e8bb | pbrook | if (insn & (1 << 9)) |
7291 | 9ee6e8bb | pbrook | imm = CPSR_A | CPSR_I | CPSR_F; |
7292 | 9ee6e8bb | pbrook | } |
7293 | 9ee6e8bb | pbrook | if (insn & (1 << 8)) { |
7294 | 9ee6e8bb | pbrook | offset |= 0x1f;
|
7295 | 9ee6e8bb | pbrook | imm |= (insn & 0x1f);
|
7296 | 9ee6e8bb | pbrook | } |
7297 | 9ee6e8bb | pbrook | if (offset) {
|
7298 | 9ee6e8bb | pbrook | gen_op_movl_T0_im(imm); |
7299 | 9ee6e8bb | pbrook | gen_set_psr_T0(s, offset, 0);
|
7300 | 9ee6e8bb | pbrook | } |
7301 | 9ee6e8bb | pbrook | break;
|
7302 | 9ee6e8bb | pbrook | case 3: /* Special control operations. */ |
7303 | 9ee6e8bb | pbrook | op = (insn >> 4) & 0xf; |
7304 | 9ee6e8bb | pbrook | switch (op) {
|
7305 | 9ee6e8bb | pbrook | case 2: /* clrex */ |
7306 | 8f8e3aa4 | pbrook | gen_helper_clrex(cpu_env); |
7307 | 9ee6e8bb | pbrook | break;
|
7308 | 9ee6e8bb | pbrook | case 4: /* dsb */ |
7309 | 9ee6e8bb | pbrook | case 5: /* dmb */ |
7310 | 9ee6e8bb | pbrook | case 6: /* isb */ |
7311 | 9ee6e8bb | pbrook | /* These execute as NOPs. */
|
7312 | 9ee6e8bb | pbrook | ARCH(7);
|
7313 | 9ee6e8bb | pbrook | break;
|
7314 | 9ee6e8bb | pbrook | default:
|
7315 | 9ee6e8bb | pbrook | goto illegal_op;
|
7316 | 9ee6e8bb | pbrook | } |
7317 | 9ee6e8bb | pbrook | break;
|
7318 | 9ee6e8bb | pbrook | case 4: /* bxj */ |
7319 | 9ee6e8bb | pbrook | /* Trivial implementation equivalent to bx. */
|
7320 | d9ba4830 | pbrook | tmp = load_reg(s, rn); |
7321 | d9ba4830 | pbrook | gen_bx(s, tmp); |
7322 | 9ee6e8bb | pbrook | break;
|
7323 | 9ee6e8bb | pbrook | case 5: /* Exception return. */ |
7324 | 9ee6e8bb | pbrook | /* Unpredictable in user mode. */
|
7325 | 9ee6e8bb | pbrook | goto illegal_op;
|
7326 | 9ee6e8bb | pbrook | case 6: /* mrs cpsr. */ |
7327 | 8984bd2e | pbrook | tmp = new_tmp(); |
7328 | 9ee6e8bb | pbrook | if (IS_M(env)) {
|
7329 | 8984bd2e | pbrook | addr = tcg_const_i32(insn & 0xff);
|
7330 | 8984bd2e | pbrook | gen_helper_v7m_mrs(tmp, cpu_env, addr); |
7331 | 9ee6e8bb | pbrook | } else {
|
7332 | 8984bd2e | pbrook | gen_helper_cpsr_read(tmp); |
7333 | 9ee6e8bb | pbrook | } |
7334 | 8984bd2e | pbrook | store_reg(s, rd, tmp); |
7335 | 9ee6e8bb | pbrook | break;
|
7336 | 9ee6e8bb | pbrook | case 7: /* mrs spsr. */ |
7337 | 9ee6e8bb | pbrook | /* Not accessible in user mode. */
|
7338 | 9ee6e8bb | pbrook | if (IS_USER(s) || IS_M(env))
|
7339 | 9ee6e8bb | pbrook | goto illegal_op;
|
7340 | d9ba4830 | pbrook | tmp = load_cpu_field(spsr); |
7341 | d9ba4830 | pbrook | store_reg(s, rd, tmp); |
7342 | 9ee6e8bb | pbrook | break;
|
7343 | 2c0262af | bellard | } |
7344 | 2c0262af | bellard | } |
7345 | 9ee6e8bb | pbrook | } else {
|
7346 | 9ee6e8bb | pbrook | /* Conditional branch. */
|
7347 | 9ee6e8bb | pbrook | op = (insn >> 22) & 0xf; |
7348 | 9ee6e8bb | pbrook | /* Generate a conditional jump to next instruction. */
|
7349 | 9ee6e8bb | pbrook | s->condlabel = gen_new_label(); |
7350 | d9ba4830 | pbrook | gen_test_cc(op ^ 1, s->condlabel);
|
7351 | 9ee6e8bb | pbrook | s->condjmp = 1;
|
7352 | 9ee6e8bb | pbrook | |
7353 | 9ee6e8bb | pbrook | /* offset[11:1] = insn[10:0] */
|
7354 | 9ee6e8bb | pbrook | offset = (insn & 0x7ff) << 1; |
7355 | 9ee6e8bb | pbrook | /* offset[17:12] = insn[21:16]. */
|
7356 | 9ee6e8bb | pbrook | offset |= (insn & 0x003f0000) >> 4; |
7357 | 9ee6e8bb | pbrook | /* offset[31:20] = insn[26]. */
|
7358 | 9ee6e8bb | pbrook | offset |= ((int32_t)((insn << 5) & 0x80000000)) >> 11; |
7359 | 9ee6e8bb | pbrook | /* offset[18] = insn[13]. */
|
7360 | 9ee6e8bb | pbrook | offset |= (insn & (1 << 13)) << 5; |
7361 | 9ee6e8bb | pbrook | /* offset[19] = insn[11]. */
|
7362 | 9ee6e8bb | pbrook | offset |= (insn & (1 << 11)) << 8; |
7363 | 9ee6e8bb | pbrook | |
7364 | 9ee6e8bb | pbrook | /* jump to the offset */
|
7365 | b0109805 | pbrook | gen_jmp(s, s->pc + offset); |
7366 | 9ee6e8bb | pbrook | } |
7367 | 9ee6e8bb | pbrook | } else {
|
7368 | 9ee6e8bb | pbrook | /* Data processing immediate. */
|
7369 | 9ee6e8bb | pbrook | if (insn & (1 << 25)) { |
7370 | 9ee6e8bb | pbrook | if (insn & (1 << 24)) { |
7371 | 9ee6e8bb | pbrook | if (insn & (1 << 20)) |
7372 | 9ee6e8bb | pbrook | goto illegal_op;
|
7373 | 9ee6e8bb | pbrook | /* Bitfield/Saturate. */
|
7374 | 9ee6e8bb | pbrook | op = (insn >> 21) & 7; |
7375 | 9ee6e8bb | pbrook | imm = insn & 0x1f;
|
7376 | 9ee6e8bb | pbrook | shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c); |
7377 | 6ddbc6e4 | pbrook | if (rn == 15) { |
7378 | 6ddbc6e4 | pbrook | tmp = new_tmp(); |
7379 | 6ddbc6e4 | pbrook | tcg_gen_movi_i32(tmp, 0);
|
7380 | 6ddbc6e4 | pbrook | } else {
|
7381 | 6ddbc6e4 | pbrook | tmp = load_reg(s, rn); |
7382 | 6ddbc6e4 | pbrook | } |
7383 | 9ee6e8bb | pbrook | switch (op) {
|
7384 | 9ee6e8bb | pbrook | case 2: /* Signed bitfield extract. */ |
7385 | 9ee6e8bb | pbrook | imm++; |
7386 | 9ee6e8bb | pbrook | if (shift + imm > 32) |
7387 | 9ee6e8bb | pbrook | goto illegal_op;
|
7388 | 9ee6e8bb | pbrook | if (imm < 32) |
7389 | 6ddbc6e4 | pbrook | gen_sbfx(tmp, shift, imm); |
7390 | 9ee6e8bb | pbrook | break;
|
7391 | 9ee6e8bb | pbrook | case 6: /* Unsigned bitfield extract. */ |
7392 | 9ee6e8bb | pbrook | imm++; |
7393 | 9ee6e8bb | pbrook | if (shift + imm > 32) |
7394 | 9ee6e8bb | pbrook | goto illegal_op;
|
7395 | 9ee6e8bb | pbrook | if (imm < 32) |
7396 | 6ddbc6e4 | pbrook | gen_ubfx(tmp, shift, (1u << imm) - 1); |
7397 | 9ee6e8bb | pbrook | break;
|
7398 | 9ee6e8bb | pbrook | case 3: /* Bitfield insert/clear. */ |
7399 | 9ee6e8bb | pbrook | if (imm < shift)
|
7400 | 9ee6e8bb | pbrook | goto illegal_op;
|
7401 | 9ee6e8bb | pbrook | imm = imm + 1 - shift;
|
7402 | 9ee6e8bb | pbrook | if (imm != 32) { |
7403 | 6ddbc6e4 | pbrook | tmp2 = load_reg(s, rd); |
7404 | 8f8e3aa4 | pbrook | gen_bfi(tmp, tmp2, tmp, shift, (1u << imm) - 1); |
7405 | 6ddbc6e4 | pbrook | dead_tmp(tmp2); |
7406 | 9ee6e8bb | pbrook | } |
7407 | 9ee6e8bb | pbrook | break;
|
7408 | 9ee6e8bb | pbrook | case 7: |
7409 | 9ee6e8bb | pbrook | goto illegal_op;
|
7410 | 9ee6e8bb | pbrook | default: /* Saturate. */ |
7411 | 9ee6e8bb | pbrook | if (shift) {
|
7412 | 9ee6e8bb | pbrook | if (op & 1) |
7413 | 6ddbc6e4 | pbrook | tcg_gen_sari_i32(tmp, tmp, shift); |
7414 | 9ee6e8bb | pbrook | else
|
7415 | 6ddbc6e4 | pbrook | tcg_gen_shli_i32(tmp, tmp, shift); |
7416 | 9ee6e8bb | pbrook | } |
7417 | 6ddbc6e4 | pbrook | tmp2 = tcg_const_i32(imm); |
7418 | 9ee6e8bb | pbrook | if (op & 4) { |
7419 | 9ee6e8bb | pbrook | /* Unsigned. */
|
7420 | 9ee6e8bb | pbrook | if ((op & 1) && shift == 0) |
7421 | 6ddbc6e4 | pbrook | gen_helper_usat16(tmp, tmp, tmp2); |
7422 | 9ee6e8bb | pbrook | else
|
7423 | 6ddbc6e4 | pbrook | gen_helper_usat(tmp, tmp, tmp2); |
7424 | 2c0262af | bellard | } else {
|
7425 | 9ee6e8bb | pbrook | /* Signed. */
|
7426 | 9ee6e8bb | pbrook | if ((op & 1) && shift == 0) |
7427 | 6ddbc6e4 | pbrook | gen_helper_ssat16(tmp, tmp, tmp2); |
7428 | 9ee6e8bb | pbrook | else
|
7429 | 6ddbc6e4 | pbrook | gen_helper_ssat(tmp, tmp, tmp2); |
7430 | 2c0262af | bellard | } |
7431 | 9ee6e8bb | pbrook | break;
|
7432 | 2c0262af | bellard | } |
7433 | 6ddbc6e4 | pbrook | store_reg(s, rd, tmp); |
7434 | 9ee6e8bb | pbrook | } else {
|
7435 | 9ee6e8bb | pbrook | imm = ((insn & 0x04000000) >> 15) |
7436 | 9ee6e8bb | pbrook | | ((insn & 0x7000) >> 4) | (insn & 0xff); |
7437 | 9ee6e8bb | pbrook | if (insn & (1 << 22)) { |
7438 | 9ee6e8bb | pbrook | /* 16-bit immediate. */
|
7439 | 9ee6e8bb | pbrook | imm |= (insn >> 4) & 0xf000; |
7440 | 9ee6e8bb | pbrook | if (insn & (1 << 23)) { |
7441 | 9ee6e8bb | pbrook | /* movt */
|
7442 | 5e3f878a | pbrook | tmp = load_reg(s, rd); |
7443 | 5e3f878a | pbrook | tcg_gen_andi_i32(tmp, tmp, 0xffff);
|
7444 | 5e3f878a | pbrook | tcg_gen_ori_i32(tmp, tmp, imm << 16);
|
7445 | 2c0262af | bellard | } else {
|
7446 | 9ee6e8bb | pbrook | /* movw */
|
7447 | 5e3f878a | pbrook | tmp = new_tmp(); |
7448 | 5e3f878a | pbrook | tcg_gen_movi_i32(tmp, imm); |
7449 | 2c0262af | bellard | } |
7450 | 2c0262af | bellard | } else {
|
7451 | 9ee6e8bb | pbrook | /* Add/sub 12-bit immediate. */
|
7452 | 9ee6e8bb | pbrook | if (rn == 15) { |
7453 | b0109805 | pbrook | offset = s->pc & ~(uint32_t)3;
|
7454 | 9ee6e8bb | pbrook | if (insn & (1 << 23)) |
7455 | b0109805 | pbrook | offset -= imm; |
7456 | 9ee6e8bb | pbrook | else
|
7457 | b0109805 | pbrook | offset += imm; |
7458 | 5e3f878a | pbrook | tmp = new_tmp(); |
7459 | 5e3f878a | pbrook | tcg_gen_movi_i32(tmp, offset); |
7460 | 2c0262af | bellard | } else {
|
7461 | 5e3f878a | pbrook | tmp = load_reg(s, rn); |
7462 | 9ee6e8bb | pbrook | if (insn & (1 << 23)) |
7463 | 5e3f878a | pbrook | tcg_gen_subi_i32(tmp, tmp, imm); |
7464 | 9ee6e8bb | pbrook | else
|
7465 | 5e3f878a | pbrook | tcg_gen_addi_i32(tmp, tmp, imm); |
7466 | 2c0262af | bellard | } |
7467 | 9ee6e8bb | pbrook | } |
7468 | 5e3f878a | pbrook | store_reg(s, rd, tmp); |
7469 | 191abaa2 | pbrook | } |
7470 | 9ee6e8bb | pbrook | } else {
|
7471 | 9ee6e8bb | pbrook | int shifter_out = 0; |
7472 | 9ee6e8bb | pbrook | /* modified 12-bit immediate. */
|
7473 | 9ee6e8bb | pbrook | shift = ((insn & 0x04000000) >> 23) | ((insn & 0x7000) >> 12); |
7474 | 9ee6e8bb | pbrook | imm = (insn & 0xff);
|
7475 | 9ee6e8bb | pbrook | switch (shift) {
|
7476 | 9ee6e8bb | pbrook | case 0: /* XY */ |
7477 | 9ee6e8bb | pbrook | /* Nothing to do. */
|
7478 | 9ee6e8bb | pbrook | break;
|
7479 | 9ee6e8bb | pbrook | case 1: /* 00XY00XY */ |
7480 | 9ee6e8bb | pbrook | imm |= imm << 16;
|
7481 | 9ee6e8bb | pbrook | break;
|
7482 | 9ee6e8bb | pbrook | case 2: /* XY00XY00 */ |
7483 | 9ee6e8bb | pbrook | imm |= imm << 16;
|
7484 | 9ee6e8bb | pbrook | imm <<= 8;
|
7485 | 9ee6e8bb | pbrook | break;
|
7486 | 9ee6e8bb | pbrook | case 3: /* XYXYXYXY */ |
7487 | 9ee6e8bb | pbrook | imm |= imm << 16;
|
7488 | 9ee6e8bb | pbrook | imm |= imm << 8;
|
7489 | 9ee6e8bb | pbrook | break;
|
7490 | 9ee6e8bb | pbrook | default: /* Rotated constant. */ |
7491 | 9ee6e8bb | pbrook | shift = (shift << 1) | (imm >> 7); |
7492 | 9ee6e8bb | pbrook | imm |= 0x80;
|
7493 | 9ee6e8bb | pbrook | imm = imm << (32 - shift);
|
7494 | 9ee6e8bb | pbrook | shifter_out = 1;
|
7495 | 9ee6e8bb | pbrook | break;
|
7496 | b5ff1b31 | bellard | } |
7497 | 9ee6e8bb | pbrook | gen_op_movl_T1_im(imm); |
7498 | 9ee6e8bb | pbrook | rn = (insn >> 16) & 0xf; |
7499 | 9ee6e8bb | pbrook | if (rn == 15) |
7500 | 9ee6e8bb | pbrook | gen_op_movl_T0_im(0);
|
7501 | 9ee6e8bb | pbrook | else
|
7502 | 9ee6e8bb | pbrook | gen_movl_T0_reg(s, rn); |
7503 | 9ee6e8bb | pbrook | op = (insn >> 21) & 0xf; |
7504 | 9ee6e8bb | pbrook | if (gen_thumb2_data_op(s, op, (insn & (1 << 20)) != 0, |
7505 | 9ee6e8bb | pbrook | shifter_out)) |
7506 | 9ee6e8bb | pbrook | goto illegal_op;
|
7507 | 9ee6e8bb | pbrook | rd = (insn >> 8) & 0xf; |
7508 | 9ee6e8bb | pbrook | if (rd != 15) { |
7509 | 9ee6e8bb | pbrook | gen_movl_reg_T0(s, rd); |
7510 | 2c0262af | bellard | } |
7511 | 2c0262af | bellard | } |
7512 | 9ee6e8bb | pbrook | } |
7513 | 9ee6e8bb | pbrook | break;
|
7514 | 9ee6e8bb | pbrook | case 12: /* Load/store single data item. */ |
7515 | 9ee6e8bb | pbrook | { |
7516 | 9ee6e8bb | pbrook | int postinc = 0; |
7517 | 9ee6e8bb | pbrook | int writeback = 0; |
7518 | b0109805 | pbrook | int user;
|
7519 | 9ee6e8bb | pbrook | if ((insn & 0x01100000) == 0x01000000) { |
7520 | 9ee6e8bb | pbrook | if (disas_neon_ls_insn(env, s, insn))
|
7521 | c1713132 | balrog | goto illegal_op;
|
7522 | 9ee6e8bb | pbrook | break;
|
7523 | 9ee6e8bb | pbrook | } |
7524 | b0109805 | pbrook | user = IS_USER(s); |
7525 | 9ee6e8bb | pbrook | if (rn == 15) { |
7526 | b0109805 | pbrook | addr = new_tmp(); |
7527 | 9ee6e8bb | pbrook | /* PC relative. */
|
7528 | 9ee6e8bb | pbrook | /* s->pc has already been incremented by 4. */
|
7529 | 9ee6e8bb | pbrook | imm = s->pc & 0xfffffffc;
|
7530 | 9ee6e8bb | pbrook | if (insn & (1 << 23)) |
7531 | 9ee6e8bb | pbrook | imm += insn & 0xfff;
|
7532 | 9ee6e8bb | pbrook | else
|
7533 | 9ee6e8bb | pbrook | imm -= insn & 0xfff;
|
7534 | b0109805 | pbrook | tcg_gen_movi_i32(addr, imm); |
7535 | 9ee6e8bb | pbrook | } else {
|
7536 | b0109805 | pbrook | addr = load_reg(s, rn); |
7537 | 9ee6e8bb | pbrook | if (insn & (1 << 23)) { |
7538 | 9ee6e8bb | pbrook | /* Positive offset. */
|
7539 | 9ee6e8bb | pbrook | imm = insn & 0xfff;
|
7540 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, imm); |
7541 | 9ee6e8bb | pbrook | } else {
|
7542 | 9ee6e8bb | pbrook | op = (insn >> 8) & 7; |
7543 | 9ee6e8bb | pbrook | imm = insn & 0xff;
|
7544 | 9ee6e8bb | pbrook | switch (op) {
|
7545 | 9ee6e8bb | pbrook | case 0: case 8: /* Shifted Register. */ |
7546 | 9ee6e8bb | pbrook | shift = (insn >> 4) & 0xf; |
7547 | 9ee6e8bb | pbrook | if (shift > 3) |
7548 | 18c9b560 | balrog | goto illegal_op;
|
7549 | b26eefb6 | pbrook | tmp = load_reg(s, rm); |
7550 | 9ee6e8bb | pbrook | if (shift)
|
7551 | b26eefb6 | pbrook | tcg_gen_shli_i32(tmp, tmp, shift); |
7552 | b0109805 | pbrook | tcg_gen_add_i32(addr, addr, tmp); |
7553 | b26eefb6 | pbrook | dead_tmp(tmp); |
7554 | 9ee6e8bb | pbrook | break;
|
7555 | 9ee6e8bb | pbrook | case 4: /* Negative offset. */ |
7556 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, -imm); |
7557 | 9ee6e8bb | pbrook | break;
|
7558 | 9ee6e8bb | pbrook | case 6: /* User privilege. */ |
7559 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, imm); |
7560 | b0109805 | pbrook | user = 1;
|
7561 | 9ee6e8bb | pbrook | break;
|
7562 | 9ee6e8bb | pbrook | case 1: /* Post-decrement. */ |
7563 | 9ee6e8bb | pbrook | imm = -imm; |
7564 | 9ee6e8bb | pbrook | /* Fall through. */
|
7565 | 9ee6e8bb | pbrook | case 3: /* Post-increment. */ |
7566 | 9ee6e8bb | pbrook | postinc = 1;
|
7567 | 9ee6e8bb | pbrook | writeback = 1;
|
7568 | 9ee6e8bb | pbrook | break;
|
7569 | 9ee6e8bb | pbrook | case 5: /* Pre-decrement. */ |
7570 | 9ee6e8bb | pbrook | imm = -imm; |
7571 | 9ee6e8bb | pbrook | /* Fall through. */
|
7572 | 9ee6e8bb | pbrook | case 7: /* Pre-increment. */ |
7573 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, imm); |
7574 | 9ee6e8bb | pbrook | writeback = 1;
|
7575 | 9ee6e8bb | pbrook | break;
|
7576 | 9ee6e8bb | pbrook | default:
|
7577 | b7bcbe95 | bellard | goto illegal_op;
|
7578 | 9ee6e8bb | pbrook | } |
7579 | 9ee6e8bb | pbrook | } |
7580 | 9ee6e8bb | pbrook | } |
7581 | 9ee6e8bb | pbrook | op = ((insn >> 21) & 3) | ((insn >> 22) & 4); |
7582 | 9ee6e8bb | pbrook | if (insn & (1 << 20)) { |
7583 | 9ee6e8bb | pbrook | /* Load. */
|
7584 | 9ee6e8bb | pbrook | if (rs == 15 && op != 2) { |
7585 | 9ee6e8bb | pbrook | if (op & 2) |
7586 | b5ff1b31 | bellard | goto illegal_op;
|
7587 | 9ee6e8bb | pbrook | /* Memory hint. Implemented as NOP. */
|
7588 | 9ee6e8bb | pbrook | } else {
|
7589 | 9ee6e8bb | pbrook | switch (op) {
|
7590 | b0109805 | pbrook | case 0: tmp = gen_ld8u(addr, user); break; |
7591 | b0109805 | pbrook | case 4: tmp = gen_ld8s(addr, user); break; |
7592 | b0109805 | pbrook | case 1: tmp = gen_ld16u(addr, user); break; |
7593 | b0109805 | pbrook | case 5: tmp = gen_ld16s(addr, user); break; |
7594 | b0109805 | pbrook | case 2: tmp = gen_ld32(addr, user); break; |
7595 | 9ee6e8bb | pbrook | default: goto illegal_op; |
7596 | 9ee6e8bb | pbrook | } |
7597 | 9ee6e8bb | pbrook | if (rs == 15) { |
7598 | b0109805 | pbrook | gen_bx(s, tmp); |
7599 | 9ee6e8bb | pbrook | } else {
|
7600 | b0109805 | pbrook | store_reg(s, rs, tmp); |
7601 | 9ee6e8bb | pbrook | } |
7602 | 9ee6e8bb | pbrook | } |
7603 | 9ee6e8bb | pbrook | } else {
|
7604 | 9ee6e8bb | pbrook | /* Store. */
|
7605 | 9ee6e8bb | pbrook | if (rs == 15) |
7606 | b7bcbe95 | bellard | goto illegal_op;
|
7607 | b0109805 | pbrook | tmp = load_reg(s, rs); |
7608 | 9ee6e8bb | pbrook | switch (op) {
|
7609 | b0109805 | pbrook | case 0: gen_st8(tmp, addr, user); break; |
7610 | b0109805 | pbrook | case 1: gen_st16(tmp, addr, user); break; |
7611 | b0109805 | pbrook | case 2: gen_st32(tmp, addr, user); break; |
7612 | 9ee6e8bb | pbrook | default: goto illegal_op; |
7613 | b7bcbe95 | bellard | } |
7614 | 2c0262af | bellard | } |
7615 | 9ee6e8bb | pbrook | if (postinc)
|
7616 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, imm); |
7617 | b0109805 | pbrook | if (writeback) {
|
7618 | b0109805 | pbrook | store_reg(s, rn, addr); |
7619 | b0109805 | pbrook | } else {
|
7620 | b0109805 | pbrook | dead_tmp(addr); |
7621 | b0109805 | pbrook | } |
7622 | 9ee6e8bb | pbrook | } |
7623 | 9ee6e8bb | pbrook | break;
|
7624 | 9ee6e8bb | pbrook | default:
|
7625 | 9ee6e8bb | pbrook | goto illegal_op;
|
7626 | 2c0262af | bellard | } |
7627 | 9ee6e8bb | pbrook | return 0; |
7628 | 9ee6e8bb | pbrook | illegal_op:
|
7629 | 9ee6e8bb | pbrook | return 1; |
7630 | 2c0262af | bellard | } |
7631 | 2c0262af | bellard | |
7632 | 9ee6e8bb | pbrook | static void disas_thumb_insn(CPUState *env, DisasContext *s) |
7633 | 99c475ab | bellard | { |
7634 | 99c475ab | bellard | uint32_t val, insn, op, rm, rn, rd, shift, cond; |
7635 | 99c475ab | bellard | int32_t offset; |
7636 | 99c475ab | bellard | int i;
|
7637 | b26eefb6 | pbrook | TCGv tmp; |
7638 | d9ba4830 | pbrook | TCGv tmp2; |
7639 | b0109805 | pbrook | TCGv addr; |
7640 | 99c475ab | bellard | |
7641 | 9ee6e8bb | pbrook | if (s->condexec_mask) {
|
7642 | 9ee6e8bb | pbrook | cond = s->condexec_cond; |
7643 | 9ee6e8bb | pbrook | s->condlabel = gen_new_label(); |
7644 | d9ba4830 | pbrook | gen_test_cc(cond ^ 1, s->condlabel);
|
7645 | 9ee6e8bb | pbrook | s->condjmp = 1;
|
7646 | 9ee6e8bb | pbrook | } |
7647 | 9ee6e8bb | pbrook | |
7648 | b5ff1b31 | bellard | insn = lduw_code(s->pc); |
7649 | 99c475ab | bellard | s->pc += 2;
|
7650 | b5ff1b31 | bellard | |
7651 | 99c475ab | bellard | switch (insn >> 12) { |
7652 | 99c475ab | bellard | case 0: case 1: |
7653 | 99c475ab | bellard | rd = insn & 7;
|
7654 | 99c475ab | bellard | op = (insn >> 11) & 3; |
7655 | 99c475ab | bellard | if (op == 3) { |
7656 | 99c475ab | bellard | /* add/subtract */
|
7657 | 99c475ab | bellard | rn = (insn >> 3) & 7; |
7658 | 99c475ab | bellard | gen_movl_T0_reg(s, rn); |
7659 | 99c475ab | bellard | if (insn & (1 << 10)) { |
7660 | 99c475ab | bellard | /* immediate */
|
7661 | 99c475ab | bellard | gen_op_movl_T1_im((insn >> 6) & 7); |
7662 | 99c475ab | bellard | } else {
|
7663 | 99c475ab | bellard | /* reg */
|
7664 | 99c475ab | bellard | rm = (insn >> 6) & 7; |
7665 | 99c475ab | bellard | gen_movl_T1_reg(s, rm); |
7666 | 99c475ab | bellard | } |
7667 | 9ee6e8bb | pbrook | if (insn & (1 << 9)) { |
7668 | 9ee6e8bb | pbrook | if (s->condexec_mask)
|
7669 | 9ee6e8bb | pbrook | gen_op_subl_T0_T1(); |
7670 | 9ee6e8bb | pbrook | else
|
7671 | 9ee6e8bb | pbrook | gen_op_subl_T0_T1_cc(); |
7672 | 9ee6e8bb | pbrook | } else {
|
7673 | 9ee6e8bb | pbrook | if (s->condexec_mask)
|
7674 | 9ee6e8bb | pbrook | gen_op_addl_T0_T1(); |
7675 | 9ee6e8bb | pbrook | else
|
7676 | 9ee6e8bb | pbrook | gen_op_addl_T0_T1_cc(); |
7677 | 9ee6e8bb | pbrook | } |
7678 | 99c475ab | bellard | gen_movl_reg_T0(s, rd); |
7679 | 99c475ab | bellard | } else {
|
7680 | 99c475ab | bellard | /* shift immediate */
|
7681 | 99c475ab | bellard | rm = (insn >> 3) & 7; |
7682 | 99c475ab | bellard | shift = (insn >> 6) & 0x1f; |
7683 | 9a119ff6 | pbrook | tmp = load_reg(s, rm); |
7684 | 9a119ff6 | pbrook | gen_arm_shift_im(tmp, op, shift, s->condexec_mask == 0);
|
7685 | 9a119ff6 | pbrook | if (!s->condexec_mask)
|
7686 | 9a119ff6 | pbrook | gen_logic_CC(tmp); |
7687 | 9a119ff6 | pbrook | store_reg(s, rd, tmp); |
7688 | 99c475ab | bellard | } |
7689 | 99c475ab | bellard | break;
|
7690 | 99c475ab | bellard | case 2: case 3: |
7691 | 99c475ab | bellard | /* arithmetic large immediate */
|
7692 | 99c475ab | bellard | op = (insn >> 11) & 3; |
7693 | 99c475ab | bellard | rd = (insn >> 8) & 0x7; |
7694 | 99c475ab | bellard | if (op == 0) { |
7695 | 99c475ab | bellard | gen_op_movl_T0_im(insn & 0xff);
|
7696 | 99c475ab | bellard | } else {
|
7697 | 99c475ab | bellard | gen_movl_T0_reg(s, rd); |
7698 | 99c475ab | bellard | gen_op_movl_T1_im(insn & 0xff);
|
7699 | 99c475ab | bellard | } |
7700 | 99c475ab | bellard | switch (op) {
|
7701 | 99c475ab | bellard | case 0: /* mov */ |
7702 | 9ee6e8bb | pbrook | if (!s->condexec_mask)
|
7703 | 9ee6e8bb | pbrook | gen_op_logic_T0_cc(); |
7704 | 99c475ab | bellard | break;
|
7705 | 99c475ab | bellard | case 1: /* cmp */ |
7706 | 99c475ab | bellard | gen_op_subl_T0_T1_cc(); |
7707 | 99c475ab | bellard | break;
|
7708 | 99c475ab | bellard | case 2: /* add */ |
7709 | 9ee6e8bb | pbrook | if (s->condexec_mask)
|
7710 | 9ee6e8bb | pbrook | gen_op_addl_T0_T1(); |
7711 | 9ee6e8bb | pbrook | else
|
7712 | 9ee6e8bb | pbrook | gen_op_addl_T0_T1_cc(); |
7713 | 99c475ab | bellard | break;
|
7714 | 99c475ab | bellard | case 3: /* sub */ |
7715 | 9ee6e8bb | pbrook | if (s->condexec_mask)
|
7716 | 9ee6e8bb | pbrook | gen_op_subl_T0_T1(); |
7717 | 9ee6e8bb | pbrook | else
|
7718 | 9ee6e8bb | pbrook | gen_op_subl_T0_T1_cc(); |
7719 | 99c475ab | bellard | break;
|
7720 | 99c475ab | bellard | } |
7721 | 99c475ab | bellard | if (op != 1) |
7722 | 99c475ab | bellard | gen_movl_reg_T0(s, rd); |
7723 | 99c475ab | bellard | break;
|
7724 | 99c475ab | bellard | case 4: |
7725 | 99c475ab | bellard | if (insn & (1 << 11)) { |
7726 | 99c475ab | bellard | rd = (insn >> 8) & 7; |
7727 | 5899f386 | bellard | /* load pc-relative. Bit 1 of PC is ignored. */
|
7728 | 5899f386 | bellard | val = s->pc + 2 + ((insn & 0xff) * 4); |
7729 | 5899f386 | bellard | val &= ~(uint32_t)2;
|
7730 | b0109805 | pbrook | addr = new_tmp(); |
7731 | b0109805 | pbrook | tcg_gen_movi_i32(addr, val); |
7732 | b0109805 | pbrook | tmp = gen_ld32(addr, IS_USER(s)); |
7733 | b0109805 | pbrook | dead_tmp(addr); |
7734 | b0109805 | pbrook | store_reg(s, rd, tmp); |
7735 | 99c475ab | bellard | break;
|
7736 | 99c475ab | bellard | } |
7737 | 99c475ab | bellard | if (insn & (1 << 10)) { |
7738 | 99c475ab | bellard | /* data processing extended or blx */
|
7739 | 99c475ab | bellard | rd = (insn & 7) | ((insn >> 4) & 8); |
7740 | 99c475ab | bellard | rm = (insn >> 3) & 0xf; |
7741 | 99c475ab | bellard | op = (insn >> 8) & 3; |
7742 | 99c475ab | bellard | switch (op) {
|
7743 | 99c475ab | bellard | case 0: /* add */ |
7744 | 99c475ab | bellard | gen_movl_T0_reg(s, rd); |
7745 | 99c475ab | bellard | gen_movl_T1_reg(s, rm); |
7746 | 99c475ab | bellard | gen_op_addl_T0_T1(); |
7747 | 99c475ab | bellard | gen_movl_reg_T0(s, rd); |
7748 | 99c475ab | bellard | break;
|
7749 | 99c475ab | bellard | case 1: /* cmp */ |
7750 | 99c475ab | bellard | gen_movl_T0_reg(s, rd); |
7751 | 99c475ab | bellard | gen_movl_T1_reg(s, rm); |
7752 | 99c475ab | bellard | gen_op_subl_T0_T1_cc(); |
7753 | 99c475ab | bellard | break;
|
7754 | 99c475ab | bellard | case 2: /* mov/cpy */ |
7755 | 99c475ab | bellard | gen_movl_T0_reg(s, rm); |
7756 | 99c475ab | bellard | gen_movl_reg_T0(s, rd); |
7757 | 99c475ab | bellard | break;
|
7758 | 99c475ab | bellard | case 3:/* branch [and link] exchange thumb register */ |
7759 | b0109805 | pbrook | tmp = load_reg(s, rm); |
7760 | 99c475ab | bellard | if (insn & (1 << 7)) { |
7761 | 99c475ab | bellard | val = (uint32_t)s->pc | 1;
|
7762 | b0109805 | pbrook | tmp2 = new_tmp(); |
7763 | b0109805 | pbrook | tcg_gen_movi_i32(tmp2, val); |
7764 | b0109805 | pbrook | store_reg(s, 14, tmp2);
|
7765 | 99c475ab | bellard | } |
7766 | d9ba4830 | pbrook | gen_bx(s, tmp); |
7767 | 99c475ab | bellard | break;
|
7768 | 99c475ab | bellard | } |
7769 | 99c475ab | bellard | break;
|
7770 | 99c475ab | bellard | } |
7771 | 99c475ab | bellard | |
7772 | 99c475ab | bellard | /* data processing register */
|
7773 | 99c475ab | bellard | rd = insn & 7;
|
7774 | 99c475ab | bellard | rm = (insn >> 3) & 7; |
7775 | 99c475ab | bellard | op = (insn >> 6) & 0xf; |
7776 | 99c475ab | bellard | if (op == 2 || op == 3 || op == 4 || op == 7) { |
7777 | 99c475ab | bellard | /* the shift/rotate ops want the operands backwards */
|
7778 | 99c475ab | bellard | val = rm; |
7779 | 99c475ab | bellard | rm = rd; |
7780 | 99c475ab | bellard | rd = val; |
7781 | 99c475ab | bellard | val = 1;
|
7782 | 99c475ab | bellard | } else {
|
7783 | 99c475ab | bellard | val = 0;
|
7784 | 99c475ab | bellard | } |
7785 | 99c475ab | bellard | |
7786 | 99c475ab | bellard | if (op == 9) /* neg */ |
7787 | 99c475ab | bellard | gen_op_movl_T0_im(0);
|
7788 | 99c475ab | bellard | else if (op != 0xf) /* mvn doesn't read its first operand */ |
7789 | 99c475ab | bellard | gen_movl_T0_reg(s, rd); |
7790 | 99c475ab | bellard | |
7791 | 99c475ab | bellard | gen_movl_T1_reg(s, rm); |
7792 | 5899f386 | bellard | switch (op) {
|
7793 | 99c475ab | bellard | case 0x0: /* and */ |
7794 | 99c475ab | bellard | gen_op_andl_T0_T1(); |
7795 | 9ee6e8bb | pbrook | if (!s->condexec_mask)
|
7796 | 9ee6e8bb | pbrook | gen_op_logic_T0_cc(); |
7797 | 99c475ab | bellard | break;
|
7798 | 99c475ab | bellard | case 0x1: /* eor */ |
7799 | 99c475ab | bellard | gen_op_xorl_T0_T1(); |
7800 | 9ee6e8bb | pbrook | if (!s->condexec_mask)
|
7801 | 9ee6e8bb | pbrook | gen_op_logic_T0_cc(); |
7802 | 99c475ab | bellard | break;
|
7803 | 99c475ab | bellard | case 0x2: /* lsl */ |
7804 | 9ee6e8bb | pbrook | if (s->condexec_mask) {
|
7805 | 8984bd2e | pbrook | gen_helper_shl(cpu_T[1], cpu_T[1], cpu_T[0]); |
7806 | 9ee6e8bb | pbrook | } else {
|
7807 | 8984bd2e | pbrook | gen_helper_shl_cc(cpu_T[1], cpu_T[1], cpu_T[0]); |
7808 | 9ee6e8bb | pbrook | gen_op_logic_T1_cc(); |
7809 | 9ee6e8bb | pbrook | } |
7810 | 99c475ab | bellard | break;
|
7811 | 99c475ab | bellard | case 0x3: /* lsr */ |
7812 | 9ee6e8bb | pbrook | if (s->condexec_mask) {
|
7813 | 8984bd2e | pbrook | gen_helper_shr(cpu_T[1], cpu_T[1], cpu_T[0]); |
7814 | 9ee6e8bb | pbrook | } else {
|
7815 | 8984bd2e | pbrook | gen_helper_shr_cc(cpu_T[1], cpu_T[1], cpu_T[0]); |
7816 | 9ee6e8bb | pbrook | gen_op_logic_T1_cc(); |
7817 | 9ee6e8bb | pbrook | } |
7818 | 99c475ab | bellard | break;
|
7819 | 99c475ab | bellard | case 0x4: /* asr */ |
7820 | 9ee6e8bb | pbrook | if (s->condexec_mask) {
|
7821 | 8984bd2e | pbrook | gen_helper_sar(cpu_T[1], cpu_T[1], cpu_T[0]); |
7822 | 9ee6e8bb | pbrook | } else {
|
7823 | 8984bd2e | pbrook | gen_helper_sar_cc(cpu_T[1], cpu_T[1], cpu_T[0]); |
7824 | 9ee6e8bb | pbrook | gen_op_logic_T1_cc(); |
7825 | 9ee6e8bb | pbrook | } |
7826 | 99c475ab | bellard | break;
|
7827 | 99c475ab | bellard | case 0x5: /* adc */ |
7828 | 9ee6e8bb | pbrook | if (s->condexec_mask)
|
7829 | b26eefb6 | pbrook | gen_adc_T0_T1(); |
7830 | 9ee6e8bb | pbrook | else
|
7831 | 9ee6e8bb | pbrook | gen_op_adcl_T0_T1_cc(); |
7832 | 99c475ab | bellard | break;
|
7833 | 99c475ab | bellard | case 0x6: /* sbc */ |
7834 | 9ee6e8bb | pbrook | if (s->condexec_mask)
|
7835 | 3670669c | pbrook | gen_sbc_T0_T1(); |
7836 | 9ee6e8bb | pbrook | else
|
7837 | 9ee6e8bb | pbrook | gen_op_sbcl_T0_T1_cc(); |
7838 | 99c475ab | bellard | break;
|
7839 | 99c475ab | bellard | case 0x7: /* ror */ |
7840 | 9ee6e8bb | pbrook | if (s->condexec_mask) {
|
7841 | 8984bd2e | pbrook | gen_helper_ror(cpu_T[1], cpu_T[1], cpu_T[0]); |
7842 | 9ee6e8bb | pbrook | } else {
|
7843 | 8984bd2e | pbrook | gen_helper_ror_cc(cpu_T[1], cpu_T[1], cpu_T[0]); |
7844 | 9ee6e8bb | pbrook | gen_op_logic_T1_cc(); |
7845 | 9ee6e8bb | pbrook | } |
7846 | 99c475ab | bellard | break;
|
7847 | 99c475ab | bellard | case 0x8: /* tst */ |
7848 | 99c475ab | bellard | gen_op_andl_T0_T1(); |
7849 | 99c475ab | bellard | gen_op_logic_T0_cc(); |
7850 | 99c475ab | bellard | rd = 16;
|
7851 | 5899f386 | bellard | break;
|
7852 | 99c475ab | bellard | case 0x9: /* neg */ |
7853 | 9ee6e8bb | pbrook | if (s->condexec_mask)
|
7854 | 9ee6e8bb | pbrook | gen_op_subl_T0_T1(); |
7855 | 9ee6e8bb | pbrook | else
|
7856 | 9ee6e8bb | pbrook | gen_op_subl_T0_T1_cc(); |
7857 | 99c475ab | bellard | break;
|
7858 | 99c475ab | bellard | case 0xa: /* cmp */ |
7859 | 99c475ab | bellard | gen_op_subl_T0_T1_cc(); |
7860 | 99c475ab | bellard | rd = 16;
|
7861 | 99c475ab | bellard | break;
|
7862 | 99c475ab | bellard | case 0xb: /* cmn */ |
7863 | 99c475ab | bellard | gen_op_addl_T0_T1_cc(); |
7864 | 99c475ab | bellard | rd = 16;
|
7865 | 99c475ab | bellard | break;
|
7866 | 99c475ab | bellard | case 0xc: /* orr */ |
7867 | 99c475ab | bellard | gen_op_orl_T0_T1(); |
7868 | 9ee6e8bb | pbrook | if (!s->condexec_mask)
|
7869 | 9ee6e8bb | pbrook | gen_op_logic_T0_cc(); |
7870 | 99c475ab | bellard | break;
|
7871 | 99c475ab | bellard | case 0xd: /* mul */ |
7872 | 99c475ab | bellard | gen_op_mull_T0_T1(); |
7873 | 9ee6e8bb | pbrook | if (!s->condexec_mask)
|
7874 | 9ee6e8bb | pbrook | gen_op_logic_T0_cc(); |
7875 | 99c475ab | bellard | break;
|
7876 | 99c475ab | bellard | case 0xe: /* bic */ |
7877 | 99c475ab | bellard | gen_op_bicl_T0_T1(); |
7878 | 9ee6e8bb | pbrook | if (!s->condexec_mask)
|
7879 | 9ee6e8bb | pbrook | gen_op_logic_T0_cc(); |
7880 | 99c475ab | bellard | break;
|
7881 | 99c475ab | bellard | case 0xf: /* mvn */ |
7882 | 99c475ab | bellard | gen_op_notl_T1(); |
7883 | 9ee6e8bb | pbrook | if (!s->condexec_mask)
|
7884 | 9ee6e8bb | pbrook | gen_op_logic_T1_cc(); |
7885 | 99c475ab | bellard | val = 1;
|
7886 | 5899f386 | bellard | rm = rd; |
7887 | 99c475ab | bellard | break;
|
7888 | 99c475ab | bellard | } |
7889 | 99c475ab | bellard | if (rd != 16) { |
7890 | 99c475ab | bellard | if (val)
|
7891 | 5899f386 | bellard | gen_movl_reg_T1(s, rm); |
7892 | 99c475ab | bellard | else
|
7893 | 99c475ab | bellard | gen_movl_reg_T0(s, rd); |
7894 | 99c475ab | bellard | } |
7895 | 99c475ab | bellard | break;
|
7896 | 99c475ab | bellard | |
7897 | 99c475ab | bellard | case 5: |
7898 | 99c475ab | bellard | /* load/store register offset. */
|
7899 | 99c475ab | bellard | rd = insn & 7;
|
7900 | 99c475ab | bellard | rn = (insn >> 3) & 7; |
7901 | 99c475ab | bellard | rm = (insn >> 6) & 7; |
7902 | 99c475ab | bellard | op = (insn >> 9) & 7; |
7903 | b0109805 | pbrook | addr = load_reg(s, rn); |
7904 | b26eefb6 | pbrook | tmp = load_reg(s, rm); |
7905 | b0109805 | pbrook | tcg_gen_add_i32(addr, addr, tmp); |
7906 | b26eefb6 | pbrook | dead_tmp(tmp); |
7907 | 99c475ab | bellard | |
7908 | 99c475ab | bellard | if (op < 3) /* store */ |
7909 | b0109805 | pbrook | tmp = load_reg(s, rd); |
7910 | 99c475ab | bellard | |
7911 | 99c475ab | bellard | switch (op) {
|
7912 | 99c475ab | bellard | case 0: /* str */ |
7913 | b0109805 | pbrook | gen_st32(tmp, addr, IS_USER(s)); |
7914 | 99c475ab | bellard | break;
|
7915 | 99c475ab | bellard | case 1: /* strh */ |
7916 | b0109805 | pbrook | gen_st16(tmp, addr, IS_USER(s)); |
7917 | 99c475ab | bellard | break;
|
7918 | 99c475ab | bellard | case 2: /* strb */ |
7919 | b0109805 | pbrook | gen_st8(tmp, addr, IS_USER(s)); |
7920 | 99c475ab | bellard | break;
|
7921 | 99c475ab | bellard | case 3: /* ldrsb */ |
7922 | b0109805 | pbrook | tmp = gen_ld8s(addr, IS_USER(s)); |
7923 | 99c475ab | bellard | break;
|
7924 | 99c475ab | bellard | case 4: /* ldr */ |
7925 | b0109805 | pbrook | tmp = gen_ld32(addr, IS_USER(s)); |
7926 | 99c475ab | bellard | break;
|
7927 | 99c475ab | bellard | case 5: /* ldrh */ |
7928 | b0109805 | pbrook | tmp = gen_ld16u(addr, IS_USER(s)); |
7929 | 99c475ab | bellard | break;
|
7930 | 99c475ab | bellard | case 6: /* ldrb */ |
7931 | b0109805 | pbrook | tmp = gen_ld8u(addr, IS_USER(s)); |
7932 | 99c475ab | bellard | break;
|
7933 | 99c475ab | bellard | case 7: /* ldrsh */ |
7934 | b0109805 | pbrook | tmp = gen_ld16s(addr, IS_USER(s)); |
7935 | 99c475ab | bellard | break;
|
7936 | 99c475ab | bellard | } |
7937 | 99c475ab | bellard | if (op >= 3) /* load */ |
7938 | b0109805 | pbrook | store_reg(s, rd, tmp); |
7939 | b0109805 | pbrook | dead_tmp(addr); |
7940 | 99c475ab | bellard | break;
|
7941 | 99c475ab | bellard | |
7942 | 99c475ab | bellard | case 6: |
7943 | 99c475ab | bellard | /* load/store word immediate offset */
|
7944 | 99c475ab | bellard | rd = insn & 7;
|
7945 | 99c475ab | bellard | rn = (insn >> 3) & 7; |
7946 | b0109805 | pbrook | addr = load_reg(s, rn); |
7947 | 99c475ab | bellard | val = (insn >> 4) & 0x7c; |
7948 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, val); |
7949 | 99c475ab | bellard | |
7950 | 99c475ab | bellard | if (insn & (1 << 11)) { |
7951 | 99c475ab | bellard | /* load */
|
7952 | b0109805 | pbrook | tmp = gen_ld32(addr, IS_USER(s)); |
7953 | b0109805 | pbrook | store_reg(s, rd, tmp); |
7954 | 99c475ab | bellard | } else {
|
7955 | 99c475ab | bellard | /* store */
|
7956 | b0109805 | pbrook | tmp = load_reg(s, rd); |
7957 | b0109805 | pbrook | gen_st32(tmp, addr, IS_USER(s)); |
7958 | 99c475ab | bellard | } |
7959 | b0109805 | pbrook | dead_tmp(addr); |
7960 | 99c475ab | bellard | break;
|
7961 | 99c475ab | bellard | |
7962 | 99c475ab | bellard | case 7: |
7963 | 99c475ab | bellard | /* load/store byte immediate offset */
|
7964 | 99c475ab | bellard | rd = insn & 7;
|
7965 | 99c475ab | bellard | rn = (insn >> 3) & 7; |
7966 | b0109805 | pbrook | addr = load_reg(s, rn); |
7967 | 99c475ab | bellard | val = (insn >> 6) & 0x1f; |
7968 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, val); |
7969 | 99c475ab | bellard | |
7970 | 99c475ab | bellard | if (insn & (1 << 11)) { |
7971 | 99c475ab | bellard | /* load */
|
7972 | b0109805 | pbrook | tmp = gen_ld8u(addr, IS_USER(s)); |
7973 | b0109805 | pbrook | store_reg(s, rd, tmp); |
7974 | 99c475ab | bellard | } else {
|
7975 | 99c475ab | bellard | /* store */
|
7976 | b0109805 | pbrook | tmp = load_reg(s, rd); |
7977 | b0109805 | pbrook | gen_st8(tmp, addr, IS_USER(s)); |
7978 | 99c475ab | bellard | } |
7979 | b0109805 | pbrook | dead_tmp(addr); |
7980 | 99c475ab | bellard | break;
|
7981 | 99c475ab | bellard | |
7982 | 99c475ab | bellard | case 8: |
7983 | 99c475ab | bellard | /* load/store halfword immediate offset */
|
7984 | 99c475ab | bellard | rd = insn & 7;
|
7985 | 99c475ab | bellard | rn = (insn >> 3) & 7; |
7986 | b0109805 | pbrook | addr = load_reg(s, rn); |
7987 | 99c475ab | bellard | val = (insn >> 5) & 0x3e; |
7988 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, val); |
7989 | 99c475ab | bellard | |
7990 | 99c475ab | bellard | if (insn & (1 << 11)) { |
7991 | 99c475ab | bellard | /* load */
|
7992 | b0109805 | pbrook | tmp = gen_ld16u(addr, IS_USER(s)); |
7993 | b0109805 | pbrook | store_reg(s, rd, tmp); |
7994 | 99c475ab | bellard | } else {
|
7995 | 99c475ab | bellard | /* store */
|
7996 | b0109805 | pbrook | tmp = load_reg(s, rd); |
7997 | b0109805 | pbrook | gen_st16(tmp, addr, IS_USER(s)); |
7998 | 99c475ab | bellard | } |
7999 | b0109805 | pbrook | dead_tmp(addr); |
8000 | 99c475ab | bellard | break;
|
8001 | 99c475ab | bellard | |
8002 | 99c475ab | bellard | case 9: |
8003 | 99c475ab | bellard | /* load/store from stack */
|
8004 | 99c475ab | bellard | rd = (insn >> 8) & 7; |
8005 | b0109805 | pbrook | addr = load_reg(s, 13);
|
8006 | 99c475ab | bellard | val = (insn & 0xff) * 4; |
8007 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, val); |
8008 | 99c475ab | bellard | |
8009 | 99c475ab | bellard | if (insn & (1 << 11)) { |
8010 | 99c475ab | bellard | /* load */
|
8011 | b0109805 | pbrook | tmp = gen_ld32(addr, IS_USER(s)); |
8012 | b0109805 | pbrook | store_reg(s, rd, tmp); |
8013 | 99c475ab | bellard | } else {
|
8014 | 99c475ab | bellard | /* store */
|
8015 | b0109805 | pbrook | tmp = load_reg(s, rd); |
8016 | b0109805 | pbrook | gen_st32(tmp, addr, IS_USER(s)); |
8017 | 99c475ab | bellard | } |
8018 | b0109805 | pbrook | dead_tmp(addr); |
8019 | 99c475ab | bellard | break;
|
8020 | 99c475ab | bellard | |
8021 | 99c475ab | bellard | case 10: |
8022 | 99c475ab | bellard | /* add to high reg */
|
8023 | 99c475ab | bellard | rd = (insn >> 8) & 7; |
8024 | 5899f386 | bellard | if (insn & (1 << 11)) { |
8025 | 5899f386 | bellard | /* SP */
|
8026 | 5e3f878a | pbrook | tmp = load_reg(s, 13);
|
8027 | 5899f386 | bellard | } else {
|
8028 | 5899f386 | bellard | /* PC. bit 1 is ignored. */
|
8029 | 5e3f878a | pbrook | tmp = new_tmp(); |
8030 | 5e3f878a | pbrook | tcg_gen_movi_i32(tmp, (s->pc + 2) & ~(uint32_t)2); |
8031 | 5899f386 | bellard | } |
8032 | 99c475ab | bellard | val = (insn & 0xff) * 4; |
8033 | 5e3f878a | pbrook | tcg_gen_addi_i32(tmp, tmp, val); |
8034 | 5e3f878a | pbrook | store_reg(s, rd, tmp); |
8035 | 99c475ab | bellard | break;
|
8036 | 99c475ab | bellard | |
8037 | 99c475ab | bellard | case 11: |
8038 | 99c475ab | bellard | /* misc */
|
8039 | 99c475ab | bellard | op = (insn >> 8) & 0xf; |
8040 | 99c475ab | bellard | switch (op) {
|
8041 | 99c475ab | bellard | case 0: |
8042 | 99c475ab | bellard | /* adjust stack pointer */
|
8043 | b26eefb6 | pbrook | tmp = load_reg(s, 13);
|
8044 | 99c475ab | bellard | val = (insn & 0x7f) * 4; |
8045 | 99c475ab | bellard | if (insn & (1 << 7)) |
8046 | 99c475ab | bellard | val = -(int32_t)val; |
8047 | b26eefb6 | pbrook | tcg_gen_addi_i32(tmp, tmp, val); |
8048 | b26eefb6 | pbrook | store_reg(s, 13, tmp);
|
8049 | 99c475ab | bellard | break;
|
8050 | 99c475ab | bellard | |
8051 | 9ee6e8bb | pbrook | case 2: /* sign/zero extend. */ |
8052 | 9ee6e8bb | pbrook | ARCH(6);
|
8053 | 9ee6e8bb | pbrook | rd = insn & 7;
|
8054 | 9ee6e8bb | pbrook | rm = (insn >> 3) & 7; |
8055 | b0109805 | pbrook | tmp = load_reg(s, rm); |
8056 | 9ee6e8bb | pbrook | switch ((insn >> 6) & 3) { |
8057 | b0109805 | pbrook | case 0: gen_sxth(tmp); break; |
8058 | b0109805 | pbrook | case 1: gen_sxtb(tmp); break; |
8059 | b0109805 | pbrook | case 2: gen_uxth(tmp); break; |
8060 | b0109805 | pbrook | case 3: gen_uxtb(tmp); break; |
8061 | 9ee6e8bb | pbrook | } |
8062 | b0109805 | pbrook | store_reg(s, rd, tmp); |
8063 | 9ee6e8bb | pbrook | break;
|
8064 | 99c475ab | bellard | case 4: case 5: case 0xc: case 0xd: |
8065 | 99c475ab | bellard | /* push/pop */
|
8066 | b0109805 | pbrook | addr = load_reg(s, 13);
|
8067 | 5899f386 | bellard | if (insn & (1 << 8)) |
8068 | 5899f386 | bellard | offset = 4;
|
8069 | 99c475ab | bellard | else
|
8070 | 5899f386 | bellard | offset = 0;
|
8071 | 5899f386 | bellard | for (i = 0; i < 8; i++) { |
8072 | 5899f386 | bellard | if (insn & (1 << i)) |
8073 | 5899f386 | bellard | offset += 4;
|
8074 | 5899f386 | bellard | } |
8075 | 5899f386 | bellard | if ((insn & (1 << 11)) == 0) { |
8076 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, -offset); |
8077 | 5899f386 | bellard | } |
8078 | 99c475ab | bellard | for (i = 0; i < 8; i++) { |
8079 | 99c475ab | bellard | if (insn & (1 << i)) { |
8080 | 99c475ab | bellard | if (insn & (1 << 11)) { |
8081 | 99c475ab | bellard | /* pop */
|
8082 | b0109805 | pbrook | tmp = gen_ld32(addr, IS_USER(s)); |
8083 | b0109805 | pbrook | store_reg(s, i, tmp); |
8084 | 99c475ab | bellard | } else {
|
8085 | 99c475ab | bellard | /* push */
|
8086 | b0109805 | pbrook | tmp = load_reg(s, i); |
8087 | b0109805 | pbrook | gen_st32(tmp, addr, IS_USER(s)); |
8088 | 99c475ab | bellard | } |
8089 | 5899f386 | bellard | /* advance to the next address. */
|
8090 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, 4);
|
8091 | 99c475ab | bellard | } |
8092 | 99c475ab | bellard | } |
8093 | 99c475ab | bellard | if (insn & (1 << 8)) { |
8094 | 99c475ab | bellard | if (insn & (1 << 11)) { |
8095 | 99c475ab | bellard | /* pop pc */
|
8096 | b0109805 | pbrook | tmp = gen_ld32(addr, IS_USER(s)); |
8097 | 99c475ab | bellard | /* don't set the pc until the rest of the instruction
|
8098 | 99c475ab | bellard | has completed */
|
8099 | 99c475ab | bellard | } else {
|
8100 | 99c475ab | bellard | /* push lr */
|
8101 | b0109805 | pbrook | tmp = load_reg(s, 14);
|
8102 | b0109805 | pbrook | gen_st32(tmp, addr, IS_USER(s)); |
8103 | 99c475ab | bellard | } |
8104 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, 4);
|
8105 | 99c475ab | bellard | } |
8106 | 5899f386 | bellard | if ((insn & (1 << 11)) == 0) { |
8107 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, -offset); |
8108 | 5899f386 | bellard | } |
8109 | 99c475ab | bellard | /* write back the new stack pointer */
|
8110 | b0109805 | pbrook | store_reg(s, 13, addr);
|
8111 | 99c475ab | bellard | /* set the new PC value */
|
8112 | 99c475ab | bellard | if ((insn & 0x0900) == 0x0900) |
8113 | b0109805 | pbrook | gen_bx(s, tmp); |
8114 | 99c475ab | bellard | break;
|
8115 | 99c475ab | bellard | |
8116 | 9ee6e8bb | pbrook | case 1: case 3: case 9: case 11: /* czb */ |
8117 | 9ee6e8bb | pbrook | rm = insn & 7;
|
8118 | d9ba4830 | pbrook | tmp = load_reg(s, rm); |
8119 | d9ba4830 | pbrook | tmp2 = tcg_const_i32(0);
|
8120 | 9ee6e8bb | pbrook | s->condlabel = gen_new_label(); |
8121 | 9ee6e8bb | pbrook | s->condjmp = 1;
|
8122 | 9ee6e8bb | pbrook | if (insn & (1 << 11)) |
8123 | d9ba4830 | pbrook | tcg_gen_brcond_i32(TCG_COND_EQ, tmp, tmp2, s->condlabel); |
8124 | 9ee6e8bb | pbrook | else
|
8125 | d9ba4830 | pbrook | tcg_gen_brcond_i32(TCG_COND_NE, tmp, tmp2, s->condlabel); |
8126 | d9ba4830 | pbrook | dead_tmp(tmp); |
8127 | 9ee6e8bb | pbrook | offset = ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3; |
8128 | 9ee6e8bb | pbrook | val = (uint32_t)s->pc + 2;
|
8129 | 9ee6e8bb | pbrook | val += offset; |
8130 | 9ee6e8bb | pbrook | gen_jmp(s, val); |
8131 | 9ee6e8bb | pbrook | break;
|
8132 | 9ee6e8bb | pbrook | |
8133 | 9ee6e8bb | pbrook | case 15: /* IT, nop-hint. */ |
8134 | 9ee6e8bb | pbrook | if ((insn & 0xf) == 0) { |
8135 | 9ee6e8bb | pbrook | gen_nop_hint(s, (insn >> 4) & 0xf); |
8136 | 9ee6e8bb | pbrook | break;
|
8137 | 9ee6e8bb | pbrook | } |
8138 | 9ee6e8bb | pbrook | /* If Then. */
|
8139 | 9ee6e8bb | pbrook | s->condexec_cond = (insn >> 4) & 0xe; |
8140 | 9ee6e8bb | pbrook | s->condexec_mask = insn & 0x1f;
|
8141 | 9ee6e8bb | pbrook | /* No actual code generated for this insn, just setup state. */
|
8142 | 9ee6e8bb | pbrook | break;
|
8143 | 9ee6e8bb | pbrook | |
8144 | 06c949e6 | pbrook | case 0xe: /* bkpt */ |
8145 | 9ee6e8bb | pbrook | gen_set_condexec(s); |
8146 | 5e3f878a | pbrook | gen_set_pc_im(s->pc - 2);
|
8147 | d9ba4830 | pbrook | gen_exception(EXCP_BKPT); |
8148 | 06c949e6 | pbrook | s->is_jmp = DISAS_JUMP; |
8149 | 06c949e6 | pbrook | break;
|
8150 | 06c949e6 | pbrook | |
8151 | 9ee6e8bb | pbrook | case 0xa: /* rev */ |
8152 | 9ee6e8bb | pbrook | ARCH(6);
|
8153 | 9ee6e8bb | pbrook | rn = (insn >> 3) & 0x7; |
8154 | 9ee6e8bb | pbrook | rd = insn & 0x7;
|
8155 | b0109805 | pbrook | tmp = load_reg(s, rn); |
8156 | 9ee6e8bb | pbrook | switch ((insn >> 6) & 3) { |
8157 | b0109805 | pbrook | case 0: tcg_gen_bswap_i32(tmp, tmp); break; |
8158 | b0109805 | pbrook | case 1: gen_rev16(tmp); break; |
8159 | b0109805 | pbrook | case 3: gen_revsh(tmp); break; |
8160 | 9ee6e8bb | pbrook | default: goto illegal_op; |
8161 | 9ee6e8bb | pbrook | } |
8162 | b0109805 | pbrook | store_reg(s, rd, tmp); |
8163 | 9ee6e8bb | pbrook | break;
|
8164 | 9ee6e8bb | pbrook | |
8165 | 9ee6e8bb | pbrook | case 6: /* cps */ |
8166 | 9ee6e8bb | pbrook | ARCH(6);
|
8167 | 9ee6e8bb | pbrook | if (IS_USER(s))
|
8168 | 9ee6e8bb | pbrook | break;
|
8169 | 9ee6e8bb | pbrook | if (IS_M(env)) {
|
8170 | 8984bd2e | pbrook | tmp = tcg_const_i32((insn & (1 << 4)) != 0); |
8171 | 9ee6e8bb | pbrook | /* PRIMASK */
|
8172 | 8984bd2e | pbrook | if (insn & 1) { |
8173 | 8984bd2e | pbrook | addr = tcg_const_i32(16);
|
8174 | 8984bd2e | pbrook | gen_helper_v7m_msr(cpu_env, addr, tmp); |
8175 | 8984bd2e | pbrook | } |
8176 | 9ee6e8bb | pbrook | /* FAULTMASK */
|
8177 | 8984bd2e | pbrook | if (insn & 2) { |
8178 | 8984bd2e | pbrook | addr = tcg_const_i32(17);
|
8179 | 8984bd2e | pbrook | gen_helper_v7m_msr(cpu_env, addr, tmp); |
8180 | 8984bd2e | pbrook | } |
8181 | 9ee6e8bb | pbrook | gen_lookup_tb(s); |
8182 | 9ee6e8bb | pbrook | } else {
|
8183 | 9ee6e8bb | pbrook | if (insn & (1 << 4)) |
8184 | 9ee6e8bb | pbrook | shift = CPSR_A | CPSR_I | CPSR_F; |
8185 | 9ee6e8bb | pbrook | else
|
8186 | 9ee6e8bb | pbrook | shift = 0;
|
8187 | 9ee6e8bb | pbrook | |
8188 | 9ee6e8bb | pbrook | val = ((insn & 7) << 6) & shift; |
8189 | 9ee6e8bb | pbrook | gen_op_movl_T0_im(val); |
8190 | 9ee6e8bb | pbrook | gen_set_psr_T0(s, shift, 0);
|
8191 | 9ee6e8bb | pbrook | } |
8192 | 9ee6e8bb | pbrook | break;
|
8193 | 9ee6e8bb | pbrook | |
8194 | 99c475ab | bellard | default:
|
8195 | 99c475ab | bellard | goto undef;
|
8196 | 99c475ab | bellard | } |
8197 | 99c475ab | bellard | break;
|
8198 | 99c475ab | bellard | |
8199 | 99c475ab | bellard | case 12: |
8200 | 99c475ab | bellard | /* load/store multiple */
|
8201 | 99c475ab | bellard | rn = (insn >> 8) & 0x7; |
8202 | b0109805 | pbrook | addr = load_reg(s, rn); |
8203 | 99c475ab | bellard | for (i = 0; i < 8; i++) { |
8204 | 99c475ab | bellard | if (insn & (1 << i)) { |
8205 | 99c475ab | bellard | if (insn & (1 << 11)) { |
8206 | 99c475ab | bellard | /* load */
|
8207 | b0109805 | pbrook | tmp = gen_ld32(addr, IS_USER(s)); |
8208 | b0109805 | pbrook | store_reg(s, i, tmp); |
8209 | 99c475ab | bellard | } else {
|
8210 | 99c475ab | bellard | /* store */
|
8211 | b0109805 | pbrook | tmp = load_reg(s, i); |
8212 | b0109805 | pbrook | gen_st32(tmp, addr, IS_USER(s)); |
8213 | 99c475ab | bellard | } |
8214 | 5899f386 | bellard | /* advance to the next address */
|
8215 | b0109805 | pbrook | tcg_gen_addi_i32(addr, addr, 4);
|
8216 | 99c475ab | bellard | } |
8217 | 99c475ab | bellard | } |
8218 | 5899f386 | bellard | /* Base register writeback. */
|
8219 | b0109805 | pbrook | if ((insn & (1 << rn)) == 0) { |
8220 | b0109805 | pbrook | store_reg(s, rn, addr); |
8221 | b0109805 | pbrook | } else {
|
8222 | b0109805 | pbrook | dead_tmp(addr); |
8223 | b0109805 | pbrook | } |
8224 | 99c475ab | bellard | break;
|
8225 | 99c475ab | bellard | |
8226 | 99c475ab | bellard | case 13: |
8227 | 99c475ab | bellard | /* conditional branch or swi */
|
8228 | 99c475ab | bellard | cond = (insn >> 8) & 0xf; |
8229 | 99c475ab | bellard | if (cond == 0xe) |
8230 | 99c475ab | bellard | goto undef;
|
8231 | 99c475ab | bellard | |
8232 | 99c475ab | bellard | if (cond == 0xf) { |
8233 | 99c475ab | bellard | /* swi */
|
8234 | 9ee6e8bb | pbrook | gen_set_condexec(s); |
8235 | 5e3f878a | pbrook | gen_set_pc_im(s->pc | 1);
|
8236 | 9ee6e8bb | pbrook | s->is_jmp = DISAS_SWI; |
8237 | 99c475ab | bellard | break;
|
8238 | 99c475ab | bellard | } |
8239 | 99c475ab | bellard | /* generate a conditional jump to next instruction */
|
8240 | e50e6a20 | bellard | s->condlabel = gen_new_label(); |
8241 | d9ba4830 | pbrook | gen_test_cc(cond ^ 1, s->condlabel);
|
8242 | e50e6a20 | bellard | s->condjmp = 1;
|
8243 | 99c475ab | bellard | gen_movl_T1_reg(s, 15);
|
8244 | 99c475ab | bellard | |
8245 | 99c475ab | bellard | /* jump to the offset */
|
8246 | 5899f386 | bellard | val = (uint32_t)s->pc + 2;
|
8247 | 99c475ab | bellard | offset = ((int32_t)insn << 24) >> 24; |
8248 | 5899f386 | bellard | val += offset << 1;
|
8249 | 8aaca4c0 | bellard | gen_jmp(s, val); |
8250 | 99c475ab | bellard | break;
|
8251 | 99c475ab | bellard | |
8252 | 99c475ab | bellard | case 14: |
8253 | 358bf29e | pbrook | if (insn & (1 << 11)) { |
8254 | 9ee6e8bb | pbrook | if (disas_thumb2_insn(env, s, insn))
|
8255 | 9ee6e8bb | pbrook | goto undef32;
|
8256 | 358bf29e | pbrook | break;
|
8257 | 358bf29e | pbrook | } |
8258 | 9ee6e8bb | pbrook | /* unconditional branch */
|
8259 | 99c475ab | bellard | val = (uint32_t)s->pc; |
8260 | 99c475ab | bellard | offset = ((int32_t)insn << 21) >> 21; |
8261 | 99c475ab | bellard | val += (offset << 1) + 2; |
8262 | 8aaca4c0 | bellard | gen_jmp(s, val); |
8263 | 99c475ab | bellard | break;
|
8264 | 99c475ab | bellard | |
8265 | 99c475ab | bellard | case 15: |
8266 | 9ee6e8bb | pbrook | if (disas_thumb2_insn(env, s, insn))
|
8267 | 9ee6e8bb | pbrook | goto undef32;
|
8268 | 9ee6e8bb | pbrook | break;
|
8269 | 99c475ab | bellard | } |
8270 | 99c475ab | bellard | return;
|
8271 | 9ee6e8bb | pbrook | undef32:
|
8272 | 9ee6e8bb | pbrook | gen_set_condexec(s); |
8273 | 5e3f878a | pbrook | gen_set_pc_im(s->pc - 4);
|
8274 | d9ba4830 | pbrook | gen_exception(EXCP_UDEF); |
8275 | 9ee6e8bb | pbrook | s->is_jmp = DISAS_JUMP; |
8276 | 9ee6e8bb | pbrook | return;
|
8277 | 9ee6e8bb | pbrook | illegal_op:
|
8278 | 99c475ab | bellard | undef:
|
8279 | 9ee6e8bb | pbrook | gen_set_condexec(s); |
8280 | 5e3f878a | pbrook | gen_set_pc_im(s->pc - 2);
|
8281 | d9ba4830 | pbrook | gen_exception(EXCP_UDEF); |
8282 | 99c475ab | bellard | s->is_jmp = DISAS_JUMP; |
8283 | 99c475ab | bellard | } |
8284 | 99c475ab | bellard | |
8285 | 2c0262af | bellard | /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
|
8286 | 2c0262af | bellard | basic block 'tb'. If search_pc is TRUE, also generate PC
|
8287 | 2c0262af | bellard | information for each intermediate instruction. */
|
8288 | 5fafdf24 | ths | static inline int gen_intermediate_code_internal(CPUState *env, |
8289 | 5fafdf24 | ths | TranslationBlock *tb, |
8290 | 2c0262af | bellard | int search_pc)
|
8291 | 2c0262af | bellard | { |
8292 | 2c0262af | bellard | DisasContext dc1, *dc = &dc1; |
8293 | 2c0262af | bellard | uint16_t *gen_opc_end; |
8294 | 2c0262af | bellard | int j, lj;
|
8295 | 0fa85d43 | bellard | target_ulong pc_start; |
8296 | b5ff1b31 | bellard | uint32_t next_page_start; |
8297 | 3b46e624 | ths | |
8298 | 2c0262af | bellard | /* generate intermediate code */
|
8299 | b26eefb6 | pbrook | num_temps = 0;
|
8300 | b26eefb6 | pbrook | memset(temps, 0, sizeof(temps)); |
8301 | b26eefb6 | pbrook | |
8302 | 0fa85d43 | bellard | pc_start = tb->pc; |
8303 | 3b46e624 | ths | |
8304 | 2c0262af | bellard | dc->tb = tb; |
8305 | 2c0262af | bellard | |
8306 | 2c0262af | bellard | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
8307 | 2c0262af | bellard | |
8308 | 2c0262af | bellard | dc->is_jmp = DISAS_NEXT; |
8309 | 2c0262af | bellard | dc->pc = pc_start; |
8310 | 8aaca4c0 | bellard | dc->singlestep_enabled = env->singlestep_enabled; |
8311 | e50e6a20 | bellard | dc->condjmp = 0;
|
8312 | 5899f386 | bellard | dc->thumb = env->thumb; |
8313 | 9ee6e8bb | pbrook | dc->condexec_mask = (env->condexec_bits & 0xf) << 1; |
8314 | 9ee6e8bb | pbrook | dc->condexec_cond = env->condexec_bits >> 4;
|
8315 | 6658ffb8 | pbrook | dc->is_mem = 0;
|
8316 | b5ff1b31 | bellard | #if !defined(CONFIG_USER_ONLY)
|
8317 | 9ee6e8bb | pbrook | if (IS_M(env)) {
|
8318 | 9ee6e8bb | pbrook | dc->user = ((env->v7m.exception == 0) && (env->v7m.control & 1)); |
8319 | 9ee6e8bb | pbrook | } else {
|
8320 | 9ee6e8bb | pbrook | dc->user = (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR;
|
8321 | 9ee6e8bb | pbrook | } |
8322 | b5ff1b31 | bellard | #endif
|
8323 | 4373f3ce | pbrook | cpu_F0s = tcg_temp_new(TCG_TYPE_I32); |
8324 | 4373f3ce | pbrook | cpu_F1s = tcg_temp_new(TCG_TYPE_I32); |
8325 | 4373f3ce | pbrook | cpu_F0d = tcg_temp_new(TCG_TYPE_I64); |
8326 | 4373f3ce | pbrook | cpu_F1d = tcg_temp_new(TCG_TYPE_I64); |
8327 | b5ff1b31 | bellard | next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; |
8328 | 2c0262af | bellard | lj = -1;
|
8329 | 9ee6e8bb | pbrook | /* Reset the conditional execution bits immediately. This avoids
|
8330 | 9ee6e8bb | pbrook | complications trying to do it at the end of the block. */
|
8331 | 9ee6e8bb | pbrook | if (env->condexec_bits)
|
8332 | 8f01245e | pbrook | { |
8333 | 8f01245e | pbrook | TCGv tmp = new_tmp(); |
8334 | 8f01245e | pbrook | tcg_gen_movi_i32(tmp, 0);
|
8335 | d9ba4830 | pbrook | store_cpu_field(tmp, condexec_bits); |
8336 | 8f01245e | pbrook | } |
8337 | 2c0262af | bellard | do {
|
8338 | 9ee6e8bb | pbrook | #ifndef CONFIG_USER_ONLY
|
8339 | 9ee6e8bb | pbrook | if (dc->pc >= 0xfffffff0 && IS_M(env)) { |
8340 | 9ee6e8bb | pbrook | /* We always get here via a jump, so know we are not in a
|
8341 | 9ee6e8bb | pbrook | conditional execution block. */
|
8342 | d9ba4830 | pbrook | gen_exception(EXCP_EXCEPTION_EXIT); |
8343 | 9ee6e8bb | pbrook | } |
8344 | 9ee6e8bb | pbrook | #endif
|
8345 | 9ee6e8bb | pbrook | |
8346 | 1fddef4b | bellard | if (env->nb_breakpoints > 0) { |
8347 | 1fddef4b | bellard | for(j = 0; j < env->nb_breakpoints; j++) { |
8348 | 1fddef4b | bellard | if (env->breakpoints[j] == dc->pc) {
|
8349 | 9ee6e8bb | pbrook | gen_set_condexec(dc); |
8350 | 5e3f878a | pbrook | gen_set_pc_im(dc->pc); |
8351 | d9ba4830 | pbrook | gen_exception(EXCP_DEBUG); |
8352 | 1fddef4b | bellard | dc->is_jmp = DISAS_JUMP; |
8353 | 9ee6e8bb | pbrook | /* Advance PC so that clearing the breakpoint will
|
8354 | 9ee6e8bb | pbrook | invalidate this TB. */
|
8355 | 9ee6e8bb | pbrook | dc->pc += 2;
|
8356 | 9ee6e8bb | pbrook | goto done_generating;
|
8357 | 1fddef4b | bellard | break;
|
8358 | 1fddef4b | bellard | } |
8359 | 1fddef4b | bellard | } |
8360 | 1fddef4b | bellard | } |
8361 | 2c0262af | bellard | if (search_pc) {
|
8362 | 2c0262af | bellard | j = gen_opc_ptr - gen_opc_buf; |
8363 | 2c0262af | bellard | if (lj < j) {
|
8364 | 2c0262af | bellard | lj++; |
8365 | 2c0262af | bellard | while (lj < j)
|
8366 | 2c0262af | bellard | gen_opc_instr_start[lj++] = 0;
|
8367 | 2c0262af | bellard | } |
8368 | 0fa85d43 | bellard | gen_opc_pc[lj] = dc->pc; |
8369 | 2c0262af | bellard | gen_opc_instr_start[lj] = 1;
|
8370 | 2c0262af | bellard | } |
8371 | e50e6a20 | bellard | |
8372 | 9ee6e8bb | pbrook | if (env->thumb) {
|
8373 | 9ee6e8bb | pbrook | disas_thumb_insn(env, dc); |
8374 | 9ee6e8bb | pbrook | if (dc->condexec_mask) {
|
8375 | 9ee6e8bb | pbrook | dc->condexec_cond = (dc->condexec_cond & 0xe)
|
8376 | 9ee6e8bb | pbrook | | ((dc->condexec_mask >> 4) & 1); |
8377 | 9ee6e8bb | pbrook | dc->condexec_mask = (dc->condexec_mask << 1) & 0x1f; |
8378 | 9ee6e8bb | pbrook | if (dc->condexec_mask == 0) { |
8379 | 9ee6e8bb | pbrook | dc->condexec_cond = 0;
|
8380 | 9ee6e8bb | pbrook | } |
8381 | 9ee6e8bb | pbrook | } |
8382 | 9ee6e8bb | pbrook | } else {
|
8383 | 9ee6e8bb | pbrook | disas_arm_insn(env, dc); |
8384 | 9ee6e8bb | pbrook | } |
8385 | b26eefb6 | pbrook | if (num_temps) {
|
8386 | b26eefb6 | pbrook | fprintf(stderr, "Internal resource leak before %08x\n", dc->pc);
|
8387 | b26eefb6 | pbrook | num_temps = 0;
|
8388 | b26eefb6 | pbrook | } |
8389 | e50e6a20 | bellard | |
8390 | e50e6a20 | bellard | if (dc->condjmp && !dc->is_jmp) {
|
8391 | e50e6a20 | bellard | gen_set_label(dc->condlabel); |
8392 | e50e6a20 | bellard | dc->condjmp = 0;
|
8393 | e50e6a20 | bellard | } |
8394 | 6658ffb8 | pbrook | /* Terminate the TB on memory ops if watchpoints are present. */
|
8395 | 6658ffb8 | pbrook | /* FIXME: This should be replacd by the deterministic execution
|
8396 | 6658ffb8 | pbrook | * IRQ raising bits. */
|
8397 | 6658ffb8 | pbrook | if (dc->is_mem && env->nb_watchpoints)
|
8398 | 6658ffb8 | pbrook | break;
|
8399 | 6658ffb8 | pbrook | |
8400 | e50e6a20 | bellard | /* Translation stops when a conditional branch is enoutered.
|
8401 | e50e6a20 | bellard | * Otherwise the subsequent code could get translated several times.
|
8402 | b5ff1b31 | bellard | * Also stop translation when a page boundary is reached. This
|
8403 | b5ff1b31 | bellard | * ensures prefech aborts occur at the right place. */
|
8404 | 1fddef4b | bellard | } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end &&
|
8405 | 1fddef4b | bellard | !env->singlestep_enabled && |
8406 | b5ff1b31 | bellard | dc->pc < next_page_start); |
8407 | 9ee6e8bb | pbrook | |
8408 | b5ff1b31 | bellard | /* At this stage dc->condjmp will only be set when the skipped
|
8409 | 9ee6e8bb | pbrook | instruction was a conditional branch or trap, and the PC has
|
8410 | 9ee6e8bb | pbrook | already been written. */
|
8411 | 8aaca4c0 | bellard | if (__builtin_expect(env->singlestep_enabled, 0)) { |
8412 | 8aaca4c0 | bellard | /* Make sure the pc is updated, and raise a debug exception. */
|
8413 | e50e6a20 | bellard | if (dc->condjmp) {
|
8414 | 9ee6e8bb | pbrook | gen_set_condexec(dc); |
8415 | 9ee6e8bb | pbrook | if (dc->is_jmp == DISAS_SWI) {
|
8416 | d9ba4830 | pbrook | gen_exception(EXCP_SWI); |
8417 | 9ee6e8bb | pbrook | } else {
|
8418 | d9ba4830 | pbrook | gen_exception(EXCP_DEBUG); |
8419 | 9ee6e8bb | pbrook | } |
8420 | e50e6a20 | bellard | gen_set_label(dc->condlabel); |
8421 | e50e6a20 | bellard | } |
8422 | e50e6a20 | bellard | if (dc->condjmp || !dc->is_jmp) {
|
8423 | 5e3f878a | pbrook | gen_set_pc_im(dc->pc); |
8424 | e50e6a20 | bellard | dc->condjmp = 0;
|
8425 | 8aaca4c0 | bellard | } |
8426 | 9ee6e8bb | pbrook | gen_set_condexec(dc); |
8427 | 9ee6e8bb | pbrook | if (dc->is_jmp == DISAS_SWI && !dc->condjmp) {
|
8428 | d9ba4830 | pbrook | gen_exception(EXCP_SWI); |
8429 | 9ee6e8bb | pbrook | } else {
|
8430 | 9ee6e8bb | pbrook | /* FIXME: Single stepping a WFI insn will not halt
|
8431 | 9ee6e8bb | pbrook | the CPU. */
|
8432 | d9ba4830 | pbrook | gen_exception(EXCP_DEBUG); |
8433 | 9ee6e8bb | pbrook | } |
8434 | 8aaca4c0 | bellard | } else {
|
8435 | 9ee6e8bb | pbrook | /* While branches must always occur at the end of an IT block,
|
8436 | 9ee6e8bb | pbrook | there are a few other things that can cause us to terminate
|
8437 | 9ee6e8bb | pbrook | the TB in the middel of an IT block:
|
8438 | 9ee6e8bb | pbrook | - Exception generating instructions (bkpt, swi, undefined).
|
8439 | 9ee6e8bb | pbrook | - Page boundaries.
|
8440 | 9ee6e8bb | pbrook | - Hardware watchpoints.
|
8441 | 9ee6e8bb | pbrook | Hardware breakpoints have already been handled and skip this code.
|
8442 | 9ee6e8bb | pbrook | */
|
8443 | 9ee6e8bb | pbrook | gen_set_condexec(dc); |
8444 | 8aaca4c0 | bellard | switch(dc->is_jmp) {
|
8445 | 8aaca4c0 | bellard | case DISAS_NEXT:
|
8446 | 6e256c93 | bellard | gen_goto_tb(dc, 1, dc->pc);
|
8447 | 8aaca4c0 | bellard | break;
|
8448 | 8aaca4c0 | bellard | default:
|
8449 | 8aaca4c0 | bellard | case DISAS_JUMP:
|
8450 | 8aaca4c0 | bellard | case DISAS_UPDATE:
|
8451 | 8aaca4c0 | bellard | /* indicate that the hash table must be used to find the next TB */
|
8452 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
8453 | 8aaca4c0 | bellard | break;
|
8454 | 8aaca4c0 | bellard | case DISAS_TB_JUMP:
|
8455 | 8aaca4c0 | bellard | /* nothing more to generate */
|
8456 | 8aaca4c0 | bellard | break;
|
8457 | 9ee6e8bb | pbrook | case DISAS_WFI:
|
8458 | d9ba4830 | pbrook | gen_helper_wfi(); |
8459 | 9ee6e8bb | pbrook | break;
|
8460 | 9ee6e8bb | pbrook | case DISAS_SWI:
|
8461 | d9ba4830 | pbrook | gen_exception(EXCP_SWI); |
8462 | 9ee6e8bb | pbrook | break;
|
8463 | 8aaca4c0 | bellard | } |
8464 | e50e6a20 | bellard | if (dc->condjmp) {
|
8465 | e50e6a20 | bellard | gen_set_label(dc->condlabel); |
8466 | 9ee6e8bb | pbrook | gen_set_condexec(dc); |
8467 | 6e256c93 | bellard | gen_goto_tb(dc, 1, dc->pc);
|
8468 | e50e6a20 | bellard | dc->condjmp = 0;
|
8469 | e50e6a20 | bellard | } |
8470 | 2c0262af | bellard | } |
8471 | 9ee6e8bb | pbrook | done_generating:
|
8472 | 2c0262af | bellard | *gen_opc_ptr = INDEX_op_end; |
8473 | 2c0262af | bellard | |
8474 | 2c0262af | bellard | #ifdef DEBUG_DISAS
|
8475 | e19e89a5 | bellard | if (loglevel & CPU_LOG_TB_IN_ASM) {
|
8476 | 2c0262af | bellard | fprintf(logfile, "----------------\n");
|
8477 | 2c0262af | bellard | fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
|
8478 | 5899f386 | bellard | target_disas(logfile, pc_start, dc->pc - pc_start, env->thumb); |
8479 | 2c0262af | bellard | fprintf(logfile, "\n");
|
8480 | 2c0262af | bellard | } |
8481 | 2c0262af | bellard | #endif
|
8482 | b5ff1b31 | bellard | if (search_pc) {
|
8483 | b5ff1b31 | bellard | j = gen_opc_ptr - gen_opc_buf; |
8484 | b5ff1b31 | bellard | lj++; |
8485 | b5ff1b31 | bellard | while (lj <= j)
|
8486 | b5ff1b31 | bellard | gen_opc_instr_start[lj++] = 0;
|
8487 | b5ff1b31 | bellard | } else {
|
8488 | 2c0262af | bellard | tb->size = dc->pc - pc_start; |
8489 | b5ff1b31 | bellard | } |
8490 | 2c0262af | bellard | return 0; |
8491 | 2c0262af | bellard | } |
8492 | 2c0262af | bellard | |
8493 | 2c0262af | bellard | int gen_intermediate_code(CPUState *env, TranslationBlock *tb)
|
8494 | 2c0262af | bellard | { |
8495 | 2c0262af | bellard | return gen_intermediate_code_internal(env, tb, 0); |
8496 | 2c0262af | bellard | } |
8497 | 2c0262af | bellard | |
8498 | 2c0262af | bellard | int gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
|
8499 | 2c0262af | bellard | { |
8500 | 2c0262af | bellard | return gen_intermediate_code_internal(env, tb, 1); |
8501 | 2c0262af | bellard | } |
8502 | 2c0262af | bellard | |
8503 | b5ff1b31 | bellard | static const char *cpu_mode_names[16] = { |
8504 | b5ff1b31 | bellard | "usr", "fiq", "irq", "svc", "???", "???", "???", "abt", |
8505 | b5ff1b31 | bellard | "???", "???", "???", "und", "???", "???", "???", "sys" |
8506 | b5ff1b31 | bellard | }; |
8507 | 9ee6e8bb | pbrook | |
8508 | 5fafdf24 | ths | void cpu_dump_state(CPUState *env, FILE *f,
|
8509 | 7fe48483 | bellard | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
8510 | 7fe48483 | bellard | int flags)
|
8511 | 2c0262af | bellard | { |
8512 | 2c0262af | bellard | int i;
|
8513 | bc380d17 | bellard | union {
|
8514 | b7bcbe95 | bellard | uint32_t i; |
8515 | b7bcbe95 | bellard | float s;
|
8516 | b7bcbe95 | bellard | } s0, s1; |
8517 | b7bcbe95 | bellard | CPU_DoubleU d; |
8518 | a94a6abf | pbrook | /* ??? This assumes float64 and double have the same layout.
|
8519 | a94a6abf | pbrook | Oh well, it's only debug dumps. */
|
8520 | a94a6abf | pbrook | union {
|
8521 | a94a6abf | pbrook | float64 f64; |
8522 | a94a6abf | pbrook | double d;
|
8523 | a94a6abf | pbrook | } d0; |
8524 | b5ff1b31 | bellard | uint32_t psr; |
8525 | 2c0262af | bellard | |
8526 | 2c0262af | bellard | for(i=0;i<16;i++) { |
8527 | 7fe48483 | bellard | cpu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
|
8528 | 2c0262af | bellard | if ((i % 4) == 3) |
8529 | 7fe48483 | bellard | cpu_fprintf(f, "\n");
|
8530 | 2c0262af | bellard | else
|
8531 | 7fe48483 | bellard | cpu_fprintf(f, " ");
|
8532 | 2c0262af | bellard | } |
8533 | b5ff1b31 | bellard | psr = cpsr_read(env); |
8534 | 687fa640 | ths | cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%d\n",
|
8535 | 687fa640 | ths | psr, |
8536 | b5ff1b31 | bellard | psr & (1 << 31) ? 'N' : '-', |
8537 | b5ff1b31 | bellard | psr & (1 << 30) ? 'Z' : '-', |
8538 | b5ff1b31 | bellard | psr & (1 << 29) ? 'C' : '-', |
8539 | b5ff1b31 | bellard | psr & (1 << 28) ? 'V' : '-', |
8540 | 5fafdf24 | ths | psr & CPSR_T ? 'T' : 'A', |
8541 | b5ff1b31 | bellard | cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26); |
8542 | b7bcbe95 | bellard | |
8543 | 5e3f878a | pbrook | #if 0
|
8544 | b7bcbe95 | bellard | for (i = 0; i < 16; i++) {
|
8545 | 8e96005d | bellard | d.d = env->vfp.regs[i];
|
8546 | 8e96005d | bellard | s0.i = d.l.lower;
|
8547 | 8e96005d | bellard | s1.i = d.l.upper;
|
8548 | a94a6abf | pbrook | d0.f64 = d.d;
|
8549 | a94a6abf | pbrook | cpu_fprintf(f, "s%02d=%08x(%8g) s%02d=%08x(%8g) d%02d=%08x%08x(%8g)\n",
|
8550 | b7bcbe95 | bellard | i * 2, (int)s0.i, s0.s,
|
8551 | a94a6abf | pbrook | i * 2 + 1, (int)s1.i, s1.s,
|
8552 | b7bcbe95 | bellard | i, (int)(uint32_t)d.l.upper, (int)(uint32_t)d.l.lower,
|
8553 | a94a6abf | pbrook | d0.d);
|
8554 | b7bcbe95 | bellard | }
|
8555 | 40f137e1 | pbrook | cpu_fprintf(f, "FPSCR: %08x\n", (int)env->vfp.xregs[ARM_VFP_FPSCR]);
|
8556 | 5e3f878a | pbrook | #endif
|
8557 | 2c0262af | bellard | } |