Revision 8fec2b8c
| b/cpu-exec.c | ||
|---|---|---|
| 532 | 532 |
} |
| 533 | 533 |
} |
| 534 | 534 |
#ifdef DEBUG_EXEC |
| 535 |
if ((loglevel & CPU_LOG_TB_CPU)) {
|
|
| 535 |
if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
|
|
| 536 | 536 |
/* restore flags in standard format */ |
| 537 | 537 |
regs_to_env(); |
| 538 | 538 |
#if defined(TARGET_I386) |
| b/hw/ppc_prep.c | ||
|---|---|---|
| 52 | 52 |
#if defined (HARD_DEBUG_PPC_IO) |
| 53 | 53 |
#define PPC_IO_DPRINTF(fmt, args...) \ |
| 54 | 54 |
do { \
|
| 55 |
if (loglevel & CPU_LOG_IOPORT) { \
|
|
| 55 |
if (qemu_loglevel_mask(CPU_LOG_IOPORT)) { \
|
|
| 56 | 56 |
qemu_log("%s: " fmt, __func__ , ##args); \
|
| 57 | 57 |
} else { \
|
| 58 | 58 |
printf("%s : " fmt, __func__ , ##args); \
|
| b/target-alpha/translate.c | ||
|---|---|---|
| 2442 | 2442 |
} |
| 2443 | 2443 |
#if defined ALPHA_DEBUG_DISAS |
| 2444 | 2444 |
log_cpu_state_mask(CPU_LOG_TB_CPU, env, 0); |
| 2445 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
|
| 2445 |
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
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|
| 2446 | 2446 |
qemu_log("IN: %s\n", lookup_symbol(pc_start));
|
| 2447 | 2447 |
log_target_disas(pc_start, ctx.pc - pc_start, 1); |
| 2448 | 2448 |
qemu_log("\n");
|
| b/target-arm/translate.c | ||
|---|---|---|
| 8870 | 8870 |
*gen_opc_ptr = INDEX_op_end; |
| 8871 | 8871 |
|
| 8872 | 8872 |
#ifdef DEBUG_DISAS |
| 8873 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
|
| 8873 |
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
|
| 8874 | 8874 |
qemu_log("----------------\n");
|
| 8875 | 8875 |
qemu_log("IN: %s\n", lookup_symbol(pc_start));
|
| 8876 | 8876 |
log_target_disas(pc_start, dc->pc - pc_start, env->thumb); |
| b/target-cris/translate.c | ||
|---|---|---|
| 3035 | 3035 |
unsigned int insn_len = 2; |
| 3036 | 3036 |
int i; |
| 3037 | 3037 |
|
| 3038 |
if (unlikely(loglevel & CPU_LOG_TB_OP))
|
|
| 3038 |
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
|
|
| 3039 | 3039 |
tcg_gen_debug_insn_start(dc->pc); |
| 3040 | 3040 |
|
| 3041 | 3041 |
/* Load a halfword onto the instruction register. */ |
| ... | ... | |
| 3179 | 3179 |
|
| 3180 | 3180 |
dc->cpustate_changed = 0; |
| 3181 | 3181 |
|
| 3182 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
|
| 3182 |
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
|
| 3183 | 3183 |
qemu_log( |
| 3184 | 3184 |
"srch=%d pc=%x %x flg=%llx bt=%x ds=%u ccs=%x\n" |
| 3185 | 3185 |
"pid=%x usp=%x\n" |
| ... | ... | |
| 3331 | 3331 |
|
| 3332 | 3332 |
#ifdef DEBUG_DISAS |
| 3333 | 3333 |
#if !DISAS_CRIS |
| 3334 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
|
| 3334 |
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
|
| 3335 | 3335 |
log_target_disas(pc_start, dc->pc - pc_start, 0); |
| 3336 | 3336 |
qemu_log("\nisize=%d osize=%zd\n",
|
| 3337 | 3337 |
dc->pc - pc_start, gen_opc_ptr - gen_opc_buf); |
| b/target-i386/op_helper.c | ||
|---|---|---|
| 1206 | 1206 |
void do_interrupt(int intno, int is_int, int error_code, |
| 1207 | 1207 |
target_ulong next_eip, int is_hw) |
| 1208 | 1208 |
{
|
| 1209 |
if (loglevel & CPU_LOG_INT) {
|
|
| 1209 |
if (qemu_loglevel_mask(CPU_LOG_INT)) {
|
|
| 1210 | 1210 |
if ((env->cr[0] & CR0_PE_MASK)) {
|
| 1211 | 1211 |
static int count; |
| 1212 | 1212 |
qemu_log("%6d: v=%02x e=%04x i=%d cpl=%d IP=%04x:" TARGET_FMT_lx " pc=" TARGET_FMT_lx " SP=%04x:" TARGET_FMT_lx,
|
| b/target-i386/translate.c | ||
|---|---|---|
| 3961 | 3961 |
target_ulong next_eip, tval; |
| 3962 | 3962 |
int rex_w, rex_r; |
| 3963 | 3963 |
|
| 3964 |
if (unlikely(loglevel & CPU_LOG_TB_OP))
|
|
| 3964 |
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
|
|
| 3965 | 3965 |
tcg_gen_debug_insn_start(pc_start); |
| 3966 | 3966 |
s->pc = pc_start; |
| 3967 | 3967 |
prefixes = 0; |
| ... | ... | |
| 7676 | 7676 |
|
| 7677 | 7677 |
#ifdef DEBUG_DISAS |
| 7678 | 7678 |
log_cpu_state_mask(CPU_LOG_TB_CPU, env, X86_DUMP_CCOP); |
| 7679 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
|
| 7679 |
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
|
| 7680 | 7680 |
int disas_flags; |
| 7681 | 7681 |
qemu_log("----------------\n");
|
| 7682 | 7682 |
qemu_log("IN: %s\n", lookup_symbol(pc_start));
|
| ... | ... | |
| 7712 | 7712 |
{
|
| 7713 | 7713 |
int cc_op; |
| 7714 | 7714 |
#ifdef DEBUG_DISAS |
| 7715 |
if (loglevel & CPU_LOG_TB_OP) {
|
|
| 7715 |
if (qemu_loglevel_mask(CPU_LOG_TB_OP)) {
|
|
| 7716 | 7716 |
int i; |
| 7717 | 7717 |
qemu_log("RESTORE:\n");
|
| 7718 | 7718 |
for(i = 0;i <= pc_pos; i++) {
|
| b/target-m68k/translate.c | ||
|---|---|---|
| 3063 | 3063 |
*gen_opc_ptr = INDEX_op_end; |
| 3064 | 3064 |
|
| 3065 | 3065 |
#ifdef DEBUG_DISAS |
| 3066 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
|
| 3066 |
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
|
| 3067 | 3067 |
qemu_log("----------------\n");
|
| 3068 | 3068 |
qemu_log("IN: %s\n", lookup_symbol(pc_start));
|
| 3069 | 3069 |
log_target_disas(pc_start, dc->pc - pc_start, 0); |
| b/target-mips/op_helper.c | ||
|---|---|---|
| 1194 | 1194 |
old = env->CP0_Status; |
| 1195 | 1195 |
env->CP0_Status = (env->CP0_Status & ~mask) | val; |
| 1196 | 1196 |
compute_hflags(env); |
| 1197 |
if (loglevel & CPU_LOG_EXEC)
|
|
| 1197 |
if (qemu_loglevel_mask(CPU_LOG_EXEC))
|
|
| 1198 | 1198 |
do_mtc0_status_debug(old, val); |
| 1199 | 1199 |
cpu_mips_update_irq(env); |
| 1200 | 1200 |
} |
| ... | ... | |
| 1705 | 1705 |
|
| 1706 | 1706 |
static void debug_pre_eret (void) |
| 1707 | 1707 |
{
|
| 1708 |
if (loglevel & CPU_LOG_EXEC) {
|
|
| 1708 |
if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
|
|
| 1709 | 1709 |
qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
|
| 1710 | 1710 |
env->active_tc.PC, env->CP0_EPC); |
| 1711 | 1711 |
if (env->CP0_Status & (1 << CP0St_ERL)) |
| ... | ... | |
| 1718 | 1718 |
|
| 1719 | 1719 |
static void debug_post_eret (void) |
| 1720 | 1720 |
{
|
| 1721 |
if (loglevel & CPU_LOG_EXEC) {
|
|
| 1721 |
if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
|
|
| 1722 | 1722 |
qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
|
| 1723 | 1723 |
env->active_tc.PC, env->CP0_EPC); |
| 1724 | 1724 |
if (env->CP0_Status & (1 << CP0St_ERL)) |
| b/target-mips/translate.c | ||
|---|---|---|
| 8289 | 8289 |
} |
| 8290 | 8290 |
#ifdef DEBUG_DISAS |
| 8291 | 8291 |
LOG_DISAS("\n");
|
| 8292 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
|
| 8292 |
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
|
| 8293 | 8293 |
qemu_log("IN: %s\n", lookup_symbol(pc_start));
|
| 8294 | 8294 |
log_target_disas(pc_start, ctx.pc - pc_start, 0); |
| 8295 | 8295 |
qemu_log("\n");
|
| b/target-ppc/translate.c | ||
|---|---|---|
| 8334 | 8334 |
#if defined(DEBUG_DISAS) |
| 8335 | 8335 |
qemu_log_mask(CPU_LOG_TB_CPU, "---------------- excp: %04x\n", ctx.exception); |
| 8336 | 8336 |
log_cpu_state_mask(CPU_LOG_TB_CPU, env, 0); |
| 8337 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
|
| 8337 |
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
|
| 8338 | 8338 |
int flags; |
| 8339 | 8339 |
flags = env->bfd_mach; |
| 8340 | 8340 |
flags |= ctx.le_mode << 16; |
| b/target-sh4/helper.c | ||
|---|---|---|
| 105 | 105 |
} |
| 106 | 106 |
} |
| 107 | 107 |
|
| 108 |
if (loglevel & CPU_LOG_INT) {
|
|
| 108 |
if (qemu_loglevel_mask(CPU_LOG_INT)) {
|
|
| 109 | 109 |
const char *expname; |
| 110 | 110 |
switch (env->exception_index) {
|
| 111 | 111 |
case 0x0e0: |
| b/target-sh4/translate.c | ||
|---|---|---|
| 1937 | 1937 |
#ifdef SH4_DEBUG_DISAS |
| 1938 | 1938 |
qemu_log_mask(CPU_LOG_TB_IN_ASM, "\n"); |
| 1939 | 1939 |
#endif |
| 1940 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
|
| 1940 |
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
|
| 1941 | 1941 |
qemu_log("IN:\n"); /* , lookup_symbol(pc_start)); */
|
| 1942 | 1942 |
log_target_disas(pc_start, ctx.pc - pc_start, 0); |
| 1943 | 1943 |
qemu_log("\n");
|
| b/target-sparc/op_helper.c | ||
|---|---|---|
| 2811 | 2811 |
int intno = env->exception_index; |
| 2812 | 2812 |
|
| 2813 | 2813 |
#ifdef DEBUG_PCALL |
| 2814 |
if (loglevel & CPU_LOG_INT) {
|
|
| 2814 |
if (qemu_loglevel_mask(CPU_LOG_INT)) {
|
|
| 2815 | 2815 |
static int count; |
| 2816 | 2816 |
const char *name; |
| 2817 | 2817 |
|
| ... | ... | |
| 2942 | 2942 |
int cwp, intno = env->exception_index; |
| 2943 | 2943 |
|
| 2944 | 2944 |
#ifdef DEBUG_PCALL |
| 2945 |
if (loglevel & CPU_LOG_INT) {
|
|
| 2945 |
if (qemu_loglevel_mask(CPU_LOG_INT)) {
|
|
| 2946 | 2946 |
static int count; |
| 2947 | 2947 |
const char *name; |
| 2948 | 2948 |
|
| b/target-sparc/translate.c | ||
|---|---|---|
| 1933 | 1933 |
{
|
| 1934 | 1934 |
unsigned int insn, opc, rs1, rs2, rd; |
| 1935 | 1935 |
|
| 1936 |
if (unlikely(loglevel & CPU_LOG_TB_OP))
|
|
| 1936 |
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
|
|
| 1937 | 1937 |
tcg_gen_debug_insn_start(dc->pc); |
| 1938 | 1938 |
insn = ldl_code(dc->pc); |
| 1939 | 1939 |
opc = GET_FIELD(insn, 0, 1); |
| ... | ... | |
| 4905 | 4905 |
tb->icount = num_insns; |
| 4906 | 4906 |
} |
| 4907 | 4907 |
#ifdef DEBUG_DISAS |
| 4908 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
|
| 4908 |
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
|
| 4909 | 4909 |
qemu_log("--------------\n");
|
| 4910 | 4910 |
qemu_log("IN: %s\n", lookup_symbol(pc_start));
|
| 4911 | 4911 |
log_target_disas(pc_start, last_pc + 4 - pc_start, 0); |
| b/tcg/tcg.c | ||
|---|---|---|
| 1878 | 1878 |
const TCGArg *args; |
| 1879 | 1879 |
|
| 1880 | 1880 |
#ifdef DEBUG_DISAS |
| 1881 |
if (unlikely(loglevel & CPU_LOG_TB_OP)) {
|
|
| 1881 |
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
|
|
| 1882 | 1882 |
qemu_log("OP:\n");
|
| 1883 | 1883 |
tcg_dump_ops(s, logfile); |
| 1884 | 1884 |
qemu_log("\n");
|
| ... | ... | |
| 1894 | 1894 |
#endif |
| 1895 | 1895 |
|
| 1896 | 1896 |
#ifdef DEBUG_DISAS |
| 1897 |
if (unlikely(loglevel & CPU_LOG_TB_OP_OPT)) {
|
|
| 1897 |
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT))) {
|
|
| 1898 | 1898 |
qemu_log("OP after la:\n");
|
| 1899 | 1899 |
tcg_dump_ops(s, logfile); |
| 1900 | 1900 |
qemu_log("\n");
|
| b/translate-all.c | ||
|---|---|---|
| 127 | 127 |
#endif |
| 128 | 128 |
|
| 129 | 129 |
#ifdef DEBUG_DISAS |
| 130 |
if (loglevel & CPU_LOG_TB_OUT_ASM) {
|
|
| 130 |
if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM)) {
|
|
| 131 | 131 |
qemu_log("OUT: [size=%d]\n", *gen_code_size_ptr);
|
| 132 | 132 |
log_disas(tb->tc_ptr, *gen_code_size_ptr); |
| 133 | 133 |
qemu_log("\n");
|
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