Revision 9004627f

b/gdbstub.c
828 828
  for (i = 0; i < 16; i++)
829 829
	  ptr += cris_save_32 (ptr, env->regs[i]);
830 830

  
831
  srs = env->pregs[SR_SRS];
831
  srs = env->pregs[PR_SRS];
832 832

  
833 833
  ptr += cris_save_8 (ptr, env->pregs[0]);
834 834
  ptr += cris_save_8 (ptr, env->pregs[1]);
b/target-cris/cpu.h
239 239

  
240 240
#include "cpu-all.h"
241 241

  
242
/* Register aliases.  */
243
#define REG_SP  14
244
#define REG_ACR 15
245
#define REG_MOF 7
246

  
247
/* Support regs.  */
248
#define SR_PID 2
249
#define SR_SRS 3
250
#define SR_EBP 9
251
#define SR_ERP 10
252
#define SR_CCS 13
253

  
254
/* Support func regs.  */
242
/* Register aliases. R0 - R15 */
243
#define R_FP  8
244
#define R_SP  14
245
#define R_ACR 15
246

  
247
/* Support regs, P0 - P15  */
248
#define PR_PID 2
249
#define PR_SRS 3
250
#define PR_MOF 7
251
#define PR_EBP 9
252
#define PR_ERP 10
253
#define PR_SRP 11
254
#define PR_CCS 13
255

  
256
/* Support function regs.  */
255 257
#define SFR_RW_GC_CFG      0][0
256 258
#define SFR_RW_MM_CFG      1][0
257 259
#define SFR_RW_MM_KBASE_LO 1][1
b/target-cris/helper.c
82 82
{
83 83
	uint32_t ccs;
84 84
	/* Apply the ccs shift.  */
85
	ccs = env->pregs[SR_CCS];
85
	ccs = env->pregs[PR_CCS];
86 86
	ccs = (ccs & 0xc0000000) | ((ccs << 12) >> 2);
87
//	printf ("ccs=%x %x\n", env->pregs[SR_CCS], ccs);
88
	env->pregs[SR_CCS] = ccs;
87
	env->pregs[PR_CCS] = ccs;
89 88
}
90 89

  
91 90
void do_interrupt(CPUState *env)
......
104 103
	switch (env->exception_index)
105 104
	{
106 105
		case EXCP_BREAK:
107
//			printf ("BREAK! %d\n", env->trapnr);
108 106
			irqnum = env->trapnr;
109
			ebp = env->pregs[SR_EBP];
107
			ebp = env->pregs[PR_EBP];
110 108
			isr = ldl_code(ebp + irqnum * 4);
111
			env->pregs[SR_ERP] = env->pc + 2;
109
			env->pregs[PR_ERP] = env->pc + 2;
112 110
			env->pc = isr;
113 111

  
114 112
			cris_shift_ccs(env);
......
117 115
		case EXCP_MMU_MISS:
118 116
//			printf ("MMU miss\n");
119 117
			irqnum = 4;
120
			ebp = env->pregs[SR_EBP];
118
			ebp = env->pregs[PR_EBP];
121 119
			isr = ldl_code(ebp + irqnum * 4);
122
			env->pregs[SR_ERP] = env->pc;
120
			env->pregs[PR_ERP] = env->pc;
123 121
			env->pc = isr;
124 122
			cris_shift_ccs(env);
125 123
			break;
......
131 129
			if (env->interrupt_request & CPU_INTERRUPT_HARD) {
132 130
				if (!env->pending_interrupts)
133 131
					return;
134
				if (!(env->pregs[SR_CCS] & I_FLAG)) {
132
				if (!(env->pregs[PR_CCS] & I_FLAG)) {
135 133
					return;
136 134
				}
137 135

  
138 136
				irqnum = 31 - clz32(env->pending_interrupts);
139 137
				irqnum += 0x30;
140
				ebp = env->pregs[SR_EBP];
138
				ebp = env->pregs[PR_EBP];
141 139
				isr = ldl_code(ebp + irqnum * 4);
142
				env->pregs[SR_ERP] = env->pc;
140
				env->pregs[PR_ERP] = env->pc;
143 141
				env->pc = isr;
144 142

  
145 143
				cris_shift_ccs(env);
......
161 159

  
162 160
target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
163 161
{
164
//	printf ("%s\n", __func__);
165 162
	uint32_t phy = addr;
166 163
	struct cris_mmu_result_t res;
167 164
	int miss;
b/target-cris/mmu.c
87 87
		pid = EXTRACT_FIELD(hi, 0, 7);
88 88

  
89 89
		if (vpn == vpage
90
		    && pid == env->pregs[SR_PID]) {
90
		    && pid == env->pregs[PR_PID]) {
91 91
			match = 1;
92 92
			break;
93 93
		}
......
104 104
	printf ("%s match=%d vaddr=%x vpage=%x vpn=%x pfn=%x pid=%x %x\n",
105 105
		__func__, match,
106 106
		vaddr, vpage,
107
		vpn, pfn, pid, env->pregs[SR_PID]);
107
		vpn, pfn, pid, env->pregs[PR_PID]);
108 108
	res->pfn = pfn;
109 109
	return !match;
110 110
}
b/target-cris/op.c
185 185
	uint32_t ccs;
186 186

  
187 187
	/* Apply the ccs shift.  */
188
	ccs = env->pregs[SR_CCS];
188
	ccs = env->pregs[PR_CCS];
189 189
	ccs = (ccs & 0xc0000000) | ((ccs << 12) >> 2);
190
	env->pregs[SR_CCS] = ccs;
190
	env->pregs[PR_CCS] = ccs;
191 191
	RETURN();
192 192
}
193 193
void OPPROTO op_ccs_rshift (void)
......
195 195
	uint32_t ccs;
196 196

  
197 197
	/* Apply the ccs shift.  */
198
	ccs = env->pregs[SR_CCS];
198
	ccs = env->pregs[PR_CCS];
199 199
	ccs = (ccs & 0xc0000000) | (ccs >> 10);
200
	env->pregs[SR_CCS] = ccs;
200
	env->pregs[PR_CCS] = ccs;
201 201
	RETURN();
202 202
}
203 203

  
204 204
void OPPROTO op_setf (void)
205 205
{
206
	env->pregs[SR_CCS] |= PARAM1;
206
	env->pregs[PR_CCS] |= PARAM1;
207 207
	RETURN();
208 208
}
209 209

  
210 210
void OPPROTO op_clrf (void)
211 211
{
212
	env->pregs[SR_CCS] &= ~PARAM1;
212
	env->pregs[PR_CCS] &= ~PARAM1;
213 213
	RETURN();
214 214
}
215 215

  
......
254 254
}
255 255
void OPPROTO op_movl_T0_flags (void)
256 256
{
257
	T0 = env->pregs[SR_CCS];
257
	T0 = env->pregs[PR_CCS];
258 258
	RETURN();
259 259
}
260 260
void OPPROTO op_movl_flags_T0 (void)
261 261
{
262
	env->pregs[SR_CCS] = T0;
262
	env->pregs[PR_CCS] = T0;
263 263
	RETURN();
264 264
}
265 265

  
266 266
void OPPROTO op_movl_sreg_T0 (void)
267 267
{
268
	env->sregs[env->pregs[SR_SRS]][PARAM1] = T0;
268
	env->sregs[env->pregs[PR_SRS]][PARAM1] = T0;
269 269
	RETURN();
270 270
}
271 271

  
272 272
void OPPROTO op_movl_tlb_lo_T0 (void)
273 273
{
274 274
	int srs;
275
	srs = env->pregs[SR_SRS];
275
	srs = env->pregs[PR_SRS];
276 276
	if (srs == 1 || srs == 2)
277 277
	{
278 278
		int set;
......
296 296

  
297 297
void OPPROTO op_movl_T0_sreg (void)
298 298
{
299
	T0 = env->sregs[env->pregs[SR_SRS]][PARAM1];
299
	T0 = env->sregs[env->pregs[PR_SRS]][PARAM1];
300 300
	RETURN();
301 301
}
302 302

  
......
356 356
	int x;
357 357

  
358 358
	/* Extended arithmetics, leave the z flag alone.  */
359
	env->debug3 = env->pregs[SR_CCS];
359
	env->debug3 = env->pregs[PR_CCS];
360 360

  
361 361
	if (env->cc_x_live)
362 362
		x = env->cc_x;
363 363
	else
364
		x = env->pregs[SR_CCS] & X_FLAG;
364
		x = env->pregs[PR_CCS] & X_FLAG;
365 365

  
366 366
	if ((x || env->cc_op == CC_OP_ADDC)
367 367
	    && flags & Z_FLAG)
368 368
		env->cc_mask &= ~Z_FLAG;
369 369

  
370 370
	/* all insn clear the x-flag except setf or clrf.  */
371
	env->pregs[SR_CCS] &= ~(env->cc_mask | X_FLAG);
371
	env->pregs[PR_CCS] &= ~(env->cc_mask | X_FLAG);
372 372
	flags &= env->cc_mask;
373
	env->pregs[SR_CCS] |= flags;
373
	env->pregs[PR_CCS] |= flags;
374 374
	RETURN();
375 375
}
376 376

  
......
778 778

  
779 779
void OPPROTO op_addxl_T0_C (void)
780 780
{
781
	if (env->pregs[SR_CCS] & X_FLAG)
782
		T0 += !!(env->pregs[SR_CCS] & C_FLAG);
781
	if (env->pregs[PR_CCS] & X_FLAG)
782
		T0 += !!(env->pregs[PR_CCS] & C_FLAG);
783 783
	RETURN();
784 784
}
785 785
void OPPROTO op_subxl_T0_C (void)
786 786
{
787
	if (env->pregs[SR_CCS] & X_FLAG)
788
		T0 -= !!(env->pregs[SR_CCS] & C_FLAG);
787
	if (env->pregs[PR_CCS] & X_FLAG)
788
		T0 -= !!(env->pregs[PR_CCS] & C_FLAG);
789 789
	RETURN();
790 790
}
791 791
void OPPROTO op_addl_T0_C (void)
792 792
{
793
	T0 += !!(env->pregs[SR_CCS] & C_FLAG);
793
	T0 += !!(env->pregs[PR_CCS] & C_FLAG);
794 794
	RETURN();
795 795
}
796 796
void OPPROTO op_addl_T0_R (void)
797 797
{
798
	T0 += !!(env->pregs[SR_CCS] & R_FLAG);
798
	T0 += !!(env->pregs[PR_CCS] & R_FLAG);
799 799
	RETURN();
800 800
}
801 801

  
802 802
void OPPROTO op_clr_R (void)
803 803
{
804
	env->pregs[SR_CCS] &= ~R_FLAG;
804
	env->pregs[PR_CCS] &= ~R_FLAG;
805 805
	RETURN();
806 806
}
807 807

  
......
880 880

  
881 881
	tmp = t0 * t1;
882 882
	T0 = tmp & 0xffffffff;
883
	env->pregs[REG_MOF] = tmp >> 32;
883
	env->pregs[PR_MOF] = tmp >> 32;
884 884
	RETURN();
885 885
}
886 886

  
......
892 892

  
893 893
	tmp = t0 * t1;
894 894
	T0 = tmp & 0xffffffff;
895
	env->pregs[REG_MOF] = tmp >> 32;
895
	env->pregs[PR_MOF] = tmp >> 32;
896 896
	RETURN();
897 897
}
898 898

  
......
1042 1042
}
1043 1043

  
1044 1044
void OPPROTO op_tst_cc_eq (void) {
1045
	uint32_t flags = env->pregs[SR_CCS];
1045
	uint32_t flags = env->pregs[PR_CCS];
1046 1046
	int z_set;
1047 1047

  
1048 1048
	z_set = !!(flags & Z_FLAG);
......
1056 1056
}
1057 1057

  
1058 1058
void OPPROTO op_tst_cc_ne (void) {
1059
	uint32_t flags = env->pregs[SR_CCS];
1059
	uint32_t flags = env->pregs[PR_CCS];
1060 1060
	int z_set;
1061 1061

  
1062 1062
	z_set = !!(flags & Z_FLAG);
......
1069 1069
}
1070 1070

  
1071 1071
void OPPROTO op_tst_cc_cc (void) {
1072
	uint32_t flags = env->pregs[SR_CCS];
1072
	uint32_t flags = env->pregs[PR_CCS];
1073 1073
	int c_set;
1074 1074

  
1075 1075
	c_set = !!(flags & C_FLAG);
......
1077 1077
	RETURN();
1078 1078
}
1079 1079
void OPPROTO op_tst_cc_cs (void) {
1080
	uint32_t flags = env->pregs[SR_CCS];
1080
	uint32_t flags = env->pregs[PR_CCS];
1081 1081
	int c_set;
1082 1082

  
1083 1083
	c_set = !!(flags & C_FLAG);
......
1086 1086
}
1087 1087

  
1088 1088
void OPPROTO op_tst_cc_vc (void) {
1089
	uint32_t flags = env->pregs[SR_CCS];
1089
	uint32_t flags = env->pregs[PR_CCS];
1090 1090
	int v_set;
1091 1091

  
1092 1092
	v_set = !!(flags & V_FLAG);
......
1094 1094
	RETURN();
1095 1095
}
1096 1096
void OPPROTO op_tst_cc_vs (void) {
1097
	uint32_t flags = env->pregs[SR_CCS];
1097
	uint32_t flags = env->pregs[PR_CCS];
1098 1098
	int v_set;
1099 1099

  
1100 1100
	v_set = !!(flags & V_FLAG);
......
1102 1102
	RETURN();
1103 1103
}
1104 1104
void OPPROTO op_tst_cc_pl (void) {
1105
	uint32_t flags = env->pregs[SR_CCS];
1105
	uint32_t flags = env->pregs[PR_CCS];
1106 1106
	int n_set;
1107 1107

  
1108 1108
	n_set = !!(flags & N_FLAG);
......
1115 1115
}
1116 1116

  
1117 1117
void OPPROTO op_tst_cc_mi (void) {
1118
	uint32_t flags = env->pregs[SR_CCS];
1118
	uint32_t flags = env->pregs[PR_CCS];
1119 1119
	int n_set;
1120 1120

  
1121 1121
	n_set = !!(flags & N_FLAG);
......
1128 1128
}
1129 1129

  
1130 1130
void OPPROTO op_tst_cc_ls (void) {
1131
	uint32_t flags = env->pregs[SR_CCS];
1131
	uint32_t flags = env->pregs[PR_CCS];
1132 1132
	int c_set;
1133 1133
	int z_set;
1134 1134

  
......
1138 1138
	RETURN();
1139 1139
}
1140 1140
void OPPROTO op_tst_cc_hi (void) {
1141
	uint32_t flags = env->pregs[SR_CCS];
1141
	uint32_t flags = env->pregs[PR_CCS];
1142 1142
	int z_set;
1143 1143
	int c_set;
1144 1144

  
......
1150 1150
}
1151 1151

  
1152 1152
void OPPROTO op_tst_cc_ge (void) {
1153
	uint32_t flags = env->pregs[SR_CCS];
1153
	uint32_t flags = env->pregs[PR_CCS];
1154 1154
	int n_set;
1155 1155
	int v_set;
1156 1156

  
......
1166 1166
}
1167 1167

  
1168 1168
void OPPROTO op_tst_cc_lt (void) {
1169
	uint32_t flags = env->pregs[SR_CCS];
1169
	uint32_t flags = env->pregs[PR_CCS];
1170 1170
	int n_set;
1171 1171
	int v_set;
1172 1172

  
......
1177 1177
}
1178 1178

  
1179 1179
void OPPROTO op_tst_cc_gt (void) {
1180
	uint32_t flags = env->pregs[SR_CCS];
1180
	uint32_t flags = env->pregs[PR_CCS];
1181 1181
	int n_set;
1182 1182
	int v_set;
1183 1183
	int z_set;
......
1191 1191
}
1192 1192

  
1193 1193
void OPPROTO op_tst_cc_le (void) {
1194
	uint32_t flags = env->pregs[SR_CCS];
1194
	uint32_t flags = env->pregs[PR_CCS];
1195 1195
	int n_set;
1196 1196
	int v_set;
1197 1197
	int z_set;
......
1204 1204
}
1205 1205

  
1206 1206
void OPPROTO op_tst_cc_p (void) {
1207
	uint32_t flags = env->pregs[SR_CCS];
1207
	uint32_t flags = env->pregs[PR_CCS];
1208 1208
	int p_set;
1209 1209

  
1210 1210
	p_set = !!(flags & P_FLAG);
......
1224 1224
/* this one is used on every alu op, optimize it!.  */
1225 1225
void OPPROTO op_goto_if_not_x (void)
1226 1226
{
1227
	if (env->pregs[SR_CCS] & X_FLAG)
1227
	if (env->pregs[PR_CCS] & X_FLAG)
1228 1228
		GOTO_LABEL_PARAM(1);
1229 1229
	RETURN();
1230 1230
}
b/target-cris/translate.c
882 882
	/* Fetch register operand,  */
883 883
	gen_movl_T0_reg[dc->op2]();
884 884
	gen_op_movl_T1_im(imm);
885
	crisv32_alu_op(dc, CC_OP_ADD, REG_ACR, 4);
885
	crisv32_alu_op(dc, CC_OP_ADD, R_ACR, 4);
886 886
	return 2;
887 887
}
888 888
static unsigned int dec_addq(DisasContext *dc)
......
1293 1293
	dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1294 1294
	gen_op_lsll_T0_im(dc->zzsize);
1295 1295
	gen_op_addl_T0_T1();
1296
	gen_movl_reg_T0[REG_ACR]();
1296
	gen_movl_reg_T0[R_ACR]();
1297 1297
	return 2;
1298 1298
}
1299 1299

  
......
1736 1736

  
1737 1737
	cris_cc_mask(dc, 0);
1738 1738
	insn_len = dec_prep_alu_m(dc, 1, memsize);
1739
	crisv32_alu_op(dc, CC_OP_ADD, REG_ACR, 4);
1739
	crisv32_alu_op(dc, CC_OP_ADD, R_ACR, 4);
1740 1740
	do_postinc(dc, memsize);
1741 1741
	return insn_len;
1742 1742
}
......
2352 2352
		if (!dc->flagx_live
2353 2353
		    || (dc->flagx_live &&
2354 2354
			!(dc->cc_op == CC_OP_FLAGS && dc->flags_x))) {
2355
			gen_movl_T0_preg[SR_CCS]();
2355
			gen_movl_T0_preg[PR_CCS]();
2356 2356
			gen_op_andl_T0_im(~X_FLAG);
2357
			gen_movl_preg_T0[SR_CCS]();
2357
			gen_movl_preg_T0[PR_CCS]();
2358 2358
			dc->flagx_live = 1;
2359 2359
			dc->flags_x = 0;
2360 2360
		}
......
2453 2453
	cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
2454 2454
		    "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n"
2455 2455
		    "debug=%x %x %x\n",
2456
		    env->pc, env->pregs[SR_CCS], env->btaken, env->btarget,
2456
		    env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
2457 2457
		    env->cc_op,
2458 2458
		    env->cc_src, env->cc_dest, env->cc_result, env->cc_mask,
2459 2459
		    env->debug1, env->debug2, env->debug3);
......
2469 2469
		if ((i + 1) % 4 == 0)
2470 2470
			cpu_fprintf(f, "\n");
2471 2471
	}
2472
	srs = env->pregs[SR_SRS];
2472
	srs = env->pregs[PR_SRS];
2473 2473
	cpu_fprintf(f, "\nsupport function regs bank %d:\n", srs);
2474 2474
	if (srs < 256) {
2475 2475
		for (i = 0; i < 16; i++) {

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