Revision 9004627f target-cris/translate.c

b/target-cris/translate.c
882 882
	/* Fetch register operand,  */
883 883
	gen_movl_T0_reg[dc->op2]();
884 884
	gen_op_movl_T1_im(imm);
885
	crisv32_alu_op(dc, CC_OP_ADD, REG_ACR, 4);
885
	crisv32_alu_op(dc, CC_OP_ADD, R_ACR, 4);
886 886
	return 2;
887 887
}
888 888
static unsigned int dec_addq(DisasContext *dc)
......
1293 1293
	dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1294 1294
	gen_op_lsll_T0_im(dc->zzsize);
1295 1295
	gen_op_addl_T0_T1();
1296
	gen_movl_reg_T0[REG_ACR]();
1296
	gen_movl_reg_T0[R_ACR]();
1297 1297
	return 2;
1298 1298
}
1299 1299

  
......
1736 1736

  
1737 1737
	cris_cc_mask(dc, 0);
1738 1738
	insn_len = dec_prep_alu_m(dc, 1, memsize);
1739
	crisv32_alu_op(dc, CC_OP_ADD, REG_ACR, 4);
1739
	crisv32_alu_op(dc, CC_OP_ADD, R_ACR, 4);
1740 1740
	do_postinc(dc, memsize);
1741 1741
	return insn_len;
1742 1742
}
......
2352 2352
		if (!dc->flagx_live
2353 2353
		    || (dc->flagx_live &&
2354 2354
			!(dc->cc_op == CC_OP_FLAGS && dc->flags_x))) {
2355
			gen_movl_T0_preg[SR_CCS]();
2355
			gen_movl_T0_preg[PR_CCS]();
2356 2356
			gen_op_andl_T0_im(~X_FLAG);
2357
			gen_movl_preg_T0[SR_CCS]();
2357
			gen_movl_preg_T0[PR_CCS]();
2358 2358
			dc->flagx_live = 1;
2359 2359
			dc->flags_x = 0;
2360 2360
		}
......
2453 2453
	cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
2454 2454
		    "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n"
2455 2455
		    "debug=%x %x %x\n",
2456
		    env->pc, env->pregs[SR_CCS], env->btaken, env->btarget,
2456
		    env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
2457 2457
		    env->cc_op,
2458 2458
		    env->cc_src, env->cc_dest, env->cc_result, env->cc_mask,
2459 2459
		    env->debug1, env->debug2, env->debug3);
......
2469 2469
		if ((i + 1) % 4 == 0)
2470 2470
			cpu_fprintf(f, "\n");
2471 2471
	}
2472
	srs = env->pregs[SR_SRS];
2472
	srs = env->pregs[PR_SRS];
2473 2473
	cpu_fprintf(f, "\nsupport function regs bank %d:\n", srs);
2474 2474
	if (srs < 256) {
2475 2475
		for (i = 0; i < 16; i++) {

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