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| 1 | 7a3f1944 | bellard | /*
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| 2 | 7a3f1944 | bellard | SPARC micro operations
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| 3 | 7a3f1944 | bellard | |
| 4 | 7a3f1944 | bellard | Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
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| 5 | 7a3f1944 | bellard | |
| 6 | 7a3f1944 | bellard | This library is free software; you can redistribute it and/or
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| 7 | 7a3f1944 | bellard | modify it under the terms of the GNU Lesser General Public
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| 8 | 7a3f1944 | bellard | License as published by the Free Software Foundation; either
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| 9 | 7a3f1944 | bellard | version 2 of the License, or (at your option) any later version.
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| 10 | 7a3f1944 | bellard | |
| 11 | 7a3f1944 | bellard | This library is distributed in the hope that it will be useful,
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| 12 | 7a3f1944 | bellard | but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 13 | 7a3f1944 | bellard | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 14 | 7a3f1944 | bellard | Lesser General Public License for more details.
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| 15 | 7a3f1944 | bellard | |
| 16 | 7a3f1944 | bellard | You should have received a copy of the GNU Lesser General Public
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| 17 | 7a3f1944 | bellard | License along with this library; if not, write to the Free Software
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| 18 | 7a3f1944 | bellard | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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| 19 | 7a3f1944 | bellard | */
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| 20 | 7a3f1944 | bellard | |
| 21 | 7a3f1944 | bellard | #include "exec.h" |
| 22 | 7a3f1944 | bellard | |
| 23 | cf495bcf | bellard | /*XXX*/
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| 24 | 7a3f1944 | bellard | #define REGNAME g0
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| 25 | 7a3f1944 | bellard | #define REG (env->gregs[0]) |
| 26 | 7a3f1944 | bellard | #include "op_template.h" |
| 27 | 7a3f1944 | bellard | #define REGNAME g1
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| 28 | 7a3f1944 | bellard | #define REG (env->gregs[1]) |
| 29 | 7a3f1944 | bellard | #include "op_template.h" |
| 30 | 7a3f1944 | bellard | #define REGNAME g2
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| 31 | 7a3f1944 | bellard | #define REG (env->gregs[2]) |
| 32 | 7a3f1944 | bellard | #include "op_template.h" |
| 33 | 7a3f1944 | bellard | #define REGNAME g3
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| 34 | 7a3f1944 | bellard | #define REG (env->gregs[3]) |
| 35 | 7a3f1944 | bellard | #include "op_template.h" |
| 36 | 7a3f1944 | bellard | #define REGNAME g4
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| 37 | 7a3f1944 | bellard | #define REG (env->gregs[4]) |
| 38 | 7a3f1944 | bellard | #include "op_template.h" |
| 39 | 7a3f1944 | bellard | #define REGNAME g5
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| 40 | 7a3f1944 | bellard | #define REG (env->gregs[5]) |
| 41 | 7a3f1944 | bellard | #include "op_template.h" |
| 42 | 7a3f1944 | bellard | #define REGNAME g6
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| 43 | 7a3f1944 | bellard | #define REG (env->gregs[6]) |
| 44 | 7a3f1944 | bellard | #include "op_template.h" |
| 45 | 7a3f1944 | bellard | #define REGNAME g7
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| 46 | 7a3f1944 | bellard | #define REG (env->gregs[7]) |
| 47 | 7a3f1944 | bellard | #include "op_template.h" |
| 48 | 7a3f1944 | bellard | #define REGNAME i0
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| 49 | 3475187d | bellard | #define REG (REGWPTR[16]) |
| 50 | 7a3f1944 | bellard | #include "op_template.h" |
| 51 | 7a3f1944 | bellard | #define REGNAME i1
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| 52 | 3475187d | bellard | #define REG (REGWPTR[17]) |
| 53 | 7a3f1944 | bellard | #include "op_template.h" |
| 54 | 7a3f1944 | bellard | #define REGNAME i2
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| 55 | 3475187d | bellard | #define REG (REGWPTR[18]) |
| 56 | 7a3f1944 | bellard | #include "op_template.h" |
| 57 | 7a3f1944 | bellard | #define REGNAME i3
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| 58 | 3475187d | bellard | #define REG (REGWPTR[19]) |
| 59 | 7a3f1944 | bellard | #include "op_template.h" |
| 60 | 7a3f1944 | bellard | #define REGNAME i4
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| 61 | 3475187d | bellard | #define REG (REGWPTR[20]) |
| 62 | 7a3f1944 | bellard | #include "op_template.h" |
| 63 | 7a3f1944 | bellard | #define REGNAME i5
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| 64 | 3475187d | bellard | #define REG (REGWPTR[21]) |
| 65 | 7a3f1944 | bellard | #include "op_template.h" |
| 66 | 7a3f1944 | bellard | #define REGNAME i6
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| 67 | 3475187d | bellard | #define REG (REGWPTR[22]) |
| 68 | 7a3f1944 | bellard | #include "op_template.h" |
| 69 | 7a3f1944 | bellard | #define REGNAME i7
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| 70 | 3475187d | bellard | #define REG (REGWPTR[23]) |
| 71 | 7a3f1944 | bellard | #include "op_template.h" |
| 72 | 7a3f1944 | bellard | #define REGNAME l0
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| 73 | 3475187d | bellard | #define REG (REGWPTR[8]) |
| 74 | 7a3f1944 | bellard | #include "op_template.h" |
| 75 | 7a3f1944 | bellard | #define REGNAME l1
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| 76 | 3475187d | bellard | #define REG (REGWPTR[9]) |
| 77 | 7a3f1944 | bellard | #include "op_template.h" |
| 78 | 7a3f1944 | bellard | #define REGNAME l2
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| 79 | 3475187d | bellard | #define REG (REGWPTR[10]) |
| 80 | 7a3f1944 | bellard | #include "op_template.h" |
| 81 | 7a3f1944 | bellard | #define REGNAME l3
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| 82 | 3475187d | bellard | #define REG (REGWPTR[11]) |
| 83 | 7a3f1944 | bellard | #include "op_template.h" |
| 84 | 7a3f1944 | bellard | #define REGNAME l4
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| 85 | 3475187d | bellard | #define REG (REGWPTR[12]) |
| 86 | 7a3f1944 | bellard | #include "op_template.h" |
| 87 | 7a3f1944 | bellard | #define REGNAME l5
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| 88 | 3475187d | bellard | #define REG (REGWPTR[13]) |
| 89 | 7a3f1944 | bellard | #include "op_template.h" |
| 90 | 7a3f1944 | bellard | #define REGNAME l6
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| 91 | 3475187d | bellard | #define REG (REGWPTR[14]) |
| 92 | 7a3f1944 | bellard | #include "op_template.h" |
| 93 | 7a3f1944 | bellard | #define REGNAME l7
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| 94 | 3475187d | bellard | #define REG (REGWPTR[15]) |
| 95 | 7a3f1944 | bellard | #include "op_template.h" |
| 96 | 7a3f1944 | bellard | #define REGNAME o0
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| 97 | 3475187d | bellard | #define REG (REGWPTR[0]) |
| 98 | 7a3f1944 | bellard | #include "op_template.h" |
| 99 | 7a3f1944 | bellard | #define REGNAME o1
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| 100 | 3475187d | bellard | #define REG (REGWPTR[1]) |
| 101 | 7a3f1944 | bellard | #include "op_template.h" |
| 102 | 7a3f1944 | bellard | #define REGNAME o2
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| 103 | 3475187d | bellard | #define REG (REGWPTR[2]) |
| 104 | 7a3f1944 | bellard | #include "op_template.h" |
| 105 | 7a3f1944 | bellard | #define REGNAME o3
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| 106 | 3475187d | bellard | #define REG (REGWPTR[3]) |
| 107 | 7a3f1944 | bellard | #include "op_template.h" |
| 108 | 7a3f1944 | bellard | #define REGNAME o4
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| 109 | 3475187d | bellard | #define REG (REGWPTR[4]) |
| 110 | 7a3f1944 | bellard | #include "op_template.h" |
| 111 | 7a3f1944 | bellard | #define REGNAME o5
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| 112 | 3475187d | bellard | #define REG (REGWPTR[5]) |
| 113 | 7a3f1944 | bellard | #include "op_template.h" |
| 114 | 7a3f1944 | bellard | #define REGNAME o6
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| 115 | 3475187d | bellard | #define REG (REGWPTR[6]) |
| 116 | 7a3f1944 | bellard | #include "op_template.h" |
| 117 | 7a3f1944 | bellard | #define REGNAME o7
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| 118 | 3475187d | bellard | #define REG (REGWPTR[7]) |
| 119 | 7a3f1944 | bellard | #include "op_template.h" |
| 120 | e8af50a3 | bellard | |
| 121 | e8af50a3 | bellard | #define REGNAME f0
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| 122 | e8af50a3 | bellard | #define REG (env->fpr[0]) |
| 123 | e8af50a3 | bellard | #include "fop_template.h" |
| 124 | e8af50a3 | bellard | #define REGNAME f1
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| 125 | e8af50a3 | bellard | #define REG (env->fpr[1]) |
| 126 | e8af50a3 | bellard | #include "fop_template.h" |
| 127 | e8af50a3 | bellard | #define REGNAME f2
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| 128 | e8af50a3 | bellard | #define REG (env->fpr[2]) |
| 129 | e8af50a3 | bellard | #include "fop_template.h" |
| 130 | e8af50a3 | bellard | #define REGNAME f3
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| 131 | e8af50a3 | bellard | #define REG (env->fpr[3]) |
| 132 | e8af50a3 | bellard | #include "fop_template.h" |
| 133 | e8af50a3 | bellard | #define REGNAME f4
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| 134 | e8af50a3 | bellard | #define REG (env->fpr[4]) |
| 135 | e8af50a3 | bellard | #include "fop_template.h" |
| 136 | e8af50a3 | bellard | #define REGNAME f5
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| 137 | e8af50a3 | bellard | #define REG (env->fpr[5]) |
| 138 | e8af50a3 | bellard | #include "fop_template.h" |
| 139 | e8af50a3 | bellard | #define REGNAME f6
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| 140 | e8af50a3 | bellard | #define REG (env->fpr[6]) |
| 141 | e8af50a3 | bellard | #include "fop_template.h" |
| 142 | e8af50a3 | bellard | #define REGNAME f7
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| 143 | e8af50a3 | bellard | #define REG (env->fpr[7]) |
| 144 | e8af50a3 | bellard | #include "fop_template.h" |
| 145 | e8af50a3 | bellard | #define REGNAME f8
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| 146 | e8af50a3 | bellard | #define REG (env->fpr[8]) |
| 147 | e8af50a3 | bellard | #include "fop_template.h" |
| 148 | e8af50a3 | bellard | #define REGNAME f9
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| 149 | e8af50a3 | bellard | #define REG (env->fpr[9]) |
| 150 | e8af50a3 | bellard | #include "fop_template.h" |
| 151 | e8af50a3 | bellard | #define REGNAME f10
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| 152 | e8af50a3 | bellard | #define REG (env->fpr[10]) |
| 153 | e8af50a3 | bellard | #include "fop_template.h" |
| 154 | e8af50a3 | bellard | #define REGNAME f11
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| 155 | e8af50a3 | bellard | #define REG (env->fpr[11]) |
| 156 | e8af50a3 | bellard | #include "fop_template.h" |
| 157 | e8af50a3 | bellard | #define REGNAME f12
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| 158 | e8af50a3 | bellard | #define REG (env->fpr[12]) |
| 159 | e8af50a3 | bellard | #include "fop_template.h" |
| 160 | e8af50a3 | bellard | #define REGNAME f13
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| 161 | e8af50a3 | bellard | #define REG (env->fpr[13]) |
| 162 | e8af50a3 | bellard | #include "fop_template.h" |
| 163 | e8af50a3 | bellard | #define REGNAME f14
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| 164 | e8af50a3 | bellard | #define REG (env->fpr[14]) |
| 165 | e8af50a3 | bellard | #include "fop_template.h" |
| 166 | e8af50a3 | bellard | #define REGNAME f15
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| 167 | e8af50a3 | bellard | #define REG (env->fpr[15]) |
| 168 | e8af50a3 | bellard | #include "fop_template.h" |
| 169 | e8af50a3 | bellard | #define REGNAME f16
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| 170 | e8af50a3 | bellard | #define REG (env->fpr[16]) |
| 171 | e8af50a3 | bellard | #include "fop_template.h" |
| 172 | e8af50a3 | bellard | #define REGNAME f17
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| 173 | e8af50a3 | bellard | #define REG (env->fpr[17]) |
| 174 | e8af50a3 | bellard | #include "fop_template.h" |
| 175 | e8af50a3 | bellard | #define REGNAME f18
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| 176 | e8af50a3 | bellard | #define REG (env->fpr[18]) |
| 177 | e8af50a3 | bellard | #include "fop_template.h" |
| 178 | e8af50a3 | bellard | #define REGNAME f19
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| 179 | e8af50a3 | bellard | #define REG (env->fpr[19]) |
| 180 | e8af50a3 | bellard | #include "fop_template.h" |
| 181 | e8af50a3 | bellard | #define REGNAME f20
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| 182 | e8af50a3 | bellard | #define REG (env->fpr[20]) |
| 183 | e8af50a3 | bellard | #include "fop_template.h" |
| 184 | e8af50a3 | bellard | #define REGNAME f21
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| 185 | e8af50a3 | bellard | #define REG (env->fpr[21]) |
| 186 | e8af50a3 | bellard | #include "fop_template.h" |
| 187 | e8af50a3 | bellard | #define REGNAME f22
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| 188 | e8af50a3 | bellard | #define REG (env->fpr[22]) |
| 189 | e8af50a3 | bellard | #include "fop_template.h" |
| 190 | e8af50a3 | bellard | #define REGNAME f23
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| 191 | e8af50a3 | bellard | #define REG (env->fpr[23]) |
| 192 | e8af50a3 | bellard | #include "fop_template.h" |
| 193 | e8af50a3 | bellard | #define REGNAME f24
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| 194 | e8af50a3 | bellard | #define REG (env->fpr[24]) |
| 195 | e8af50a3 | bellard | #include "fop_template.h" |
| 196 | e8af50a3 | bellard | #define REGNAME f25
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| 197 | e8af50a3 | bellard | #define REG (env->fpr[25]) |
| 198 | e8af50a3 | bellard | #include "fop_template.h" |
| 199 | e8af50a3 | bellard | #define REGNAME f26
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| 200 | e8af50a3 | bellard | #define REG (env->fpr[26]) |
| 201 | e8af50a3 | bellard | #include "fop_template.h" |
| 202 | e8af50a3 | bellard | #define REGNAME f27
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| 203 | e8af50a3 | bellard | #define REG (env->fpr[27]) |
| 204 | e8af50a3 | bellard | #include "fop_template.h" |
| 205 | e8af50a3 | bellard | #define REGNAME f28
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| 206 | e8af50a3 | bellard | #define REG (env->fpr[28]) |
| 207 | e8af50a3 | bellard | #include "fop_template.h" |
| 208 | e8af50a3 | bellard | #define REGNAME f29
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| 209 | e8af50a3 | bellard | #define REG (env->fpr[29]) |
| 210 | e8af50a3 | bellard | #include "fop_template.h" |
| 211 | e8af50a3 | bellard | #define REGNAME f30
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| 212 | e8af50a3 | bellard | #define REG (env->fpr[30]) |
| 213 | e8af50a3 | bellard | #include "fop_template.h" |
| 214 | e8af50a3 | bellard | #define REGNAME f31
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| 215 | e8af50a3 | bellard | #define REG (env->fpr[31]) |
| 216 | e8af50a3 | bellard | #include "fop_template.h" |
| 217 | e8af50a3 | bellard | |
| 218 | 3475187d | bellard | #ifdef TARGET_SPARC64
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| 219 | 3475187d | bellard | #define REGNAME f32
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| 220 | 3475187d | bellard | #define REG (env->fpr[32]) |
| 221 | 3475187d | bellard | #include "fop_template.h" |
| 222 | 3475187d | bellard | #define REGNAME f34
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| 223 | 3475187d | bellard | #define REG (env->fpr[34]) |
| 224 | 3475187d | bellard | #include "fop_template.h" |
| 225 | 3475187d | bellard | #define REGNAME f36
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| 226 | 3475187d | bellard | #define REG (env->fpr[36]) |
| 227 | 3475187d | bellard | #include "fop_template.h" |
| 228 | 3475187d | bellard | #define REGNAME f38
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| 229 | 3475187d | bellard | #define REG (env->fpr[38]) |
| 230 | 3475187d | bellard | #include "fop_template.h" |
| 231 | 3475187d | bellard | #define REGNAME f40
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| 232 | 3475187d | bellard | #define REG (env->fpr[40]) |
| 233 | 3475187d | bellard | #include "fop_template.h" |
| 234 | 3475187d | bellard | #define REGNAME f42
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| 235 | 3475187d | bellard | #define REG (env->fpr[42]) |
| 236 | 3475187d | bellard | #include "fop_template.h" |
| 237 | 3475187d | bellard | #define REGNAME f44
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| 238 | 3475187d | bellard | #define REG (env->fpr[44]) |
| 239 | 3475187d | bellard | #include "fop_template.h" |
| 240 | 3475187d | bellard | #define REGNAME f46
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| 241 | 3475187d | bellard | #define REG (env->fpr[46]) |
| 242 | 3475187d | bellard | #include "fop_template.h" |
| 243 | 3475187d | bellard | #define REGNAME f48
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| 244 | 3475187d | bellard | #define REG (env->fpr[47]) |
| 245 | 3475187d | bellard | #include "fop_template.h" |
| 246 | 3475187d | bellard | #define REGNAME f50
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| 247 | 3475187d | bellard | #define REG (env->fpr[50]) |
| 248 | 3475187d | bellard | #include "fop_template.h" |
| 249 | 3475187d | bellard | #define REGNAME f52
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| 250 | 3475187d | bellard | #define REG (env->fpr[52]) |
| 251 | 3475187d | bellard | #include "fop_template.h" |
| 252 | 3475187d | bellard | #define REGNAME f54
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| 253 | 3475187d | bellard | #define REG (env->fpr[54]) |
| 254 | 3475187d | bellard | #include "fop_template.h" |
| 255 | 3475187d | bellard | #define REGNAME f56
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| 256 | 3475187d | bellard | #define REG (env->fpr[56]) |
| 257 | 3475187d | bellard | #include "fop_template.h" |
| 258 | 3475187d | bellard | #define REGNAME f58
|
| 259 | 3475187d | bellard | #define REG (env->fpr[58]) |
| 260 | 3475187d | bellard | #include "fop_template.h" |
| 261 | 3475187d | bellard | #define REGNAME f60
|
| 262 | 3475187d | bellard | #define REG (env->fpr[60]) |
| 263 | 3475187d | bellard | #include "fop_template.h" |
| 264 | 3475187d | bellard | #define REGNAME f62
|
| 265 | 3475187d | bellard | #define REG (env->fpr[62]) |
| 266 | 3475187d | bellard | #include "fop_template.h" |
| 267 | 3475187d | bellard | #endif
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| 268 | 3475187d | bellard | |
| 269 | 3475187d | bellard | #ifdef TARGET_SPARC64
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| 270 | 3475187d | bellard | #ifdef WORDS_BIGENDIAN
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| 271 | 3475187d | bellard | typedef union UREG64 { |
| 272 | 3475187d | bellard | struct { uint16_t v3, v2, v1, v0; } w;
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| 273 | 3475187d | bellard | struct { uint32_t v1, v0; } l;
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| 274 | 3475187d | bellard | uint64_t q; |
| 275 | 3475187d | bellard | } UREG64; |
| 276 | 3475187d | bellard | #else
|
| 277 | 3475187d | bellard | typedef union UREG64 { |
| 278 | 3475187d | bellard | struct { uint16_t v0, v1, v2, v3; } w;
|
| 279 | 3475187d | bellard | struct { uint32_t v0, v1; } l;
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| 280 | 3475187d | bellard | uint64_t q; |
| 281 | 3475187d | bellard | } UREG64; |
| 282 | 3475187d | bellard | #endif
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| 283 | 3475187d | bellard | |
| 284 | 3475187d | bellard | #define PARAMQ1 \
|
| 285 | 3475187d | bellard | ({\
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| 286 | 3475187d | bellard | UREG64 __p;\ |
| 287 | 3475187d | bellard | __p.l.v1 = PARAM1;\ |
| 288 | 3475187d | bellard | __p.l.v0 = PARAM2;\ |
| 289 | 3475187d | bellard | __p.q;\ |
| 290 | 5fafdf24 | ths | }) |
| 291 | 3475187d | bellard | |
| 292 | 3475187d | bellard | void OPPROTO op_movq_T0_im64(void) |
| 293 | 3475187d | bellard | {
|
| 294 | 3475187d | bellard | T0 = PARAMQ1; |
| 295 | 3475187d | bellard | } |
| 296 | 3475187d | bellard | |
| 297 | 3475187d | bellard | void OPPROTO op_movq_T1_im64(void) |
| 298 | 3475187d | bellard | {
|
| 299 | 3475187d | bellard | T1 = PARAMQ1; |
| 300 | 3475187d | bellard | } |
| 301 | 3475187d | bellard | |
| 302 | 3475187d | bellard | #define XFLAG_SET(x) ((env->xcc&x)?1:0) |
| 303 | 3475187d | bellard | |
| 304 | 3475187d | bellard | #else
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| 305 | 7a3f1944 | bellard | #define EIP (env->pc)
|
| 306 | 3475187d | bellard | #endif
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| 307 | 7a3f1944 | bellard | |
| 308 | af7bf89b | bellard | #define FLAG_SET(x) ((env->psr&x)?1:0) |
| 309 | cf495bcf | bellard | |
| 310 | 7a3f1944 | bellard | void OPPROTO op_movl_T0_0(void) |
| 311 | 7a3f1944 | bellard | {
|
| 312 | cf495bcf | bellard | T0 = 0;
|
| 313 | 7a3f1944 | bellard | } |
| 314 | 7a3f1944 | bellard | |
| 315 | 7a3f1944 | bellard | void OPPROTO op_movl_T0_im(void) |
| 316 | 7a3f1944 | bellard | {
|
| 317 | 3475187d | bellard | T0 = (uint32_t)PARAM1; |
| 318 | 7a3f1944 | bellard | } |
| 319 | 7a3f1944 | bellard | |
| 320 | 7a3f1944 | bellard | void OPPROTO op_movl_T1_im(void) |
| 321 | 7a3f1944 | bellard | {
|
| 322 | 3475187d | bellard | T1 = (uint32_t)PARAM1; |
| 323 | 7a3f1944 | bellard | } |
| 324 | 7a3f1944 | bellard | |
| 325 | 7a3f1944 | bellard | void OPPROTO op_movl_T2_im(void) |
| 326 | 7a3f1944 | bellard | {
|
| 327 | 3475187d | bellard | T2 = (uint32_t)PARAM1; |
| 328 | 3475187d | bellard | } |
| 329 | 3475187d | bellard | |
| 330 | 3475187d | bellard | void OPPROTO op_movl_T0_sim(void) |
| 331 | 3475187d | bellard | {
|
| 332 | 3475187d | bellard | T0 = (int32_t)PARAM1; |
| 333 | 3475187d | bellard | } |
| 334 | 3475187d | bellard | |
| 335 | 3475187d | bellard | void OPPROTO op_movl_T1_sim(void) |
| 336 | 3475187d | bellard | {
|
| 337 | 3475187d | bellard | T1 = (int32_t)PARAM1; |
| 338 | 3475187d | bellard | } |
| 339 | 3475187d | bellard | |
| 340 | 3475187d | bellard | void OPPROTO op_movl_T2_sim(void) |
| 341 | 3475187d | bellard | {
|
| 342 | 3475187d | bellard | T2 = (int32_t)PARAM1; |
| 343 | 3475187d | bellard | } |
| 344 | 3475187d | bellard | |
| 345 | 3475187d | bellard | void OPPROTO op_movl_T0_env(void) |
| 346 | 3475187d | bellard | {
|
| 347 | 3475187d | bellard | T0 = *(uint32_t *)((char *)env + PARAM1);
|
| 348 | 3475187d | bellard | } |
| 349 | 3475187d | bellard | |
| 350 | 3475187d | bellard | void OPPROTO op_movl_env_T0(void) |
| 351 | 3475187d | bellard | {
|
| 352 | 3475187d | bellard | *(uint32_t *)((char *)env + PARAM1) = T0;
|
| 353 | 3475187d | bellard | } |
| 354 | 3475187d | bellard | |
| 355 | 3475187d | bellard | void OPPROTO op_movtl_T0_env(void) |
| 356 | 3475187d | bellard | {
|
| 357 | 3475187d | bellard | T0 = *(target_ulong *)((char *)env + PARAM1);
|
| 358 | 3475187d | bellard | } |
| 359 | 3475187d | bellard | |
| 360 | 3475187d | bellard | void OPPROTO op_movtl_env_T0(void) |
| 361 | 3475187d | bellard | {
|
| 362 | 3475187d | bellard | *(target_ulong *)((char *)env + PARAM1) = T0;
|
| 363 | 7a3f1944 | bellard | } |
| 364 | 7a3f1944 | bellard | |
| 365 | af7bf89b | bellard | void OPPROTO op_add_T1_T0(void) |
| 366 | 7a3f1944 | bellard | {
|
| 367 | af7bf89b | bellard | T0 += T1; |
| 368 | 7a3f1944 | bellard | } |
| 369 | 7a3f1944 | bellard | |
| 370 | af7bf89b | bellard | void OPPROTO op_add_T1_T0_cc(void) |
| 371 | 7a3f1944 | bellard | {
|
| 372 | af7bf89b | bellard | target_ulong src1; |
| 373 | 7a3f1944 | bellard | |
| 374 | af7bf89b | bellard | src1 = T0; |
| 375 | af7bf89b | bellard | T0 += T1; |
| 376 | af7bf89b | bellard | env->psr = 0;
|
| 377 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
| 378 | 3475187d | bellard | if (!(T0 & 0xffffffff)) |
| 379 | 0f8a249a | blueswir1 | env->psr |= PSR_ZERO; |
| 380 | 3475187d | bellard | if ((int32_t) T0 < 0) |
| 381 | 0f8a249a | blueswir1 | env->psr |= PSR_NEG; |
| 382 | bb3911a6 | bellard | if ((T0 & 0xffffffff) < (src1 & 0xffffffff)) |
| 383 | 0f8a249a | blueswir1 | env->psr |= PSR_CARRY; |
| 384 | 3475187d | bellard | if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) & |
| 385 | 0f8a249a | blueswir1 | ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31)) |
| 386 | 0f8a249a | blueswir1 | env->psr |= PSR_OVF; |
| 387 | 3475187d | bellard | |
| 388 | 3475187d | bellard | env->xcc = 0;
|
| 389 | 3475187d | bellard | if (!T0)
|
| 390 | 0f8a249a | blueswir1 | env->xcc |= PSR_ZERO; |
| 391 | 3475187d | bellard | if ((int64_t) T0 < 0) |
| 392 | 0f8a249a | blueswir1 | env->xcc |= PSR_NEG; |
| 393 | 3475187d | bellard | if (T0 < src1)
|
| 394 | 0f8a249a | blueswir1 | env->xcc |= PSR_CARRY; |
| 395 | 3475187d | bellard | if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1ULL << 63)) |
| 396 | 0f8a249a | blueswir1 | env->xcc |= PSR_OVF; |
| 397 | 3475187d | bellard | #else
|
| 398 | af7bf89b | bellard | if (!T0)
|
| 399 | 0f8a249a | blueswir1 | env->psr |= PSR_ZERO; |
| 400 | af7bf89b | bellard | if ((int32_t) T0 < 0) |
| 401 | 0f8a249a | blueswir1 | env->psr |= PSR_NEG; |
| 402 | af7bf89b | bellard | if (T0 < src1)
|
| 403 | 0f8a249a | blueswir1 | env->psr |= PSR_CARRY; |
| 404 | af7bf89b | bellard | if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31)) |
| 405 | 0f8a249a | blueswir1 | env->psr |= PSR_OVF; |
| 406 | 3475187d | bellard | #endif
|
| 407 | af7bf89b | bellard | FORCE_RET(); |
| 408 | 7a3f1944 | bellard | } |
| 409 | 7a3f1944 | bellard | |
| 410 | af7bf89b | bellard | void OPPROTO op_addx_T1_T0(void) |
| 411 | 7a3f1944 | bellard | {
|
| 412 | af7bf89b | bellard | T0 += T1 + FLAG_SET(PSR_CARRY); |
| 413 | 7a3f1944 | bellard | } |
| 414 | 7a3f1944 | bellard | |
| 415 | af7bf89b | bellard | void OPPROTO op_addx_T1_T0_cc(void) |
| 416 | 7a3f1944 | bellard | {
|
| 417 | af7bf89b | bellard | target_ulong src1; |
| 418 | cf495bcf | bellard | src1 = T0; |
| 419 | b854608e | bellard | if (FLAG_SET(PSR_CARRY))
|
| 420 | b854608e | bellard | {
|
| 421 | b854608e | bellard | T0 += T1 + 1;
|
| 422 | b854608e | bellard | env->psr = 0;
|
| 423 | b854608e | bellard | #ifdef TARGET_SPARC64
|
| 424 | b854608e | bellard | if ((T0 & 0xffffffff) <= (src1 & 0xffffffff)) |
| 425 | b854608e | bellard | env->psr |= PSR_CARRY; |
| 426 | b854608e | bellard | env->xcc = 0;
|
| 427 | b854608e | bellard | if (T0 <= src1)
|
| 428 | b854608e | bellard | env->xcc |= PSR_CARRY; |
| 429 | b854608e | bellard | #else
|
| 430 | b854608e | bellard | if (T0 <= src1)
|
| 431 | b854608e | bellard | env->psr |= PSR_CARRY; |
| 432 | b854608e | bellard | #endif
|
| 433 | b854608e | bellard | } |
| 434 | b854608e | bellard | else
|
| 435 | b854608e | bellard | {
|
| 436 | b854608e | bellard | T0 += T1; |
| 437 | b854608e | bellard | env->psr = 0;
|
| 438 | b854608e | bellard | #ifdef TARGET_SPARC64
|
| 439 | b854608e | bellard | if ((T0 & 0xffffffff) < (src1 & 0xffffffff)) |
| 440 | b854608e | bellard | env->psr |= PSR_CARRY; |
| 441 | b854608e | bellard | env->xcc = 0;
|
| 442 | b854608e | bellard | if (T0 < src1)
|
| 443 | b854608e | bellard | env->xcc |= PSR_CARRY; |
| 444 | b854608e | bellard | #else
|
| 445 | b854608e | bellard | if (T0 < src1)
|
| 446 | b854608e | bellard | env->psr |= PSR_CARRY; |
| 447 | b854608e | bellard | #endif
|
| 448 | b854608e | bellard | } |
| 449 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
| 450 | 3475187d | bellard | if (!(T0 & 0xffffffff)) |
| 451 | 0f8a249a | blueswir1 | env->psr |= PSR_ZERO; |
| 452 | 3475187d | bellard | if ((int32_t) T0 < 0) |
| 453 | 0f8a249a | blueswir1 | env->psr |= PSR_NEG; |
| 454 | 3475187d | bellard | if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) & |
| 455 | 0f8a249a | blueswir1 | ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31)) |
| 456 | 0f8a249a | blueswir1 | env->psr |= PSR_OVF; |
| 457 | 3475187d | bellard | |
| 458 | 3475187d | bellard | if (!T0)
|
| 459 | 0f8a249a | blueswir1 | env->xcc |= PSR_ZERO; |
| 460 | 3475187d | bellard | if ((int64_t) T0 < 0) |
| 461 | 0f8a249a | blueswir1 | env->xcc |= PSR_NEG; |
| 462 | 3475187d | bellard | if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1ULL << 63)) |
| 463 | 0f8a249a | blueswir1 | env->xcc |= PSR_OVF; |
| 464 | 3475187d | bellard | #else
|
| 465 | cf495bcf | bellard | if (!T0)
|
| 466 | 0f8a249a | blueswir1 | env->psr |= PSR_ZERO; |
| 467 | af7bf89b | bellard | if ((int32_t) T0 < 0) |
| 468 | 0f8a249a | blueswir1 | env->psr |= PSR_NEG; |
| 469 | cf495bcf | bellard | if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31)) |
| 470 | 0f8a249a | blueswir1 | env->psr |= PSR_OVF; |
| 471 | 3475187d | bellard | #endif
|
| 472 | cf495bcf | bellard | FORCE_RET(); |
| 473 | 7a3f1944 | bellard | } |
| 474 | 7a3f1944 | bellard | |
| 475 | e32f879d | blueswir1 | void OPPROTO op_tadd_T1_T0_cc(void) |
| 476 | e32f879d | blueswir1 | {
|
| 477 | e32f879d | blueswir1 | target_ulong src1; |
| 478 | e32f879d | blueswir1 | |
| 479 | e32f879d | blueswir1 | src1 = T0; |
| 480 | e32f879d | blueswir1 | T0 += T1; |
| 481 | e32f879d | blueswir1 | env->psr = 0;
|
| 482 | e32f879d | blueswir1 | #ifdef TARGET_SPARC64
|
| 483 | e32f879d | blueswir1 | if (!(T0 & 0xffffffff)) |
| 484 | 0f8a249a | blueswir1 | env->psr |= PSR_ZERO; |
| 485 | e32f879d | blueswir1 | if ((int32_t) T0 < 0) |
| 486 | 0f8a249a | blueswir1 | env->psr |= PSR_NEG; |
| 487 | e32f879d | blueswir1 | if ((T0 & 0xffffffff) < (src1 & 0xffffffff)) |
| 488 | 0f8a249a | blueswir1 | env->psr |= PSR_CARRY; |
| 489 | e32f879d | blueswir1 | if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) & |
| 490 | 0f8a249a | blueswir1 | ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31)) |
| 491 | 0f8a249a | blueswir1 | env->psr |= PSR_OVF; |
| 492 | e32f879d | blueswir1 | if ((src1 & 0x03) || (T1 & 0x03)) |
| 493 | 0f8a249a | blueswir1 | env->psr |= PSR_OVF; |
| 494 | e32f879d | blueswir1 | |
| 495 | e32f879d | blueswir1 | env->xcc = 0;
|
| 496 | e32f879d | blueswir1 | if (!T0)
|
| 497 | 0f8a249a | blueswir1 | env->xcc |= PSR_ZERO; |
| 498 | e32f879d | blueswir1 | if ((int64_t) T0 < 0) |
| 499 | 0f8a249a | blueswir1 | env->xcc |= PSR_NEG; |
| 500 | e32f879d | blueswir1 | if (T0 < src1)
|
| 501 | 0f8a249a | blueswir1 | env->xcc |= PSR_CARRY; |
| 502 | e32f879d | blueswir1 | if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1ULL << 63)) |
| 503 | 0f8a249a | blueswir1 | env->xcc |= PSR_OVF; |
| 504 | e32f879d | blueswir1 | #else
|
| 505 | e32f879d | blueswir1 | if (!T0)
|
| 506 | 0f8a249a | blueswir1 | env->psr |= PSR_ZERO; |
| 507 | e32f879d | blueswir1 | if ((int32_t) T0 < 0) |
| 508 | 0f8a249a | blueswir1 | env->psr |= PSR_NEG; |
| 509 | e32f879d | blueswir1 | if (T0 < src1)
|
| 510 | 0f8a249a | blueswir1 | env->psr |= PSR_CARRY; |
| 511 | e32f879d | blueswir1 | if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31)) |
| 512 | 0f8a249a | blueswir1 | env->psr |= PSR_OVF; |
| 513 | e32f879d | blueswir1 | if ((src1 & 0x03) || (T1 & 0x03)) |
| 514 | 0f8a249a | blueswir1 | env->psr |= PSR_OVF; |
| 515 | e32f879d | blueswir1 | #endif
|
| 516 | e32f879d | blueswir1 | FORCE_RET(); |
| 517 | e32f879d | blueswir1 | } |
| 518 | e32f879d | blueswir1 | |
| 519 | e32f879d | blueswir1 | void OPPROTO op_tadd_T1_T0_ccTV(void) |
| 520 | e32f879d | blueswir1 | {
|
| 521 | e32f879d | blueswir1 | target_ulong src1; |
| 522 | e32f879d | blueswir1 | |
| 523 | d69d2ca9 | blueswir1 | if ((T0 & 0x03) || (T1 & 0x03)) { |
| 524 | e32f879d | blueswir1 | raise_exception(TT_TOVF); |
| 525 | d69d2ca9 | blueswir1 | FORCE_RET(); |
| 526 | d69d2ca9 | blueswir1 | return;
|
| 527 | d69d2ca9 | blueswir1 | } |
| 528 | e32f879d | blueswir1 | |
| 529 | e32f879d | blueswir1 | src1 = T0; |
| 530 | e32f879d | blueswir1 | T0 += T1; |
| 531 | e32f879d | blueswir1 | |
| 532 | e32f879d | blueswir1 | #ifdef TARGET_SPARC64
|
| 533 | e32f879d | blueswir1 | if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) & |
| 534 | 0f8a249a | blueswir1 | ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31)) |
| 535 | e32f879d | blueswir1 | raise_exception(TT_TOVF); |
| 536 | e32f879d | blueswir1 | #else
|
| 537 | 90251fb9 | blueswir1 | if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31)) |
| 538 | e32f879d | blueswir1 | raise_exception(TT_TOVF); |
| 539 | e32f879d | blueswir1 | #endif
|
| 540 | e32f879d | blueswir1 | |
| 541 | e32f879d | blueswir1 | env->psr = 0;
|
| 542 | e32f879d | blueswir1 | #ifdef TARGET_SPARC64
|
| 543 | e32f879d | blueswir1 | if (!(T0 & 0xffffffff)) |
| 544 | 0f8a249a | blueswir1 | env->psr |= PSR_ZERO; |
| 545 | e32f879d | blueswir1 | if ((int32_t) T0 < 0) |
| 546 | 0f8a249a | blueswir1 | env->psr |= PSR_NEG; |
| 547 | e32f879d | blueswir1 | if ((T0 & 0xffffffff) < (src1 & 0xffffffff)) |
| 548 | 0f8a249a | blueswir1 | env->psr |= PSR_CARRY; |
| 549 | e32f879d | blueswir1 | |
| 550 | e32f879d | blueswir1 | env->xcc = 0;
|
| 551 | e32f879d | blueswir1 | if (!T0)
|
| 552 | 0f8a249a | blueswir1 | env->xcc |= PSR_ZERO; |
| 553 | e32f879d | blueswir1 | if ((int64_t) T0 < 0) |
| 554 | 0f8a249a | blueswir1 | env->xcc |= PSR_NEG; |
| 555 | e32f879d | blueswir1 | if (T0 < src1)
|
| 556 | 0f8a249a | blueswir1 | env->xcc |= PSR_CARRY; |
| 557 | e32f879d | blueswir1 | #else
|
| 558 | e32f879d | blueswir1 | if (!T0)
|
| 559 | 0f8a249a | blueswir1 | env->psr |= PSR_ZERO; |
| 560 | e32f879d | blueswir1 | if ((int32_t) T0 < 0) |
| 561 | 0f8a249a | blueswir1 | env->psr |= PSR_NEG; |
| 562 | e32f879d | blueswir1 | if (T0 < src1)
|
| 563 | 0f8a249a | blueswir1 | env->psr |= PSR_CARRY; |
| 564 | e32f879d | blueswir1 | #endif
|
| 565 | e32f879d | blueswir1 | FORCE_RET(); |
| 566 | e32f879d | blueswir1 | } |
| 567 | e32f879d | blueswir1 | |
| 568 | cf495bcf | bellard | void OPPROTO op_sub_T1_T0(void) |
| 569 | 7a3f1944 | bellard | {
|
| 570 | cf495bcf | bellard | T0 -= T1; |
| 571 | 7a3f1944 | bellard | } |
| 572 | 7a3f1944 | bellard | |
| 573 | cf495bcf | bellard | void OPPROTO op_sub_T1_T0_cc(void) |
| 574 | 7a3f1944 | bellard | {
|
| 575 | af7bf89b | bellard | target_ulong src1; |
| 576 | cf495bcf | bellard | |
| 577 | cf495bcf | bellard | src1 = T0; |
| 578 | cf495bcf | bellard | T0 -= T1; |
| 579 | cf495bcf | bellard | env->psr = 0;
|
| 580 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
| 581 | 3475187d | bellard | if (!(T0 & 0xffffffff)) |
| 582 | 0f8a249a | blueswir1 | env->psr |= PSR_ZERO; |
| 583 | 3475187d | bellard | if ((int32_t) T0 < 0) |
| 584 | 0f8a249a | blueswir1 | env->psr |= PSR_NEG; |
| 585 | 83469015 | bellard | if ((src1 & 0xffffffff) < (T1 & 0xffffffff)) |
| 586 | 0f8a249a | blueswir1 | env->psr |= PSR_CARRY; |
| 587 | 3475187d | bellard | if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) & |
| 588 | 0f8a249a | blueswir1 | ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31)) |
| 589 | 0f8a249a | blueswir1 | env->psr |= PSR_OVF; |
| 590 | 3475187d | bellard | |
| 591 | 3475187d | bellard | env->xcc = 0;
|
| 592 | 3475187d | bellard | if (!T0)
|
| 593 | 0f8a249a | blueswir1 | env->xcc |= PSR_ZERO; |
| 594 | 3475187d | bellard | if ((int64_t) T0 < 0) |
| 595 | 0f8a249a | blueswir1 | env->xcc |= PSR_NEG; |
| 596 | bb3911a6 | bellard | if (src1 < T1)
|
| 597 | 0f8a249a | blueswir1 | env->xcc |= PSR_CARRY; |
| 598 | 3475187d | bellard | if (((src1 ^ T1) & (src1 ^ T0)) & (1ULL << 63)) |
| 599 | 0f8a249a | blueswir1 | env->xcc |= PSR_OVF; |
| 600 | 3475187d | bellard | #else
|
| 601 | cf495bcf | bellard | if (!T0)
|
| 602 | 0f8a249a | blueswir1 | env->psr |= PSR_ZERO; |
| 603 | af7bf89b | bellard | if ((int32_t) T0 < 0) |
| 604 | 0f8a249a | blueswir1 | env->psr |= PSR_NEG; |
| 605 | cf495bcf | bellard | if (src1 < T1)
|
| 606 | 0f8a249a | blueswir1 | env->psr |= PSR_CARRY; |
| 607 | cf495bcf | bellard | if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31)) |
| 608 | 0f8a249a | blueswir1 | env->psr |= PSR_OVF; |
| 609 | 3475187d | bellard | #endif
|
| 610 | af7bf89b | bellard | FORCE_RET(); |
| 611 | af7bf89b | bellard | } |
| 612 | af7bf89b | bellard | |
| 613 | af7bf89b | bellard | void OPPROTO op_subx_T1_T0(void) |
| 614 | af7bf89b | bellard | {
|
| 615 | af7bf89b | bellard | T0 -= T1 + FLAG_SET(PSR_CARRY); |
| 616 | af7bf89b | bellard | } |
| 617 | af7bf89b | bellard | |
| 618 | af7bf89b | bellard | void OPPROTO op_subx_T1_T0_cc(void) |
| 619 | af7bf89b | bellard | {
|
| 620 | af7bf89b | bellard | target_ulong src1; |
| 621 | af7bf89b | bellard | src1 = T0; |
| 622 | b854608e | bellard | if (FLAG_SET(PSR_CARRY))
|
| 623 | b854608e | bellard | {
|
| 624 | b854608e | bellard | T0 -= T1 + 1;
|
| 625 | b854608e | bellard | env->psr = 0;
|
| 626 | b854608e | bellard | #ifdef TARGET_SPARC64
|
| 627 | b854608e | bellard | if ((src1 & 0xffffffff) <= (T1 & 0xffffffff)) |
| 628 | b854608e | bellard | env->psr |= PSR_CARRY; |
| 629 | b854608e | bellard | env->xcc = 0;
|
| 630 | b854608e | bellard | if (src1 <= T1)
|
| 631 | b854608e | bellard | env->xcc |= PSR_CARRY; |
| 632 | b854608e | bellard | #else
|
| 633 | b854608e | bellard | if (src1 <= T1)
|
| 634 | b854608e | bellard | env->psr |= PSR_CARRY; |
| 635 | b854608e | bellard | #endif
|
| 636 | b854608e | bellard | } |
| 637 | b854608e | bellard | else
|
| 638 | b854608e | bellard | {
|
| 639 | b854608e | bellard | T0 -= T1; |
| 640 | b854608e | bellard | env->psr = 0;
|
| 641 | b854608e | bellard | #ifdef TARGET_SPARC64
|
| 642 | b854608e | bellard | if ((src1 & 0xffffffff) < (T1 & 0xffffffff)) |
| 643 | b854608e | bellard | env->psr |= PSR_CARRY; |
| 644 | b854608e | bellard | env->xcc = 0;
|
| 645 | b854608e | bellard | if (src1 < T1)
|
| 646 | b854608e | bellard | env->xcc |= PSR_CARRY; |
| 647 | b854608e | bellard | #else
|
| 648 | b854608e | bellard | if (src1 < T1)
|
| 649 | b854608e | bellard | env->psr |= PSR_CARRY; |
| 650 | b854608e | bellard | #endif
|
| 651 | b854608e | bellard | } |
| 652 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
| 653 | 3475187d | bellard | if (!(T0 & 0xffffffff)) |
| 654 | 0f8a249a | blueswir1 | env->psr |= PSR_ZERO; |
| 655 | 3475187d | bellard | if ((int32_t) T0 < 0) |
| 656 | 0f8a249a | blueswir1 | env->psr |= PSR_NEG; |
| 657 | 3475187d | bellard | if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) & |
| 658 | 0f8a249a | blueswir1 | ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31)) |
| 659 | 0f8a249a | blueswir1 | env->psr |= PSR_OVF; |
| 660 | 3475187d | bellard | |
| 661 | 3475187d | bellard | if (!T0)
|
| 662 | 0f8a249a | blueswir1 | env->xcc |= PSR_ZERO; |
| 663 | 3475187d | bellard | if ((int64_t) T0 < 0) |
| 664 | 0f8a249a | blueswir1 | env->xcc |= PSR_NEG; |
| 665 | 3475187d | bellard | if (((src1 ^ T1) & (src1 ^ T0)) & (1ULL << 63)) |
| 666 | 0f8a249a | blueswir1 | env->xcc |= PSR_OVF; |
| 667 | 3475187d | bellard | #else
|
| 668 | af7bf89b | bellard | if (!T0)
|
| 669 | 0f8a249a | blueswir1 | env->psr |= PSR_ZERO; |
| 670 | af7bf89b | bellard | if ((int32_t) T0 < 0) |
| 671 | 0f8a249a | blueswir1 | env->psr |= PSR_NEG; |
| 672 | af7bf89b | bellard | if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31)) |
| 673 | 0f8a249a | blueswir1 | env->psr |= PSR_OVF; |
| 674 | 3475187d | bellard | #endif
|
| 675 | cf495bcf | bellard | FORCE_RET(); |
| 676 | 7a3f1944 | bellard | } |
| 677 | 7a3f1944 | bellard | |
| 678 | e32f879d | blueswir1 | void OPPROTO op_tsub_T1_T0_cc(void) |
| 679 | e32f879d | blueswir1 | {
|
| 680 | e32f879d | blueswir1 | target_ulong src1; |
| 681 | e32f879d | blueswir1 | |
| 682 | e32f879d | blueswir1 | src1 = T0; |
| 683 | e32f879d | blueswir1 | T0 -= T1; |
| 684 | e32f879d | blueswir1 | env->psr = 0;
|
| 685 | e32f879d | blueswir1 | #ifdef TARGET_SPARC64
|
| 686 | e32f879d | blueswir1 | if (!(T0 & 0xffffffff)) |
| 687 | 0f8a249a | blueswir1 | env->psr |= PSR_ZERO; |
| 688 | e32f879d | blueswir1 | if ((int32_t) T0 < 0) |
| 689 | 0f8a249a | blueswir1 | env->psr |= PSR_NEG; |
| 690 | e32f879d | blueswir1 | if ((src1 & 0xffffffff) < (T1 & 0xffffffff)) |
| 691 | 0f8a249a | blueswir1 | env->psr |= PSR_CARRY; |
| 692 | e32f879d | blueswir1 | if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) & |
| 693 | 0f8a249a | blueswir1 | ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31)) |
| 694 | 0f8a249a | blueswir1 | env->psr |= PSR_OVF; |
| 695 | e32f879d | blueswir1 | if ((src1 & 0x03) || (T1 & 0x03)) |
| 696 | 0f8a249a | blueswir1 | env->psr |= PSR_OVF; |
| 697 | e32f879d | blueswir1 | |
| 698 | e32f879d | blueswir1 | env->xcc = 0;
|
| 699 | e32f879d | blueswir1 | if (!T0)
|
| 700 | 0f8a249a | blueswir1 | env->xcc |= PSR_ZERO; |
| 701 | e32f879d | blueswir1 | if ((int64_t) T0 < 0) |
| 702 | 0f8a249a | blueswir1 | env->xcc |= PSR_NEG; |
| 703 | e32f879d | blueswir1 | if (src1 < T1)
|
| 704 | 0f8a249a | blueswir1 | env->xcc |= PSR_CARRY; |
| 705 | e32f879d | blueswir1 | if (((src1 ^ T1) & (src1 ^ T0)) & (1ULL << 63)) |
| 706 | 0f8a249a | blueswir1 | env->xcc |= PSR_OVF; |
| 707 | e32f879d | blueswir1 | #else
|
| 708 | e32f879d | blueswir1 | if (!T0)
|
| 709 | 0f8a249a | blueswir1 | env->psr |= PSR_ZERO; |
| 710 | e32f879d | blueswir1 | if ((int32_t) T0 < 0) |
| 711 | 0f8a249a | blueswir1 | env->psr |= PSR_NEG; |
| 712 | e32f879d | blueswir1 | if (src1 < T1)
|
| 713 | 0f8a249a | blueswir1 | env->psr |= PSR_CARRY; |
| 714 | e32f879d | blueswir1 | if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31)) |
| 715 | 0f8a249a | blueswir1 | env->psr |= PSR_OVF; |
| 716 | e32f879d | blueswir1 | if ((src1 & 0x03) || (T1 & 0x03)) |
| 717 | 0f8a249a | blueswir1 | env->psr |= PSR_OVF; |
| 718 | e32f879d | blueswir1 | #endif
|
| 719 | e32f879d | blueswir1 | FORCE_RET(); |
| 720 | e32f879d | blueswir1 | } |
| 721 | e32f879d | blueswir1 | |
| 722 | e32f879d | blueswir1 | void OPPROTO op_tsub_T1_T0_ccTV(void) |
| 723 | e32f879d | blueswir1 | {
|
| 724 | e32f879d | blueswir1 | target_ulong src1; |
| 725 | e32f879d | blueswir1 | |
| 726 | e32f879d | blueswir1 | if ((T0 & 0x03) || (T1 & 0x03)) |
| 727 | e32f879d | blueswir1 | raise_exception(TT_TOVF); |
| 728 | e32f879d | blueswir1 | |
| 729 | e32f879d | blueswir1 | src1 = T0; |
| 730 | e32f879d | blueswir1 | T0 -= T1; |
| 731 | e32f879d | blueswir1 | |
| 732 | e32f879d | blueswir1 | #ifdef TARGET_SPARC64
|
| 733 | e32f879d | blueswir1 | if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) & |
| 734 | 0f8a249a | blueswir1 | ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31)) |
| 735 | e32f879d | blueswir1 | raise_exception(TT_TOVF); |
| 736 | e32f879d | blueswir1 | #else
|
| 737 | e32f879d | blueswir1 | if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31)) |
| 738 | e32f879d | blueswir1 | raise_exception(TT_TOVF); |
| 739 | e32f879d | blueswir1 | #endif
|
| 740 | e32f879d | blueswir1 | |
| 741 | e32f879d | blueswir1 | env->psr = 0;
|
| 742 | e32f879d | blueswir1 | #ifdef TARGET_SPARC64
|
| 743 | e32f879d | blueswir1 | if (!(T0 & 0xffffffff)) |
| 744 | 0f8a249a | blueswir1 | env->psr |= PSR_ZERO; |
| 745 | e32f879d | blueswir1 | if ((int32_t) T0 < 0) |
| 746 | 0f8a249a | blueswir1 | env->psr |= PSR_NEG; |
| 747 | e32f879d | blueswir1 | if ((src1 & 0xffffffff) < (T1 & 0xffffffff)) |
| 748 | 0f8a249a | blueswir1 | env->psr |= PSR_CARRY; |
| 749 | e32f879d | blueswir1 | |
| 750 | e32f879d | blueswir1 | env->xcc = 0;
|
| 751 | e32f879d | blueswir1 | if (!T0)
|
| 752 | 0f8a249a | blueswir1 | env->xcc |= PSR_ZERO; |
| 753 | e32f879d | blueswir1 | if ((int64_t) T0 < 0) |
| 754 | 0f8a249a | blueswir1 | env->xcc |= PSR_NEG; |
| 755 | e32f879d | blueswir1 | if (src1 < T1)
|
| 756 | 0f8a249a | blueswir1 | env->xcc |= PSR_CARRY; |
| 757 | e32f879d | blueswir1 | #else
|
| 758 | e32f879d | blueswir1 | if (!T0)
|
| 759 | 0f8a249a | blueswir1 | env->psr |= PSR_ZERO; |
| 760 | e32f879d | blueswir1 | if ((int32_t) T0 < 0) |
| 761 | 0f8a249a | blueswir1 | env->psr |= PSR_NEG; |
| 762 | e32f879d | blueswir1 | if (src1 < T1)
|
| 763 | 0f8a249a | blueswir1 | env->psr |= PSR_CARRY; |
| 764 | e32f879d | blueswir1 | #endif
|
| 765 | e32f879d | blueswir1 | FORCE_RET(); |
| 766 | e32f879d | blueswir1 | } |
| 767 | e32f879d | blueswir1 | |
| 768 | cf495bcf | bellard | void OPPROTO op_and_T1_T0(void) |
| 769 | 7a3f1944 | bellard | {
|
| 770 | cf495bcf | bellard | T0 &= T1; |
| 771 | 7a3f1944 | bellard | } |
| 772 | 7a3f1944 | bellard | |
| 773 | cf495bcf | bellard | void OPPROTO op_or_T1_T0(void) |
| 774 | 7a3f1944 | bellard | {
|
| 775 | cf495bcf | bellard | T0 |= T1; |
| 776 | 7a3f1944 | bellard | } |
| 777 | 7a3f1944 | bellard | |
| 778 | cf495bcf | bellard | void OPPROTO op_xor_T1_T0(void) |
| 779 | 7a3f1944 | bellard | {
|
| 780 | cf495bcf | bellard | T0 ^= T1; |
| 781 | 7a3f1944 | bellard | } |
| 782 | 7a3f1944 | bellard | |
| 783 | cf495bcf | bellard | void OPPROTO op_andn_T1_T0(void) |
| 784 | 7a3f1944 | bellard | {
|
| 785 | cf495bcf | bellard | T0 &= ~T1; |
| 786 | 7a3f1944 | bellard | } |
| 787 | 7a3f1944 | bellard | |
| 788 | cf495bcf | bellard | void OPPROTO op_orn_T1_T0(void) |
| 789 | 7a3f1944 | bellard | {
|
| 790 | cf495bcf | bellard | T0 |= ~T1; |
| 791 | 7a3f1944 | bellard | } |
| 792 | 7a3f1944 | bellard | |
| 793 | cf495bcf | bellard | void OPPROTO op_xnor_T1_T0(void) |
| 794 | 7a3f1944 | bellard | {
|
| 795 | cf495bcf | bellard | T0 ^= ~T1; |
| 796 | 7a3f1944 | bellard | } |
| 797 | 7a3f1944 | bellard | |
| 798 | cf495bcf | bellard | void OPPROTO op_umul_T1_T0(void) |
| 799 | 7a3f1944 | bellard | {
|
| 800 | cf495bcf | bellard | uint64_t res; |
| 801 | af7bf89b | bellard | res = (uint64_t) T0 * (uint64_t) T1; |
| 802 | 83469015 | bellard | #ifdef TARGET_SPARC64
|
| 803 | 83469015 | bellard | T0 = res; |
| 804 | 83469015 | bellard | #else
|
| 805 | cf495bcf | bellard | T0 = res & 0xffffffff;
|
| 806 | 83469015 | bellard | #endif
|
| 807 | cf495bcf | bellard | env->y = res >> 32;
|
| 808 | 7a3f1944 | bellard | } |
| 809 | 7a3f1944 | bellard | |
| 810 | cf495bcf | bellard | void OPPROTO op_smul_T1_T0(void) |
| 811 | 7a3f1944 | bellard | {
|
| 812 | cf495bcf | bellard | uint64_t res; |
| 813 | cf495bcf | bellard | res = (int64_t) ((int32_t) T0) * (int64_t) ((int32_t) T1); |
| 814 | 83469015 | bellard | #ifdef TARGET_SPARC64
|
| 815 | 83469015 | bellard | T0 = res; |
| 816 | 83469015 | bellard | #else
|
| 817 | cf495bcf | bellard | T0 = res & 0xffffffff;
|
| 818 | 83469015 | bellard | #endif
|
| 819 | cf495bcf | bellard | env->y = res >> 32;
|
| 820 | 7a3f1944 | bellard | } |
| 821 | 7a3f1944 | bellard | |
| 822 | cf495bcf | bellard | void OPPROTO op_mulscc_T1_T0(void) |
| 823 | 7a3f1944 | bellard | {
|
| 824 | af7bf89b | bellard | unsigned int b1, N, V, b2; |
| 825 | af7bf89b | bellard | target_ulong src1; |
| 826 | af7bf89b | bellard | |
| 827 | 4e8b5da2 | bellard | N = FLAG_SET(PSR_NEG); |
| 828 | cf495bcf | bellard | V = FLAG_SET(PSR_OVF); |
| 829 | 4e8b5da2 | bellard | b1 = N ^ V; |
| 830 | cf495bcf | bellard | b2 = T0 & 1;
|
| 831 | cf495bcf | bellard | T0 = (b1 << 31) | (T0 >> 1); |
| 832 | cf495bcf | bellard | if (!(env->y & 1)) |
| 833 | cf495bcf | bellard | T1 = 0;
|
| 834 | cf495bcf | bellard | /* do addition and update flags */
|
| 835 | cf495bcf | bellard | src1 = T0; |
| 836 | cf495bcf | bellard | T0 += T1; |
| 837 | cf495bcf | bellard | env->psr = 0;
|
| 838 | cf495bcf | bellard | if (!T0)
|
| 839 | 0f8a249a | blueswir1 | env->psr |= PSR_ZERO; |
| 840 | af7bf89b | bellard | if ((int32_t) T0 < 0) |
| 841 | 0f8a249a | blueswir1 | env->psr |= PSR_NEG; |
| 842 | cf495bcf | bellard | if (T0 < src1)
|
| 843 | 0f8a249a | blueswir1 | env->psr |= PSR_CARRY; |
| 844 | cf495bcf | bellard | if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31)) |
| 845 | 0f8a249a | blueswir1 | env->psr |= PSR_OVF; |
| 846 | cf495bcf | bellard | env->y = (b2 << 31) | (env->y >> 1); |
| 847 | cf495bcf | bellard | FORCE_RET(); |
| 848 | cf495bcf | bellard | } |
| 849 | cf495bcf | bellard | |
| 850 | cf495bcf | bellard | void OPPROTO op_udiv_T1_T0(void) |
| 851 | cf495bcf | bellard | {
|
| 852 | cf495bcf | bellard | uint64_t x0; |
| 853 | cf495bcf | bellard | uint32_t x1; |
| 854 | cf495bcf | bellard | |
| 855 | cf495bcf | bellard | x0 = T0 | ((uint64_t) (env->y) << 32);
|
| 856 | cf495bcf | bellard | x1 = T1; |
| 857 | 9bb234b3 | ths | |
| 858 | 9bb234b3 | ths | if (x1 == 0) { |
| 859 | 9bb234b3 | ths | raise_exception(TT_DIV_ZERO); |
| 860 | 9bb234b3 | ths | } |
| 861 | 9bb234b3 | ths | |
| 862 | cf495bcf | bellard | x0 = x0 / x1; |
| 863 | cf495bcf | bellard | if (x0 > 0xffffffff) { |
| 864 | 0f8a249a | blueswir1 | T0 = 0xffffffff;
|
| 865 | 0f8a249a | blueswir1 | T1 = 1;
|
| 866 | cf495bcf | bellard | } else {
|
| 867 | 0f8a249a | blueswir1 | T0 = x0; |
| 868 | 0f8a249a | blueswir1 | T1 = 0;
|
| 869 | cf495bcf | bellard | } |
| 870 | cf495bcf | bellard | FORCE_RET(); |
| 871 | 7a3f1944 | bellard | } |
| 872 | 7a3f1944 | bellard | |
| 873 | cf495bcf | bellard | void OPPROTO op_sdiv_T1_T0(void) |
| 874 | 7a3f1944 | bellard | {
|
| 875 | cf495bcf | bellard | int64_t x0; |
| 876 | cf495bcf | bellard | int32_t x1; |
| 877 | cf495bcf | bellard | |
| 878 | af7bf89b | bellard | x0 = T0 | ((int64_t) (env->y) << 32);
|
| 879 | cf495bcf | bellard | x1 = T1; |
| 880 | 9bb234b3 | ths | |
| 881 | 9bb234b3 | ths | if (x1 == 0) { |
| 882 | 9bb234b3 | ths | raise_exception(TT_DIV_ZERO); |
| 883 | 9bb234b3 | ths | } |
| 884 | 9bb234b3 | ths | |
| 885 | cf495bcf | bellard | x0 = x0 / x1; |
| 886 | cf495bcf | bellard | if ((int32_t) x0 != x0) {
|
| 887 | 0f8a249a | blueswir1 | T0 = x0 < 0? 0x80000000: 0x7fffffff; |
| 888 | 0f8a249a | blueswir1 | T1 = 1;
|
| 889 | cf495bcf | bellard | } else {
|
| 890 | 0f8a249a | blueswir1 | T0 = x0; |
| 891 | 0f8a249a | blueswir1 | T1 = 0;
|
| 892 | cf495bcf | bellard | } |
| 893 | cf495bcf | bellard | FORCE_RET(); |
| 894 | 7a3f1944 | bellard | } |
| 895 | 7a3f1944 | bellard | |
| 896 | cf495bcf | bellard | void OPPROTO op_div_cc(void) |
| 897 | 7a3f1944 | bellard | {
|
| 898 | cf495bcf | bellard | env->psr = 0;
|
| 899 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
| 900 | 3475187d | bellard | if (!T0)
|
| 901 | 0f8a249a | blueswir1 | env->psr |= PSR_ZERO; |
| 902 | 3475187d | bellard | if ((int32_t) T0 < 0) |
| 903 | 0f8a249a | blueswir1 | env->psr |= PSR_NEG; |
| 904 | 3475187d | bellard | if (T1)
|
| 905 | 0f8a249a | blueswir1 | env->psr |= PSR_OVF; |
| 906 | 3475187d | bellard | |
| 907 | 3475187d | bellard | env->xcc = 0;
|
| 908 | 3475187d | bellard | if (!T0)
|
| 909 | 0f8a249a | blueswir1 | env->xcc |= PSR_ZERO; |
| 910 | 3475187d | bellard | if ((int64_t) T0 < 0) |
| 911 | 0f8a249a | blueswir1 | env->xcc |= PSR_NEG; |
| 912 | 3475187d | bellard | #else
|
| 913 | cf495bcf | bellard | if (!T0)
|
| 914 | 0f8a249a | blueswir1 | env->psr |= PSR_ZERO; |
| 915 | af7bf89b | bellard | if ((int32_t) T0 < 0) |
| 916 | 0f8a249a | blueswir1 | env->psr |= PSR_NEG; |
| 917 | cf495bcf | bellard | if (T1)
|
| 918 | 0f8a249a | blueswir1 | env->psr |= PSR_OVF; |
| 919 | 3475187d | bellard | #endif
|
| 920 | cf495bcf | bellard | FORCE_RET(); |
| 921 | 7a3f1944 | bellard | } |
| 922 | 7a3f1944 | bellard | |
| 923 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
| 924 | 3475187d | bellard | void OPPROTO op_mulx_T1_T0(void) |
| 925 | 3475187d | bellard | {
|
| 926 | 3475187d | bellard | T0 *= T1; |
| 927 | 3475187d | bellard | FORCE_RET(); |
| 928 | 3475187d | bellard | } |
| 929 | 3475187d | bellard | |
| 930 | 3475187d | bellard | void OPPROTO op_udivx_T1_T0(void) |
| 931 | 3475187d | bellard | {
|
| 932 | 14a1120e | blueswir1 | if (T1 == 0) { |
| 933 | 14a1120e | blueswir1 | raise_exception(TT_DIV_ZERO); |
| 934 | 14a1120e | blueswir1 | } |
| 935 | 3475187d | bellard | T0 /= T1; |
| 936 | 3475187d | bellard | FORCE_RET(); |
| 937 | 3475187d | bellard | } |
| 938 | 3475187d | bellard | |
| 939 | 3475187d | bellard | void OPPROTO op_sdivx_T1_T0(void) |
| 940 | 3475187d | bellard | {
|
| 941 | 14a1120e | blueswir1 | if (T1 == 0) { |
| 942 | 14a1120e | blueswir1 | raise_exception(TT_DIV_ZERO); |
| 943 | 14a1120e | blueswir1 | } |
| 944 | 3475187d | bellard | if (T0 == INT64_MIN && T1 == -1) |
| 945 | 0f8a249a | blueswir1 | T0 = INT64_MIN; |
| 946 | 3475187d | bellard | else
|
| 947 | 0f8a249a | blueswir1 | T0 /= (target_long) T1; |
| 948 | 3475187d | bellard | FORCE_RET(); |
| 949 | 3475187d | bellard | } |
| 950 | 3475187d | bellard | #endif
|
| 951 | 3475187d | bellard | |
| 952 | cf495bcf | bellard | void OPPROTO op_logic_T0_cc(void) |
| 953 | 7a3f1944 | bellard | {
|
| 954 | cf495bcf | bellard | env->psr = 0;
|
| 955 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
| 956 | 3475187d | bellard | if (!(T0 & 0xffffffff)) |
| 957 | 0f8a249a | blueswir1 | env->psr |= PSR_ZERO; |
| 958 | 3475187d | bellard | if ((int32_t) T0 < 0) |
| 959 | 0f8a249a | blueswir1 | env->psr |= PSR_NEG; |
| 960 | 3475187d | bellard | |
| 961 | 3475187d | bellard | env->xcc = 0;
|
| 962 | 3475187d | bellard | if (!T0)
|
| 963 | 0f8a249a | blueswir1 | env->xcc |= PSR_ZERO; |
| 964 | 3475187d | bellard | if ((int64_t) T0 < 0) |
| 965 | 0f8a249a | blueswir1 | env->xcc |= PSR_NEG; |
| 966 | 3475187d | bellard | #else
|
| 967 | cf495bcf | bellard | if (!T0)
|
| 968 | 0f8a249a | blueswir1 | env->psr |= PSR_ZERO; |
| 969 | af7bf89b | bellard | if ((int32_t) T0 < 0) |
| 970 | 0f8a249a | blueswir1 | env->psr |= PSR_NEG; |
| 971 | 3475187d | bellard | #endif
|
| 972 | cf495bcf | bellard | FORCE_RET(); |
| 973 | 7a3f1944 | bellard | } |
| 974 | 7a3f1944 | bellard | |
| 975 | cf495bcf | bellard | void OPPROTO op_sll(void) |
| 976 | 7a3f1944 | bellard | {
|
| 977 | 8a08f9a8 | blueswir1 | T0 <<= (T1 & 0x1f);
|
| 978 | 7a3f1944 | bellard | } |
| 979 | 7a3f1944 | bellard | |
| 980 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
| 981 | 8a08f9a8 | blueswir1 | void OPPROTO op_sllx(void) |
| 982 | 8a08f9a8 | blueswir1 | {
|
| 983 | 8a08f9a8 | blueswir1 | T0 <<= (T1 & 0x3f);
|
| 984 | 8a08f9a8 | blueswir1 | } |
| 985 | 8a08f9a8 | blueswir1 | |
| 986 | 3475187d | bellard | void OPPROTO op_srl(void) |
| 987 | 3475187d | bellard | {
|
| 988 | 8a08f9a8 | blueswir1 | T0 = (T0 & 0xffffffff) >> (T1 & 0x1f); |
| 989 | 3475187d | bellard | } |
| 990 | 3475187d | bellard | |
| 991 | 3475187d | bellard | void OPPROTO op_srlx(void) |
| 992 | 3475187d | bellard | {
|
| 993 | 8a08f9a8 | blueswir1 | T0 >>= (T1 & 0x3f);
|
| 994 | 3475187d | bellard | } |
| 995 | 3475187d | bellard | |
| 996 | 3475187d | bellard | void OPPROTO op_sra(void) |
| 997 | 3475187d | bellard | {
|
| 998 | 8a08f9a8 | blueswir1 | T0 = ((int32_t) (T0 & 0xffffffff)) >> (T1 & 0x1f); |
| 999 | 3475187d | bellard | } |
| 1000 | 3475187d | bellard | |
| 1001 | 3475187d | bellard | void OPPROTO op_srax(void) |
| 1002 | 3475187d | bellard | {
|
| 1003 | 8a08f9a8 | blueswir1 | T0 = ((int64_t) T0) >> (T1 & 0x3f);
|
| 1004 | 3475187d | bellard | } |
| 1005 | 3475187d | bellard | #else
|
| 1006 | cf495bcf | bellard | void OPPROTO op_srl(void) |
| 1007 | 7a3f1944 | bellard | {
|
| 1008 | 8a08f9a8 | blueswir1 | T0 >>= (T1 & 0x1f);
|
| 1009 | 7a3f1944 | bellard | } |
| 1010 | 7a3f1944 | bellard | |
| 1011 | cf495bcf | bellard | void OPPROTO op_sra(void) |
| 1012 | 7a3f1944 | bellard | {
|
| 1013 | 8a08f9a8 | blueswir1 | T0 = ((int32_t) T0) >> (T1 & 0x1f);
|
| 1014 | 7a3f1944 | bellard | } |
| 1015 | 3475187d | bellard | #endif
|
| 1016 | 7a3f1944 | bellard | |
| 1017 | e8af50a3 | bellard | /* Load and store */
|
| 1018 | e8af50a3 | bellard | #define MEMSUFFIX _raw
|
| 1019 | e8af50a3 | bellard | #include "op_mem.h" |
| 1020 | e8af50a3 | bellard | #if !defined(CONFIG_USER_ONLY)
|
| 1021 | e8af50a3 | bellard | #define MEMSUFFIX _user
|
| 1022 | e8af50a3 | bellard | #include "op_mem.h" |
| 1023 | e8af50a3 | bellard | |
| 1024 | e8af50a3 | bellard | #define MEMSUFFIX _kernel
|
| 1025 | e8af50a3 | bellard | #include "op_mem.h" |
| 1026 | e8af50a3 | bellard | #endif
|
| 1027 | e8af50a3 | bellard | |
| 1028 | e8af50a3 | bellard | void OPPROTO op_ldfsr(void) |
| 1029 | e8af50a3 | bellard | {
|
| 1030 | 3475187d | bellard | PUT_FSR32(env, *((uint32_t *) &FT0)); |
| 1031 | 8d5f07fa | bellard | helper_ldfsr(); |
| 1032 | e8af50a3 | bellard | } |
| 1033 | e8af50a3 | bellard | |
| 1034 | e8af50a3 | bellard | void OPPROTO op_stfsr(void) |
| 1035 | e8af50a3 | bellard | {
|
| 1036 | 3475187d | bellard | *((uint32_t *) &FT0) = GET_FSR32(env); |
| 1037 | e8af50a3 | bellard | } |
| 1038 | e8af50a3 | bellard | |
| 1039 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
| 1040 | 3475187d | bellard | void OPPROTO op_rdpsr(void) |
| 1041 | 7a3f1944 | bellard | {
|
| 1042 | 3475187d | bellard | do_rdpsr(); |
| 1043 | 7a3f1944 | bellard | } |
| 1044 | 7a3f1944 | bellard | |
| 1045 | 3475187d | bellard | void OPPROTO op_wrpsr(void) |
| 1046 | 7a3f1944 | bellard | {
|
| 1047 | 3475187d | bellard | do_wrpsr(); |
| 1048 | 3475187d | bellard | FORCE_RET(); |
| 1049 | 7a3f1944 | bellard | } |
| 1050 | 7a3f1944 | bellard | |
| 1051 | c688a6eb | bellard | void OPPROTO op_wrwim(void) |
| 1052 | c688a6eb | bellard | {
|
| 1053 | c688a6eb | bellard | #if NWINDOWS == 32 |
| 1054 | c688a6eb | bellard | env->wim = T0; |
| 1055 | c688a6eb | bellard | #else
|
| 1056 | c688a6eb | bellard | env->wim = T0 & ((1 << NWINDOWS) - 1); |
| 1057 | c688a6eb | bellard | #endif
|
| 1058 | c688a6eb | bellard | } |
| 1059 | c688a6eb | bellard | |
| 1060 | 3475187d | bellard | void OPPROTO op_rett(void) |
| 1061 | cf495bcf | bellard | {
|
| 1062 | 3475187d | bellard | helper_rett(); |
| 1063 | 3475187d | bellard | FORCE_RET(); |
| 1064 | e8af50a3 | bellard | } |
| 1065 | e8af50a3 | bellard | |
| 1066 | 3475187d | bellard | /* XXX: use another pointer for %iN registers to avoid slow wrapping
|
| 1067 | 3475187d | bellard | handling ? */
|
| 1068 | 3475187d | bellard | void OPPROTO op_save(void) |
| 1069 | e8af50a3 | bellard | {
|
| 1070 | 3475187d | bellard | uint32_t cwp; |
| 1071 | 5fafdf24 | ths | cwp = (env->cwp - 1) & (NWINDOWS - 1); |
| 1072 | 3475187d | bellard | if (env->wim & (1 << cwp)) { |
| 1073 | 3475187d | bellard | raise_exception(TT_WIN_OVF); |
| 1074 | 3475187d | bellard | } |
| 1075 | 3475187d | bellard | set_cwp(cwp); |
| 1076 | e8af50a3 | bellard | FORCE_RET(); |
| 1077 | e8af50a3 | bellard | } |
| 1078 | e8af50a3 | bellard | |
| 1079 | 3475187d | bellard | void OPPROTO op_restore(void) |
| 1080 | e8af50a3 | bellard | {
|
| 1081 | 3475187d | bellard | uint32_t cwp; |
| 1082 | 5fafdf24 | ths | cwp = (env->cwp + 1) & (NWINDOWS - 1); |
| 1083 | 3475187d | bellard | if (env->wim & (1 << cwp)) { |
| 1084 | 3475187d | bellard | raise_exception(TT_WIN_UNF); |
| 1085 | 3475187d | bellard | } |
| 1086 | 3475187d | bellard | set_cwp(cwp); |
| 1087 | 3475187d | bellard | FORCE_RET(); |
| 1088 | 3475187d | bellard | } |
| 1089 | 3475187d | bellard | #else
|
| 1090 | 3475187d | bellard | void OPPROTO op_rdccr(void) |
| 1091 | 3475187d | bellard | {
|
| 1092 | 3475187d | bellard | T0 = GET_CCR(env); |
| 1093 | e8af50a3 | bellard | } |
| 1094 | e8af50a3 | bellard | |
| 1095 | 3475187d | bellard | void OPPROTO op_wrccr(void) |
| 1096 | e8af50a3 | bellard | {
|
| 1097 | 3475187d | bellard | PUT_CCR(env, T0); |
| 1098 | e8af50a3 | bellard | } |
| 1099 | e8af50a3 | bellard | |
| 1100 | 3475187d | bellard | void OPPROTO op_rdtick(void) |
| 1101 | e8af50a3 | bellard | {
|
| 1102 | 20c9f095 | blueswir1 | T0 = do_tick_get_count(env->tick); |
| 1103 | e8af50a3 | bellard | } |
| 1104 | cf495bcf | bellard | |
| 1105 | 3475187d | bellard | void OPPROTO op_wrtick(void) |
| 1106 | 7a3f1944 | bellard | {
|
| 1107 | 20c9f095 | blueswir1 | do_tick_set_count(env->tick, T0); |
| 1108 | 20c9f095 | blueswir1 | } |
| 1109 | 20c9f095 | blueswir1 | |
| 1110 | 20c9f095 | blueswir1 | void OPPROTO op_wrtick_cmpr(void) |
| 1111 | 20c9f095 | blueswir1 | {
|
| 1112 | 20c9f095 | blueswir1 | do_tick_set_limit(env->tick, T0); |
| 1113 | 20c9f095 | blueswir1 | } |
| 1114 | 20c9f095 | blueswir1 | |
| 1115 | 20c9f095 | blueswir1 | void OPPROTO op_rdstick(void) |
| 1116 | 20c9f095 | blueswir1 | {
|
| 1117 | 20c9f095 | blueswir1 | T0 = do_tick_get_count(env->stick); |
| 1118 | 20c9f095 | blueswir1 | } |
| 1119 | 20c9f095 | blueswir1 | |
| 1120 | 20c9f095 | blueswir1 | void OPPROTO op_wrstick(void) |
| 1121 | 20c9f095 | blueswir1 | {
|
| 1122 | 20c9f095 | blueswir1 | do_tick_set_count(env->stick, T0); |
| 1123 | 20c9f095 | blueswir1 | do_tick_set_count(env->hstick, T0); |
| 1124 | 20c9f095 | blueswir1 | } |
| 1125 | 20c9f095 | blueswir1 | |
| 1126 | 20c9f095 | blueswir1 | void OPPROTO op_wrstick_cmpr(void) |
| 1127 | 20c9f095 | blueswir1 | {
|
| 1128 | 20c9f095 | blueswir1 | do_tick_set_limit(env->stick, T0); |
| 1129 | 20c9f095 | blueswir1 | } |
| 1130 | 20c9f095 | blueswir1 | |
| 1131 | 20c9f095 | blueswir1 | void OPPROTO op_wrhstick_cmpr(void) |
| 1132 | 20c9f095 | blueswir1 | {
|
| 1133 | 20c9f095 | blueswir1 | do_tick_set_limit(env->hstick, T0); |
| 1134 | 7a3f1944 | bellard | } |
| 1135 | 7a3f1944 | bellard | |
| 1136 | 3475187d | bellard | void OPPROTO op_rdtpc(void) |
| 1137 | cf495bcf | bellard | {
|
| 1138 | 3475187d | bellard | T0 = env->tpc[env->tl]; |
| 1139 | 3475187d | bellard | } |
| 1140 | 3475187d | bellard | |
| 1141 | 3475187d | bellard | void OPPROTO op_wrtpc(void) |
| 1142 | 3475187d | bellard | {
|
| 1143 | 3475187d | bellard | env->tpc[env->tl] = T0; |
| 1144 | 3475187d | bellard | } |
| 1145 | 3475187d | bellard | |
| 1146 | 3475187d | bellard | void OPPROTO op_rdtnpc(void) |
| 1147 | 3475187d | bellard | {
|
| 1148 | 3475187d | bellard | T0 = env->tnpc[env->tl]; |
| 1149 | 3475187d | bellard | } |
| 1150 | 3475187d | bellard | |
| 1151 | 3475187d | bellard | void OPPROTO op_wrtnpc(void) |
| 1152 | 3475187d | bellard | {
|
| 1153 | 3475187d | bellard | env->tnpc[env->tl] = T0; |
| 1154 | 3475187d | bellard | } |
| 1155 | 3475187d | bellard | |
| 1156 | 3475187d | bellard | void OPPROTO op_rdtstate(void) |
| 1157 | 3475187d | bellard | {
|
| 1158 | 3475187d | bellard | T0 = env->tstate[env->tl]; |
| 1159 | 3475187d | bellard | } |
| 1160 | 3475187d | bellard | |
| 1161 | 3475187d | bellard | void OPPROTO op_wrtstate(void) |
| 1162 | 3475187d | bellard | {
|
| 1163 | 3475187d | bellard | env->tstate[env->tl] = T0; |
| 1164 | 3475187d | bellard | } |
| 1165 | 3475187d | bellard | |
| 1166 | 3475187d | bellard | void OPPROTO op_rdtt(void) |
| 1167 | 3475187d | bellard | {
|
| 1168 | 3475187d | bellard | T0 = env->tt[env->tl]; |
| 1169 | 3475187d | bellard | } |
| 1170 | 3475187d | bellard | |
| 1171 | 3475187d | bellard | void OPPROTO op_wrtt(void) |
| 1172 | 3475187d | bellard | {
|
| 1173 | 3475187d | bellard | env->tt[env->tl] = T0; |
| 1174 | 3475187d | bellard | } |
| 1175 | 3475187d | bellard | |
| 1176 | 3475187d | bellard | void OPPROTO op_rdpstate(void) |
| 1177 | 3475187d | bellard | {
|
| 1178 | 3475187d | bellard | T0 = env->pstate; |
| 1179 | 3475187d | bellard | } |
| 1180 | 3475187d | bellard | |
| 1181 | 3475187d | bellard | void OPPROTO op_wrpstate(void) |
| 1182 | 3475187d | bellard | {
|
| 1183 | 83469015 | bellard | do_wrpstate(); |
| 1184 | 3475187d | bellard | } |
| 1185 | 3475187d | bellard | |
| 1186 | 3475187d | bellard | // CWP handling is reversed in V9, but we still use the V8 register
|
| 1187 | 3475187d | bellard | // order.
|
| 1188 | 3475187d | bellard | void OPPROTO op_rdcwp(void) |
| 1189 | 3475187d | bellard | {
|
| 1190 | 17d996e1 | blueswir1 | T0 = GET_CWP64(env); |
| 1191 | 3475187d | bellard | } |
| 1192 | 3475187d | bellard | |
| 1193 | 3475187d | bellard | void OPPROTO op_wrcwp(void) |
| 1194 | 3475187d | bellard | {
|
| 1195 | 17d996e1 | blueswir1 | PUT_CWP64(env, T0); |
| 1196 | cf495bcf | bellard | } |
| 1197 | 7a3f1944 | bellard | |
| 1198 | cf495bcf | bellard | /* XXX: use another pointer for %iN registers to avoid slow wrapping
|
| 1199 | cf495bcf | bellard | handling ? */
|
| 1200 | cf495bcf | bellard | void OPPROTO op_save(void) |
| 1201 | 7a3f1944 | bellard | {
|
| 1202 | af7bf89b | bellard | uint32_t cwp; |
| 1203 | 5fafdf24 | ths | cwp = (env->cwp - 1) & (NWINDOWS - 1); |
| 1204 | 3475187d | bellard | if (env->cansave == 0) { |
| 1205 | 5fafdf24 | ths | raise_exception(TT_SPILL | (env->otherwin != 0 ?
|
| 1206 | 0f8a249a | blueswir1 | (TT_WOTHER | ((env->wstate & 0x38) >> 1)): |
| 1207 | 0f8a249a | blueswir1 | ((env->wstate & 0x7) << 2))); |
| 1208 | 3475187d | bellard | } else {
|
| 1209 | 0f8a249a | blueswir1 | if (env->cleanwin - env->canrestore == 0) { |
| 1210 | 0f8a249a | blueswir1 | // XXX Clean windows without trap
|
| 1211 | 0f8a249a | blueswir1 | raise_exception(TT_CLRWIN); |
| 1212 | 0f8a249a | blueswir1 | } else {
|
| 1213 | 0f8a249a | blueswir1 | env->cansave--; |
| 1214 | 0f8a249a | blueswir1 | env->canrestore++; |
| 1215 | 0f8a249a | blueswir1 | set_cwp(cwp); |
| 1216 | 0f8a249a | blueswir1 | } |
| 1217 | cf495bcf | bellard | } |
| 1218 | cf495bcf | bellard | FORCE_RET(); |
| 1219 | 7a3f1944 | bellard | } |
| 1220 | 7a3f1944 | bellard | |
| 1221 | cf495bcf | bellard | void OPPROTO op_restore(void) |
| 1222 | 7a3f1944 | bellard | {
|
| 1223 | af7bf89b | bellard | uint32_t cwp; |
| 1224 | 5fafdf24 | ths | cwp = (env->cwp + 1) & (NWINDOWS - 1); |
| 1225 | 3475187d | bellard | if (env->canrestore == 0) { |
| 1226 | 5fafdf24 | ths | raise_exception(TT_FILL | (env->otherwin != 0 ?
|
| 1227 | 0f8a249a | blueswir1 | (TT_WOTHER | ((env->wstate & 0x38) >> 1)): |
| 1228 | 0f8a249a | blueswir1 | ((env->wstate & 0x7) << 2))); |
| 1229 | 3475187d | bellard | } else {
|
| 1230 | 0f8a249a | blueswir1 | env->cansave++; |
| 1231 | 0f8a249a | blueswir1 | env->canrestore--; |
| 1232 | 0f8a249a | blueswir1 | set_cwp(cwp); |
| 1233 | cf495bcf | bellard | } |
| 1234 | cf495bcf | bellard | FORCE_RET(); |
| 1235 | 7a3f1944 | bellard | } |
| 1236 | 3475187d | bellard | #endif
|
| 1237 | 7a3f1944 | bellard | |
| 1238 | cf495bcf | bellard | void OPPROTO op_exception(void) |
| 1239 | 7a3f1944 | bellard | {
|
| 1240 | cf495bcf | bellard | env->exception_index = PARAM1; |
| 1241 | cf495bcf | bellard | cpu_loop_exit(); |
| 1242 | 7a3f1944 | bellard | } |
| 1243 | 7a3f1944 | bellard | |
| 1244 | cf495bcf | bellard | void OPPROTO op_trap_T0(void) |
| 1245 | 7a3f1944 | bellard | {
|
| 1246 | cf495bcf | bellard | env->exception_index = TT_TRAP + (T0 & 0x7f);
|
| 1247 | cf495bcf | bellard | cpu_loop_exit(); |
| 1248 | 7a3f1944 | bellard | } |
| 1249 | 7a3f1944 | bellard | |
| 1250 | cf495bcf | bellard | void OPPROTO op_trapcc_T0(void) |
| 1251 | 7a3f1944 | bellard | {
|
| 1252 | cf495bcf | bellard | if (T2) {
|
| 1253 | cf495bcf | bellard | env->exception_index = TT_TRAP + (T0 & 0x7f);
|
| 1254 | cf495bcf | bellard | cpu_loop_exit(); |
| 1255 | cf495bcf | bellard | } |
| 1256 | cf495bcf | bellard | FORCE_RET(); |
| 1257 | 7a3f1944 | bellard | } |
| 1258 | 7a3f1944 | bellard | |
| 1259 | e80cfcfc | bellard | void OPPROTO op_fpexception_im(void) |
| 1260 | e8af50a3 | bellard | {
|
| 1261 | e80cfcfc | bellard | env->exception_index = TT_FP_EXCP; |
| 1262 | e80cfcfc | bellard | env->fsr &= ~FSR_FTT_MASK; |
| 1263 | e80cfcfc | bellard | env->fsr |= PARAM1; |
| 1264 | e8af50a3 | bellard | cpu_loop_exit(); |
| 1265 | e80cfcfc | bellard | FORCE_RET(); |
| 1266 | e80cfcfc | bellard | } |
| 1267 | e80cfcfc | bellard | |
| 1268 | e80cfcfc | bellard | void OPPROTO op_debug(void) |
| 1269 | e80cfcfc | bellard | {
|
| 1270 | e80cfcfc | bellard | helper_debug(); |
| 1271 | e8af50a3 | bellard | } |
| 1272 | e8af50a3 | bellard | |
| 1273 | cf495bcf | bellard | void OPPROTO op_exit_tb(void) |
| 1274 | 7a3f1944 | bellard | {
|
| 1275 | cf495bcf | bellard | EXIT_TB(); |
| 1276 | 7a3f1944 | bellard | } |
| 1277 | 7a3f1944 | bellard | |
| 1278 | 3475187d | bellard | void OPPROTO op_eval_ba(void) |
| 1279 | 3475187d | bellard | {
|
| 1280 | 3475187d | bellard | T2 = 1;
|
| 1281 | 3475187d | bellard | } |
| 1282 | 3475187d | bellard | |
| 1283 | cf495bcf | bellard | void OPPROTO op_eval_be(void) |
| 1284 | 7a3f1944 | bellard | {
|
| 1285 | af7bf89b | bellard | T2 = FLAG_SET(PSR_ZERO); |
| 1286 | 7a3f1944 | bellard | } |
| 1287 | 7a3f1944 | bellard | |
| 1288 | cf495bcf | bellard | void OPPROTO op_eval_ble(void) |
| 1289 | 7a3f1944 | bellard | {
|
| 1290 | af7bf89b | bellard | target_ulong Z = FLAG_SET(PSR_ZERO), N = FLAG_SET(PSR_NEG), V = FLAG_SET(PSR_OVF); |
| 1291 | 3b46e624 | ths | |
| 1292 | cf495bcf | bellard | T2 = Z | (N ^ V); |
| 1293 | 7a3f1944 | bellard | } |
| 1294 | 7a3f1944 | bellard | |
| 1295 | cf495bcf | bellard | void OPPROTO op_eval_bl(void) |
| 1296 | 7a3f1944 | bellard | {
|
| 1297 | af7bf89b | bellard | target_ulong N = FLAG_SET(PSR_NEG), V = FLAG_SET(PSR_OVF); |
| 1298 | 612b477d | bellard | |
| 1299 | cf495bcf | bellard | T2 = N ^ V; |
| 1300 | 7a3f1944 | bellard | } |
| 1301 | 7a3f1944 | bellard | |
| 1302 | cf495bcf | bellard | void OPPROTO op_eval_bleu(void) |
| 1303 | 7a3f1944 | bellard | {
|
| 1304 | af7bf89b | bellard | target_ulong Z = FLAG_SET(PSR_ZERO), C = FLAG_SET(PSR_CARRY); |
| 1305 | 612b477d | bellard | |
| 1306 | cf495bcf | bellard | T2 = C | Z; |
| 1307 | 7a3f1944 | bellard | } |
| 1308 | 7a3f1944 | bellard | |
| 1309 | cf495bcf | bellard | void OPPROTO op_eval_bcs(void) |
| 1310 | 7a3f1944 | bellard | {
|
| 1311 | af7bf89b | bellard | T2 = FLAG_SET(PSR_CARRY); |
| 1312 | 7a3f1944 | bellard | } |
| 1313 | 7a3f1944 | bellard | |
| 1314 | cf495bcf | bellard | void OPPROTO op_eval_bvs(void) |
| 1315 | 7a3f1944 | bellard | {
|
| 1316 | af7bf89b | bellard | T2 = FLAG_SET(PSR_OVF); |
| 1317 | 7a3f1944 | bellard | } |
| 1318 | 7a3f1944 | bellard | |
| 1319 | 3475187d | bellard | void OPPROTO op_eval_bn(void) |
| 1320 | 3475187d | bellard | {
|
| 1321 | 3475187d | bellard | T2 = 0;
|
| 1322 | 3475187d | bellard | } |
| 1323 | 3475187d | bellard | |
| 1324 | cf495bcf | bellard | void OPPROTO op_eval_bneg(void) |
| 1325 | 7a3f1944 | bellard | {
|
| 1326 | af7bf89b | bellard | T2 = FLAG_SET(PSR_NEG); |
| 1327 | 7a3f1944 | bellard | } |
| 1328 | 7a3f1944 | bellard | |
| 1329 | cf495bcf | bellard | void OPPROTO op_eval_bne(void) |
| 1330 | 7a3f1944 | bellard | {
|
| 1331 | af7bf89b | bellard | T2 = !FLAG_SET(PSR_ZERO); |
| 1332 | 7a3f1944 | bellard | } |
| 1333 | 7a3f1944 | bellard | |
| 1334 | cf495bcf | bellard | void OPPROTO op_eval_bg(void) |
| 1335 | 7a3f1944 | bellard | {
|
| 1336 | af7bf89b | bellard | target_ulong Z = FLAG_SET(PSR_ZERO), N = FLAG_SET(PSR_NEG), V = FLAG_SET(PSR_OVF); |
| 1337 | 612b477d | bellard | |
| 1338 | cf495bcf | bellard | T2 = !(Z | (N ^ V)); |
| 1339 | 7a3f1944 | bellard | } |
| 1340 | 7a3f1944 | bellard | |
| 1341 | cf495bcf | bellard | void OPPROTO op_eval_bge(void) |
| 1342 | 7a3f1944 | bellard | {
|
| 1343 | af7bf89b | bellard | target_ulong N = FLAG_SET(PSR_NEG), V = FLAG_SET(PSR_OVF); |
| 1344 | 612b477d | bellard | |
| 1345 | cf495bcf | bellard | T2 = !(N ^ V); |
| 1346 | 7a3f1944 | bellard | } |
| 1347 | 7a3f1944 | bellard | |
| 1348 | cf495bcf | bellard | void OPPROTO op_eval_bgu(void) |
| 1349 | 7a3f1944 | bellard | {
|
| 1350 | af7bf89b | bellard | target_ulong Z = FLAG_SET(PSR_ZERO), C = FLAG_SET(PSR_CARRY); |
| 1351 | 612b477d | bellard | |
| 1352 | cf495bcf | bellard | T2 = !(C | Z); |
| 1353 | 7a3f1944 | bellard | } |
| 1354 | 7a3f1944 | bellard | |
| 1355 | cf495bcf | bellard | void OPPROTO op_eval_bcc(void) |
| 1356 | 7a3f1944 | bellard | {
|
| 1357 | af7bf89b | bellard | T2 = !FLAG_SET(PSR_CARRY); |
| 1358 | 7a3f1944 | bellard | } |
| 1359 | 7a3f1944 | bellard | |
| 1360 | cf495bcf | bellard | void OPPROTO op_eval_bpos(void) |
| 1361 | cf495bcf | bellard | {
|
| 1362 | af7bf89b | bellard | T2 = !FLAG_SET(PSR_NEG); |
| 1363 | cf495bcf | bellard | } |
| 1364 | cf495bcf | bellard | |
| 1365 | cf495bcf | bellard | void OPPROTO op_eval_bvc(void) |
| 1366 | cf495bcf | bellard | {
|
| 1367 | af7bf89b | bellard | T2 = !FLAG_SET(PSR_OVF); |
| 1368 | cf495bcf | bellard | } |
| 1369 | cf495bcf | bellard | |
| 1370 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
| 1371 | 3475187d | bellard | void OPPROTO op_eval_xbe(void) |
| 1372 | 3475187d | bellard | {
|
| 1373 | 3475187d | bellard | T2 = XFLAG_SET(PSR_ZERO); |
| 1374 | 3475187d | bellard | } |
| 1375 | e8af50a3 | bellard | |
| 1376 | 3475187d | bellard | void OPPROTO op_eval_xble(void) |
| 1377 | e8af50a3 | bellard | {
|
| 1378 | 3475187d | bellard | target_ulong Z = XFLAG_SET(PSR_ZERO), N = XFLAG_SET(PSR_NEG), V = XFLAG_SET(PSR_OVF); |
| 1379 | 3b46e624 | ths | |
| 1380 | 3475187d | bellard | T2 = Z | (N ^ V); |
| 1381 | e8af50a3 | bellard | } |
| 1382 | e8af50a3 | bellard | |
| 1383 | 3475187d | bellard | void OPPROTO op_eval_xbl(void) |
| 1384 | e8af50a3 | bellard | {
|
| 1385 | 3475187d | bellard | target_ulong N = XFLAG_SET(PSR_NEG), V = XFLAG_SET(PSR_OVF); |
| 1386 | 3475187d | bellard | |
| 1387 | 3475187d | bellard | T2 = N ^ V; |
| 1388 | e8af50a3 | bellard | } |
| 1389 | e8af50a3 | bellard | |
| 1390 | 3475187d | bellard | void OPPROTO op_eval_xbleu(void) |
| 1391 | e8af50a3 | bellard | {
|
| 1392 | 3475187d | bellard | target_ulong Z = XFLAG_SET(PSR_ZERO), C = XFLAG_SET(PSR_CARRY); |
| 1393 | 3475187d | bellard | |
| 1394 | 3475187d | bellard | T2 = C | Z; |
| 1395 | e8af50a3 | bellard | } |
| 1396 | e8af50a3 | bellard | |
| 1397 | 3475187d | bellard | void OPPROTO op_eval_xbcs(void) |
| 1398 | e8af50a3 | bellard | {
|
| 1399 | 3475187d | bellard | T2 = XFLAG_SET(PSR_CARRY); |
| 1400 | e8af50a3 | bellard | } |
| 1401 | e8af50a3 | bellard | |
| 1402 | 3475187d | bellard | void OPPROTO op_eval_xbvs(void) |
| 1403 | e8af50a3 | bellard | {
|
| 1404 | 3475187d | bellard | T2 = XFLAG_SET(PSR_OVF); |
| 1405 | e8af50a3 | bellard | } |
| 1406 | e8af50a3 | bellard | |
| 1407 | 3475187d | bellard | void OPPROTO op_eval_xbneg(void) |
| 1408 | e8af50a3 | bellard | {
|
| 1409 | 3475187d | bellard | T2 = XFLAG_SET(PSR_NEG); |
| 1410 | e8af50a3 | bellard | } |
| 1411 | e8af50a3 | bellard | |
| 1412 | 3475187d | bellard | void OPPROTO op_eval_xbne(void) |
| 1413 | e8af50a3 | bellard | {
|
| 1414 | 3475187d | bellard | T2 = !XFLAG_SET(PSR_ZERO); |
| 1415 | e8af50a3 | bellard | } |
| 1416 | e8af50a3 | bellard | |
| 1417 | 3475187d | bellard | void OPPROTO op_eval_xbg(void) |
| 1418 | e8af50a3 | bellard | {
|
| 1419 | 3475187d | bellard | target_ulong Z = XFLAG_SET(PSR_ZERO), N = XFLAG_SET(PSR_NEG), V = XFLAG_SET(PSR_OVF); |
| 1420 | 3475187d | bellard | |
| 1421 | 3475187d | bellard | T2 = !(Z | (N ^ V)); |
| 1422 | e8af50a3 | bellard | } |
| 1423 | e8af50a3 | bellard | |
| 1424 | 3475187d | bellard | void OPPROTO op_eval_xbge(void) |
| 1425 | e8af50a3 | bellard | {
|
| 1426 | 3475187d | bellard | target_ulong N = XFLAG_SET(PSR_NEG), V = XFLAG_SET(PSR_OVF); |
| 1427 | 3475187d | bellard | |
| 1428 | 3475187d | bellard | T2 = !(N ^ V); |
| 1429 | 3475187d | bellard | } |
| 1430 | 3475187d | bellard | |
| 1431 | 3475187d | bellard | void OPPROTO op_eval_xbgu(void) |
| 1432 | 3475187d | bellard | {
|
| 1433 | 3475187d | bellard | target_ulong Z = XFLAG_SET(PSR_ZERO), C = XFLAG_SET(PSR_CARRY); |
| 1434 | 3475187d | bellard | |
| 1435 | 3475187d | bellard | T2 = !(C | Z); |
| 1436 | 3475187d | bellard | } |
| 1437 | 3475187d | bellard | |
| 1438 | 3475187d | bellard | void OPPROTO op_eval_xbcc(void) |
| 1439 | 3475187d | bellard | {
|
| 1440 | 3475187d | bellard | T2 = !XFLAG_SET(PSR_CARRY); |
| 1441 | 3475187d | bellard | } |
| 1442 | 3475187d | bellard | |
| 1443 | 3475187d | bellard | void OPPROTO op_eval_xbpos(void) |
| 1444 | 3475187d | bellard | {
|
| 1445 | 3475187d | bellard | T2 = !XFLAG_SET(PSR_NEG); |
| 1446 | 3475187d | bellard | } |
| 1447 | 3475187d | bellard | |
| 1448 | 3475187d | bellard | void OPPROTO op_eval_xbvc(void) |
| 1449 | 3475187d | bellard | {
|
| 1450 | 3475187d | bellard | T2 = !XFLAG_SET(PSR_OVF); |
| 1451 | 3475187d | bellard | } |
| 1452 | 3475187d | bellard | #endif
|
| 1453 | 3475187d | bellard | |
| 1454 | 3475187d | bellard | #define FCC
|
| 1455 | 3475187d | bellard | #define FFLAG_SET(x) (env->fsr & x? 1: 0) |
| 1456 | 3475187d | bellard | #include "fbranch_template.h" |
| 1457 | 3475187d | bellard | |
| 1458 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
| 1459 | 3475187d | bellard | #define FCC _fcc1
|
| 1460 | 3475187d | bellard | #define FFLAG_SET(x) ((env->fsr & ((uint64_t)x >> 32))? 1: 0) |
| 1461 | 3475187d | bellard | #include "fbranch_template.h" |
| 1462 | 3475187d | bellard | #define FCC _fcc2
|
| 1463 | 3475187d | bellard | #define FFLAG_SET(x) ((env->fsr & ((uint64_t)x >> 34))? 1: 0) |
| 1464 | 3475187d | bellard | #include "fbranch_template.h" |
| 1465 | 3475187d | bellard | #define FCC _fcc3
|
| 1466 | 3475187d | bellard | #define FFLAG_SET(x) ((env->fsr & ((uint64_t)x >> 36))? 1: 0) |
| 1467 | 3475187d | bellard | #include "fbranch_template.h" |
| 1468 | 3475187d | bellard | #endif
|
| 1469 | 3475187d | bellard | |
| 1470 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
| 1471 | 3475187d | bellard | void OPPROTO op_eval_brz(void) |
| 1472 | 3475187d | bellard | {
|
| 1473 | 83469015 | bellard | T2 = (T0 == 0);
|
| 1474 | e8af50a3 | bellard | } |
| 1475 | e8af50a3 | bellard | |
| 1476 | 3475187d | bellard | void OPPROTO op_eval_brnz(void) |
| 1477 | e8af50a3 | bellard | {
|
| 1478 | 83469015 | bellard | T2 = (T0 != 0);
|
| 1479 | e8af50a3 | bellard | } |
| 1480 | e8af50a3 | bellard | |
| 1481 | 3475187d | bellard | void OPPROTO op_eval_brlz(void) |
| 1482 | e8af50a3 | bellard | {
|
| 1483 | 3475187d | bellard | T2 = ((int64_t)T0 < 0);
|
| 1484 | e8af50a3 | bellard | } |
| 1485 | e8af50a3 | bellard | |
| 1486 | 3475187d | bellard | void OPPROTO op_eval_brlez(void) |
| 1487 | e8af50a3 | bellard | {
|
| 1488 | 3475187d | bellard | T2 = ((int64_t)T0 <= 0);
|
| 1489 | e8af50a3 | bellard | } |
| 1490 | e8af50a3 | bellard | |
| 1491 | 3475187d | bellard | void OPPROTO op_eval_brgz(void) |
| 1492 | e8af50a3 | bellard | {
|
| 1493 | 3475187d | bellard | T2 = ((int64_t)T0 > 0);
|
| 1494 | e8af50a3 | bellard | } |
| 1495 | e8af50a3 | bellard | |
| 1496 | 3475187d | bellard | void OPPROTO op_eval_brgez(void) |
| 1497 | e8af50a3 | bellard | {
|
| 1498 | 3475187d | bellard | T2 = ((int64_t)T0 >= 0);
|
| 1499 | e8af50a3 | bellard | } |
| 1500 | e8af50a3 | bellard | |
| 1501 | 3475187d | bellard | void OPPROTO op_jmp_im64(void) |
| 1502 | 3475187d | bellard | {
|
| 1503 | 3475187d | bellard | env->pc = PARAMQ1; |
| 1504 | 3475187d | bellard | } |
| 1505 | 3475187d | bellard | |
| 1506 | 3475187d | bellard | void OPPROTO op_movq_npc_im64(void) |
| 1507 | 3475187d | bellard | {
|
| 1508 | 3475187d | bellard | env->npc = PARAMQ1; |
| 1509 | 3475187d | bellard | } |
| 1510 | 3475187d | bellard | #endif
|
| 1511 | 3475187d | bellard | |
| 1512 | cf495bcf | bellard | void OPPROTO op_jmp_im(void) |
| 1513 | cf495bcf | bellard | {
|
| 1514 | 3475187d | bellard | env->pc = (uint32_t)PARAM1; |
| 1515 | cf495bcf | bellard | } |
| 1516 | cf495bcf | bellard | |
| 1517 | cf495bcf | bellard | void OPPROTO op_movl_npc_im(void) |
| 1518 | cf495bcf | bellard | {
|
| 1519 | 3475187d | bellard | env->npc = (uint32_t)PARAM1; |
| 1520 | cf495bcf | bellard | } |
| 1521 | 7a3f1944 | bellard | |
| 1522 | cf495bcf | bellard | void OPPROTO op_movl_npc_T0(void) |
| 1523 | 7a3f1944 | bellard | {
|
| 1524 | 6ea4a6c8 | blueswir1 | env->npc = T0; |
| 1525 | 7a3f1944 | bellard | } |
| 1526 | 7a3f1944 | bellard | |
| 1527 | 0bee699e | bellard | void OPPROTO op_mov_pc_npc(void) |
| 1528 | 0bee699e | bellard | {
|
| 1529 | 0bee699e | bellard | env->pc = env->npc; |
| 1530 | 0bee699e | bellard | } |
| 1531 | 0bee699e | bellard | |
| 1532 | cf495bcf | bellard | void OPPROTO op_next_insn(void) |
| 1533 | 7a3f1944 | bellard | {
|
| 1534 | cf495bcf | bellard | env->pc = env->npc; |
| 1535 | cf495bcf | bellard | env->npc = env->npc + 4;
|
| 1536 | 7a3f1944 | bellard | } |
| 1537 | 7a3f1944 | bellard | |
| 1538 | 83469015 | bellard | void OPPROTO op_goto_tb0(void) |
| 1539 | 72cbca10 | bellard | {
|
| 1540 | 83469015 | bellard | GOTO_TB(op_goto_tb0, PARAM1, 0);
|
| 1541 | 72cbca10 | bellard | } |
| 1542 | 72cbca10 | bellard | |
| 1543 | 83469015 | bellard | void OPPROTO op_goto_tb1(void) |
| 1544 | 7a3f1944 | bellard | {
|
| 1545 | 83469015 | bellard | GOTO_TB(op_goto_tb1, PARAM1, 1);
|
| 1546 | 72cbca10 | bellard | } |
| 1547 | 72cbca10 | bellard | |
| 1548 | 83469015 | bellard | void OPPROTO op_jmp_label(void) |
| 1549 | 72cbca10 | bellard | {
|
| 1550 | 83469015 | bellard | GOTO_LABEL_PARAM(1);
|
| 1551 | 83469015 | bellard | } |
| 1552 | 83469015 | bellard | |
| 1553 | 83469015 | bellard | void OPPROTO op_jnz_T2_label(void) |
| 1554 | 83469015 | bellard | {
|
| 1555 | 83469015 | bellard | if (T2)
|
| 1556 | 83469015 | bellard | GOTO_LABEL_PARAM(1);
|
| 1557 | cf495bcf | bellard | FORCE_RET(); |
| 1558 | 7a3f1944 | bellard | } |
| 1559 | 7a3f1944 | bellard | |
| 1560 | 83469015 | bellard | void OPPROTO op_jz_T2_label(void) |
| 1561 | 7a3f1944 | bellard | {
|
| 1562 | 83469015 | bellard | if (!T2)
|
| 1563 | 83469015 | bellard | GOTO_LABEL_PARAM(1);
|
| 1564 | cf495bcf | bellard | FORCE_RET(); |
| 1565 | 7a3f1944 | bellard | } |
| 1566 | 72cbca10 | bellard | |
| 1567 | 658138bc | bellard | void OPPROTO op_flush_T0(void) |
| 1568 | 658138bc | bellard | {
|
| 1569 | 658138bc | bellard | helper_flush(T0); |
| 1570 | 658138bc | bellard | } |
| 1571 | e8af50a3 | bellard | |
| 1572 | 417454b0 | blueswir1 | void OPPROTO op_clear_ieee_excp_and_FTT(void) |
| 1573 | 417454b0 | blueswir1 | {
|
| 1574 | 417454b0 | blueswir1 | env->fsr &= ~(FSR_FTT_MASK | FSR_CEXC_MASK);; |
| 1575 | 417454b0 | blueswir1 | } |
| 1576 | 417454b0 | blueswir1 | |
| 1577 | 65ce8c2f | bellard | #define F_OP(name, p) void OPPROTO op_f##name##p(void) |
| 1578 | 65ce8c2f | bellard | |
| 1579 | 65ce8c2f | bellard | #define F_BINOP(name) \
|
| 1580 | 65ce8c2f | bellard | F_OP(name, s) \ |
| 1581 | 65ce8c2f | bellard | { \
|
| 1582 | 0f8a249a | blueswir1 | set_float_exception_flags(0, &env->fp_status); \
|
| 1583 | 65ce8c2f | bellard | FT0 = float32_ ## name (FT0, FT1, &env->fp_status); \ |
| 1584 | 0f8a249a | blueswir1 | check_ieee_exceptions(); \ |
| 1585 | 65ce8c2f | bellard | } \ |
| 1586 | 65ce8c2f | bellard | F_OP(name, d) \ |
| 1587 | 65ce8c2f | bellard | { \
|
| 1588 | 0f8a249a | blueswir1 | set_float_exception_flags(0, &env->fp_status); \
|
| 1589 | 65ce8c2f | bellard | DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \ |
| 1590 | 0f8a249a | blueswir1 | check_ieee_exceptions(); \ |
| 1591 | 65ce8c2f | bellard | } |
| 1592 | e8af50a3 | bellard | |
| 1593 | 65ce8c2f | bellard | F_BINOP(add); |
| 1594 | 65ce8c2f | bellard | F_BINOP(sub); |
| 1595 | 65ce8c2f | bellard | F_BINOP(mul); |
| 1596 | 65ce8c2f | bellard | F_BINOP(div); |
| 1597 | 65ce8c2f | bellard | #undef F_BINOP
|
| 1598 | e8af50a3 | bellard | |
| 1599 | e8af50a3 | bellard | void OPPROTO op_fsmuld(void) |
| 1600 | e8af50a3 | bellard | {
|
| 1601 | 417454b0 | blueswir1 | set_float_exception_flags(0, &env->fp_status);
|
| 1602 | 65ce8c2f | bellard | DT0 = float64_mul(float32_to_float64(FT0, &env->fp_status), |
| 1603 | 65ce8c2f | bellard | float32_to_float64(FT1, &env->fp_status), |
| 1604 | 65ce8c2f | bellard | &env->fp_status); |
| 1605 | 417454b0 | blueswir1 | check_ieee_exceptions(); |
| 1606 | e8af50a3 | bellard | } |
| 1607 | e8af50a3 | bellard | |
| 1608 | 65ce8c2f | bellard | #define F_HELPER(name) \
|
| 1609 | 65ce8c2f | bellard | F_OP(name, s) \ |
| 1610 | 65ce8c2f | bellard | { \
|
| 1611 | 65ce8c2f | bellard | do_f##name##s(); \ |
| 1612 | 65ce8c2f | bellard | } \ |
| 1613 | 65ce8c2f | bellard | F_OP(name, d) \ |
| 1614 | 65ce8c2f | bellard | { \
|
| 1615 | 65ce8c2f | bellard | do_f##name##d(); \ |
| 1616 | 65ce8c2f | bellard | } |
| 1617 | e8af50a3 | bellard | |
| 1618 | 65ce8c2f | bellard | F_HELPER(sqrt); |
| 1619 | e8af50a3 | bellard | |
| 1620 | 65ce8c2f | bellard | F_OP(neg, s) |
| 1621 | e8af50a3 | bellard | {
|
| 1622 | 65ce8c2f | bellard | FT0 = float32_chs(FT1); |
| 1623 | e8af50a3 | bellard | } |
| 1624 | e8af50a3 | bellard | |
| 1625 | 65ce8c2f | bellard | F_OP(abs, s) |
| 1626 | e8af50a3 | bellard | {
|
| 1627 | 65ce8c2f | bellard | do_fabss(); |
| 1628 | e8af50a3 | bellard | } |
| 1629 | e8af50a3 | bellard | |
| 1630 | 65ce8c2f | bellard | F_HELPER(cmp); |
| 1631 | 417454b0 | blueswir1 | F_HELPER(cmpe); |
| 1632 | e8af50a3 | bellard | |
| 1633 | 65ce8c2f | bellard | #ifdef TARGET_SPARC64
|
| 1634 | 65ce8c2f | bellard | F_OP(neg, d) |
| 1635 | e8af50a3 | bellard | {
|
| 1636 | 65ce8c2f | bellard | DT0 = float64_chs(DT1); |
| 1637 | e8af50a3 | bellard | } |
| 1638 | e8af50a3 | bellard | |
| 1639 | 65ce8c2f | bellard | F_OP(abs, d) |
| 1640 | e8af50a3 | bellard | {
|
| 1641 | 65ce8c2f | bellard | do_fabsd(); |
| 1642 | e8af50a3 | bellard | } |
| 1643 | e8af50a3 | bellard | |
| 1644 | 3475187d | bellard | void OPPROTO op_fcmps_fcc1(void) |
| 1645 | 3475187d | bellard | {
|
| 1646 | 3475187d | bellard | do_fcmps_fcc1(); |
| 1647 | 3475187d | bellard | } |
| 1648 | 3475187d | bellard | |
| 1649 | 3475187d | bellard | void OPPROTO op_fcmpd_fcc1(void) |
| 1650 | 3475187d | bellard | {
|
| 1651 | 3475187d | bellard | do_fcmpd_fcc1(); |
| 1652 | 3475187d | bellard | } |
| 1653 | 3475187d | bellard | |
| 1654 | 3475187d | bellard | void OPPROTO op_fcmps_fcc2(void) |
| 1655 | 3475187d | bellard | {
|
| 1656 | 3475187d | bellard | do_fcmps_fcc2(); |
| 1657 | 3475187d | bellard | } |
| 1658 | 3475187d | bellard | |
| 1659 | 3475187d | bellard | void OPPROTO op_fcmpd_fcc2(void) |
| 1660 | 3475187d | bellard | {
|
| 1661 | 3475187d | bellard | do_fcmpd_fcc2(); |
| 1662 | 3475187d | bellard | } |
| 1663 | 3475187d | bellard | |
| 1664 | 3475187d | bellard | void OPPROTO op_fcmps_fcc3(void) |
| 1665 | 3475187d | bellard | {
|
| 1666 | 3475187d | bellard | do_fcmps_fcc3(); |
| 1667 | 3475187d | bellard | } |
| 1668 | 3475187d | bellard | |
| 1669 | 3475187d | bellard | void OPPROTO op_fcmpd_fcc3(void) |
| 1670 | 3475187d | bellard | {
|
| 1671 | 3475187d | bellard | do_fcmpd_fcc3(); |
| 1672 | 3475187d | bellard | } |
| 1673 | 417454b0 | blueswir1 | |
| 1674 | 417454b0 | blueswir1 | void OPPROTO op_fcmpes_fcc1(void) |
| 1675 | 417454b0 | blueswir1 | {
|
| 1676 | 417454b0 | blueswir1 | do_fcmpes_fcc1(); |
| 1677 | 417454b0 | blueswir1 | } |
| 1678 | 417454b0 | blueswir1 | |
| 1679 | 417454b0 | blueswir1 | void OPPROTO op_fcmped_fcc1(void) |
| 1680 | 417454b0 | blueswir1 | {
|
| 1681 | 417454b0 | blueswir1 | do_fcmped_fcc1(); |
| 1682 | 417454b0 | blueswir1 | } |
| 1683 | 417454b0 | blueswir1 | |
| 1684 | 417454b0 | blueswir1 | void OPPROTO op_fcmpes_fcc2(void) |
| 1685 | 417454b0 | blueswir1 | {
|
| 1686 | 417454b0 | blueswir1 | do_fcmpes_fcc2(); |
| 1687 | 417454b0 | blueswir1 | } |
| 1688 | 417454b0 | blueswir1 | |
| 1689 | 417454b0 | blueswir1 | void OPPROTO op_fcmped_fcc2(void) |
| 1690 | 417454b0 | blueswir1 | {
|
| 1691 | 417454b0 | blueswir1 | do_fcmped_fcc2(); |
| 1692 | 417454b0 | blueswir1 | } |
| 1693 | 417454b0 | blueswir1 | |
| 1694 | 417454b0 | blueswir1 | void OPPROTO op_fcmpes_fcc3(void) |
| 1695 | 417454b0 | blueswir1 | {
|
| 1696 | 417454b0 | blueswir1 | do_fcmpes_fcc3(); |
| 1697 | 417454b0 | blueswir1 | } |
| 1698 | 417454b0 | blueswir1 | |
| 1699 | 417454b0 | blueswir1 | void OPPROTO op_fcmped_fcc3(void) |
| 1700 | 417454b0 | blueswir1 | {
|
| 1701 | 417454b0 | blueswir1 | do_fcmped_fcc3(); |
| 1702 | 417454b0 | blueswir1 | } |
| 1703 | 417454b0 | blueswir1 | |
| 1704 | 3475187d | bellard | #endif
|
| 1705 | 3475187d | bellard | |
| 1706 | 65ce8c2f | bellard | /* Integer to float conversion. */
|
| 1707 | a0c4cb4a | bellard | #ifdef USE_INT_TO_FLOAT_HELPERS
|
| 1708 | 65ce8c2f | bellard | F_HELPER(ito); |
| 1709 | a0c4cb4a | bellard | #else
|
| 1710 | 65ce8c2f | bellard | F_OP(ito, s) |
| 1711 | a0c4cb4a | bellard | {
|
| 1712 | 417454b0 | blueswir1 | set_float_exception_flags(0, &env->fp_status);
|
| 1713 | 65ce8c2f | bellard | FT0 = int32_to_float32(*((int32_t *)&FT1), &env->fp_status); |
| 1714 | 417454b0 | blueswir1 | check_ieee_exceptions(); |
| 1715 | e8af50a3 | bellard | } |
| 1716 | e8af50a3 | bellard | |
| 1717 | 65ce8c2f | bellard | F_OP(ito, d) |
| 1718 | e8af50a3 | bellard | {
|
| 1719 | 417454b0 | blueswir1 | set_float_exception_flags(0, &env->fp_status);
|
| 1720 | 65ce8c2f | bellard | DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status); |
| 1721 | 417454b0 | blueswir1 | check_ieee_exceptions(); |
| 1722 | e8af50a3 | bellard | } |
| 1723 | 3475187d | bellard | |
| 1724 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
| 1725 | 65ce8c2f | bellard | F_OP(xto, s) |
| 1726 | 3475187d | bellard | {
|
| 1727 | 417454b0 | blueswir1 | set_float_exception_flags(0, &env->fp_status);
|
| 1728 | 65ce8c2f | bellard | FT0 = int64_to_float32(*((int64_t *)&DT1), &env->fp_status); |
| 1729 | 417454b0 | blueswir1 | check_ieee_exceptions(); |
| 1730 | 3475187d | bellard | } |
| 1731 | 3475187d | bellard | |
| 1732 | 65ce8c2f | bellard | F_OP(xto, d) |
| 1733 | 3475187d | bellard | {
|
| 1734 | 417454b0 | blueswir1 | set_float_exception_flags(0, &env->fp_status);
|
| 1735 | 65ce8c2f | bellard | DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status); |
| 1736 | 417454b0 | blueswir1 | check_ieee_exceptions(); |
| 1737 | 3475187d | bellard | } |
| 1738 | 3475187d | bellard | #endif
|
| 1739 | a0c4cb4a | bellard | #endif
|
| 1740 | 65ce8c2f | bellard | #undef F_HELPER
|
| 1741 | a0c4cb4a | bellard | |
| 1742 | 65ce8c2f | bellard | /* floating point conversion */
|
| 1743 | a0c4cb4a | bellard | void OPPROTO op_fdtos(void) |
| 1744 | a0c4cb4a | bellard | {
|
| 1745 | 417454b0 | blueswir1 | set_float_exception_flags(0, &env->fp_status);
|
| 1746 | 65ce8c2f | bellard | FT0 = float64_to_float32(DT1, &env->fp_status); |
| 1747 | 417454b0 | blueswir1 | check_ieee_exceptions(); |
| 1748 | a0c4cb4a | bellard | } |
| 1749 | e8af50a3 | bellard | |
| 1750 | e8af50a3 | bellard | void OPPROTO op_fstod(void) |
| 1751 | e8af50a3 | bellard | {
|
| 1752 | 417454b0 | blueswir1 | set_float_exception_flags(0, &env->fp_status);
|
| 1753 | 65ce8c2f | bellard | DT0 = float32_to_float64(FT1, &env->fp_status); |
| 1754 | 417454b0 | blueswir1 | check_ieee_exceptions(); |
| 1755 | e8af50a3 | bellard | } |
| 1756 | e8af50a3 | bellard | |
| 1757 | 65ce8c2f | bellard | /* Float to integer conversion. */
|
| 1758 | e8af50a3 | bellard | void OPPROTO op_fstoi(void) |
| 1759 | e8af50a3 | bellard | {
|
| 1760 | 417454b0 | blueswir1 | set_float_exception_flags(0, &env->fp_status);
|
| 1761 | bd59780c | ths | *((int32_t *)&FT0) = float32_to_int32_round_to_zero(FT1, &env->fp_status); |
| 1762 | 417454b0 | blueswir1 | check_ieee_exceptions(); |
| 1763 | e8af50a3 | bellard | } |
| 1764 | e8af50a3 | bellard | |
| 1765 | e8af50a3 | bellard | void OPPROTO op_fdtoi(void) |
| 1766 | e8af50a3 | bellard | {
|
| 1767 | 417454b0 | blueswir1 | set_float_exception_flags(0, &env->fp_status);
|
| 1768 | bd59780c | ths | *((int32_t *)&FT0) = float64_to_int32_round_to_zero(DT1, &env->fp_status); |
| 1769 | 417454b0 | blueswir1 | check_ieee_exceptions(); |
| 1770 | e8af50a3 | bellard | } |
| 1771 | e8af50a3 | bellard | |
| 1772 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
| 1773 | 3475187d | bellard | void OPPROTO op_fstox(void) |
| 1774 | 3475187d | bellard | {
|
| 1775 | 417454b0 | blueswir1 | set_float_exception_flags(0, &env->fp_status);
|
| 1776 | bd59780c | ths | *((int64_t *)&DT0) = float32_to_int64_round_to_zero(FT1, &env->fp_status); |
| 1777 | 417454b0 | blueswir1 | check_ieee_exceptions(); |
| 1778 | 3475187d | bellard | } |
| 1779 | 3475187d | bellard | |
| 1780 | 3475187d | bellard | void OPPROTO op_fdtox(void) |
| 1781 | 3475187d | bellard | {
|
| 1782 | 417454b0 | blueswir1 | set_float_exception_flags(0, &env->fp_status);
|
| 1783 | bd59780c | ths | *((int64_t *)&DT0) = float64_to_int64_round_to_zero(DT1, &env->fp_status); |
| 1784 | 417454b0 | blueswir1 | check_ieee_exceptions(); |
| 1785 | 3475187d | bellard | } |
| 1786 | 3475187d | bellard | |
| 1787 | 3475187d | bellard | void OPPROTO op_fmovs_cc(void) |
| 1788 | 3475187d | bellard | {
|
| 1789 | 3475187d | bellard | if (T2)
|
| 1790 | 0f8a249a | blueswir1 | FT0 = FT1; |
| 1791 | 3475187d | bellard | } |
| 1792 | 3475187d | bellard | |
| 1793 | 3475187d | bellard | void OPPROTO op_fmovd_cc(void) |
| 1794 | 3475187d | bellard | {
|
| 1795 | 3475187d | bellard | if (T2)
|
| 1796 | 0f8a249a | blueswir1 | DT0 = DT1; |
| 1797 | 3475187d | bellard | } |
| 1798 | 3475187d | bellard | |
| 1799 | 3475187d | bellard | void OPPROTO op_mov_cc(void) |
| 1800 | 3475187d | bellard | {
|
| 1801 | 3475187d | bellard | if (T2)
|
| 1802 | 0f8a249a | blueswir1 | T0 = T1; |
| 1803 | 3475187d | bellard | } |
| 1804 | 3475187d | bellard | |
| 1805 | 3475187d | bellard | void OPPROTO op_flushw(void) |
| 1806 | 3475187d | bellard | {
|
| 1807 | 3475187d | bellard | if (env->cansave != NWINDOWS - 2) { |
| 1808 | 5fafdf24 | ths | raise_exception(TT_SPILL | (env->otherwin != 0 ?
|
| 1809 | 0f8a249a | blueswir1 | (TT_WOTHER | ((env->wstate & 0x38) >> 1)): |
| 1810 | 0f8a249a | blueswir1 | ((env->wstate & 0x7) << 2))); |
| 1811 | 3475187d | bellard | } |
| 1812 | 3475187d | bellard | } |
| 1813 | 3475187d | bellard | |
| 1814 | 3475187d | bellard | void OPPROTO op_saved(void) |
| 1815 | 3475187d | bellard | {
|
| 1816 | 3475187d | bellard | env->cansave++; |
| 1817 | 3475187d | bellard | if (env->otherwin == 0) |
| 1818 | 0f8a249a | blueswir1 | env->canrestore--; |
| 1819 | 725cb90b | bellard | else
|
| 1820 | 0f8a249a | blueswir1 | env->otherwin--; |
| 1821 | 725cb90b | bellard | FORCE_RET(); |
| 1822 | 3475187d | bellard | } |
| 1823 | 3475187d | bellard | |
| 1824 | 3475187d | bellard | void OPPROTO op_restored(void) |
| 1825 | 3475187d | bellard | {
|
| 1826 | 3475187d | bellard | env->canrestore++; |
| 1827 | 3475187d | bellard | if (env->cleanwin < NWINDOWS - 1) |
| 1828 | 0f8a249a | blueswir1 | env->cleanwin++; |
| 1829 | 3475187d | bellard | if (env->otherwin == 0) |
| 1830 | 0f8a249a | blueswir1 | env->cansave--; |
| 1831 | 3475187d | bellard | else
|
| 1832 | 0f8a249a | blueswir1 | env->otherwin--; |
| 1833 | 725cb90b | bellard | FORCE_RET(); |
| 1834 | 3475187d | bellard | } |
| 1835 | 3475187d | bellard | |
| 1836 | 3475187d | bellard | void OPPROTO op_popc(void) |
| 1837 | 3475187d | bellard | {
|
| 1838 | 3475187d | bellard | do_popc(); |
| 1839 | 3475187d | bellard | } |
| 1840 | 3475187d | bellard | |
| 1841 | 3475187d | bellard | void OPPROTO op_done(void) |
| 1842 | 3475187d | bellard | {
|
| 1843 | 83469015 | bellard | do_done(); |
| 1844 | 3475187d | bellard | } |
| 1845 | 3475187d | bellard | |
| 1846 | 3475187d | bellard | void OPPROTO op_retry(void) |
| 1847 | 3475187d | bellard | {
|
| 1848 | 83469015 | bellard | do_retry(); |
| 1849 | 3475187d | bellard | } |
| 1850 | 3475187d | bellard | |
| 1851 | 3475187d | bellard | void OPPROTO op_sir(void) |
| 1852 | 3475187d | bellard | {
|
| 1853 | e9ebed4d | blueswir1 | T0 = 0; // XXX |
| 1854 | 3475187d | bellard | } |
| 1855 | 3475187d | bellard | |
| 1856 | 3475187d | bellard | void OPPROTO op_ld_asi_reg()
|
| 1857 | 3475187d | bellard | {
|
| 1858 | 3475187d | bellard | T0 += PARAM1; |
| 1859 | 3475187d | bellard | helper_ld_asi(env->asi, PARAM2, PARAM3); |
| 1860 | 3475187d | bellard | } |
| 1861 | 3475187d | bellard | |
| 1862 | 3475187d | bellard | void OPPROTO op_st_asi_reg()
|
| 1863 | 3475187d | bellard | {
|
| 1864 | 3475187d | bellard | T0 += PARAM1; |
| 1865 | 81ad8ba2 | blueswir1 | helper_st_asi(env->asi, PARAM2); |
| 1866 | 81ad8ba2 | blueswir1 | } |
| 1867 | 81ad8ba2 | blueswir1 | |
| 1868 | 3391c818 | blueswir1 | void OPPROTO op_ldf_asi_reg()
|
| 1869 | 3391c818 | blueswir1 | {
|
| 1870 | 3391c818 | blueswir1 | T0 += PARAM1; |
| 1871 | 3391c818 | blueswir1 | helper_ldf_asi(env->asi, PARAM2, PARAM3); |
| 1872 | 3391c818 | blueswir1 | } |
| 1873 | 3391c818 | blueswir1 | |
| 1874 | 3391c818 | blueswir1 | void OPPROTO op_stf_asi_reg()
|
| 1875 | 3391c818 | blueswir1 | {
|
| 1876 | 3391c818 | blueswir1 | T0 += PARAM1; |
| 1877 | 3391c818 | blueswir1 | helper_stf_asi(env->asi, PARAM2, PARAM3); |
| 1878 | 3391c818 | blueswir1 | } |
| 1879 | 3391c818 | blueswir1 | |
| 1880 | 3391c818 | blueswir1 | void OPPROTO op_ldf_asi()
|
| 1881 | 3391c818 | blueswir1 | {
|
| 1882 | 3391c818 | blueswir1 | helper_ldf_asi(PARAM1, PARAM2, PARAM3); |
| 1883 | 3391c818 | blueswir1 | } |
| 1884 | 3391c818 | blueswir1 | |
| 1885 | 3391c818 | blueswir1 | void OPPROTO op_stf_asi()
|
| 1886 | 3391c818 | blueswir1 | {
|
| 1887 | 3391c818 | blueswir1 | helper_stf_asi(PARAM1, PARAM2, PARAM3); |
| 1888 | 3391c818 | blueswir1 | } |
| 1889 | 3391c818 | blueswir1 | |
| 1890 | 81ad8ba2 | blueswir1 | void OPPROTO op_ldstub_asi_reg() /* XXX: should be atomically */ |
| 1891 | 81ad8ba2 | blueswir1 | {
|
| 1892 | 81ad8ba2 | blueswir1 | target_ulong tmp; |
| 1893 | 81ad8ba2 | blueswir1 | |
| 1894 | 81ad8ba2 | blueswir1 | T0 += PARAM1; |
| 1895 | 81ad8ba2 | blueswir1 | helper_ld_asi(env->asi, 1, 0); |
| 1896 | 81ad8ba2 | blueswir1 | tmp = T1; |
| 1897 | 81ad8ba2 | blueswir1 | T1 = 0xff;
|
| 1898 | 81ad8ba2 | blueswir1 | helper_st_asi(env->asi, 1);
|
| 1899 | 81ad8ba2 | blueswir1 | T1 = tmp; |
| 1900 | 81ad8ba2 | blueswir1 | } |
| 1901 | 81ad8ba2 | blueswir1 | |
| 1902 | 81ad8ba2 | blueswir1 | void OPPROTO op_swap_asi_reg() /* XXX: should be atomically */ |
| 1903 | 81ad8ba2 | blueswir1 | {
|
| 1904 | 81ad8ba2 | blueswir1 | target_ulong tmp1, tmp2; |
| 1905 | 81ad8ba2 | blueswir1 | |
| 1906 | 81ad8ba2 | blueswir1 | T0 += PARAM1; |
| 1907 | 81ad8ba2 | blueswir1 | tmp1 = T1; |
| 1908 | 81ad8ba2 | blueswir1 | helper_ld_asi(env->asi, 4, 0); |
| 1909 | 81ad8ba2 | blueswir1 | tmp2 = T1; |
| 1910 | 81ad8ba2 | blueswir1 | T1 = tmp1; |
| 1911 | 81ad8ba2 | blueswir1 | helper_st_asi(env->asi, 4);
|
| 1912 | 81ad8ba2 | blueswir1 | T1 = tmp2; |
| 1913 | 81ad8ba2 | blueswir1 | } |
| 1914 | 81ad8ba2 | blueswir1 | |
| 1915 | 81ad8ba2 | blueswir1 | void OPPROTO op_ldda_asi()
|
| 1916 | 81ad8ba2 | blueswir1 | {
|
| 1917 | 81ad8ba2 | blueswir1 | helper_ld_asi(PARAM1, 8, 0); |
| 1918 | 81ad8ba2 | blueswir1 | T0 = T1 & 0xffffffffUL;
|
| 1919 | 81ad8ba2 | blueswir1 | T1 >>= 32;
|
| 1920 | 81ad8ba2 | blueswir1 | } |
| 1921 | 81ad8ba2 | blueswir1 | |
| 1922 | 81ad8ba2 | blueswir1 | void OPPROTO op_ldda_asi_reg()
|
| 1923 | 81ad8ba2 | blueswir1 | {
|
| 1924 | 81ad8ba2 | blueswir1 | T0 += PARAM1; |
| 1925 | 81ad8ba2 | blueswir1 | helper_ld_asi(env->asi, 8, 0); |
| 1926 | 81ad8ba2 | blueswir1 | T0 = T1 & 0xffffffffUL;
|
| 1927 | 81ad8ba2 | blueswir1 | T1 >>= 32;
|
| 1928 | 81ad8ba2 | blueswir1 | } |
| 1929 | 81ad8ba2 | blueswir1 | |
| 1930 | 81ad8ba2 | blueswir1 | void OPPROTO op_stda_asi()
|
| 1931 | 81ad8ba2 | blueswir1 | {
|
| 1932 | 81ad8ba2 | blueswir1 | T1 <<= 32;
|
| 1933 | 81ad8ba2 | blueswir1 | T1 += T2 & 0xffffffffUL;
|
| 1934 | 81ad8ba2 | blueswir1 | helper_st_asi(PARAM1, 8);
|
| 1935 | 81ad8ba2 | blueswir1 | } |
| 1936 | 81ad8ba2 | blueswir1 | |
| 1937 | 81ad8ba2 | blueswir1 | void OPPROTO op_stda_asi_reg()
|
| 1938 | 81ad8ba2 | blueswir1 | {
|
| 1939 | 81ad8ba2 | blueswir1 | T0 += PARAM1; |
| 1940 | 81ad8ba2 | blueswir1 | T1 <<= 32;
|
| 1941 | 81ad8ba2 | blueswir1 | T1 += T2 & 0xffffffffUL;
|
| 1942 | 81ad8ba2 | blueswir1 | helper_st_asi(env->asi, 8);
|
| 1943 | 81ad8ba2 | blueswir1 | } |
| 1944 | 81ad8ba2 | blueswir1 | |
| 1945 | 81ad8ba2 | blueswir1 | void OPPROTO op_cas_asi() /* XXX: should be atomically */ |
| 1946 | 81ad8ba2 | blueswir1 | {
|
| 1947 | 81ad8ba2 | blueswir1 | target_ulong tmp; |
| 1948 | 81ad8ba2 | blueswir1 | |
| 1949 | 81ad8ba2 | blueswir1 | tmp = T1 & 0xffffffffUL;
|
| 1950 | 81ad8ba2 | blueswir1 | helper_ld_asi(PARAM1, 4, 0); |
| 1951 | 81ad8ba2 | blueswir1 | if (tmp == T1) {
|
| 1952 | 81ad8ba2 | blueswir1 | tmp = T1; |
| 1953 | 81ad8ba2 | blueswir1 | T1 = T2 & 0xffffffffUL;
|
| 1954 | 81ad8ba2 | blueswir1 | helper_st_asi(PARAM1, 4);
|
| 1955 | 81ad8ba2 | blueswir1 | T1 = tmp; |
| 1956 | 81ad8ba2 | blueswir1 | } |
| 1957 | 81ad8ba2 | blueswir1 | T1 &= 0xffffffffUL;
|
| 1958 | 81ad8ba2 | blueswir1 | } |
| 1959 | 81ad8ba2 | blueswir1 | |
| 1960 | 81ad8ba2 | blueswir1 | void OPPROTO op_cas_asi_reg() /* XXX: should be atomically */ |
| 1961 | 81ad8ba2 | blueswir1 | {
|
| 1962 | 81ad8ba2 | blueswir1 | target_ulong tmp; |
| 1963 | 81ad8ba2 | blueswir1 | |
| 1964 | 81ad8ba2 | blueswir1 | T0 += PARAM1; |
| 1965 | 81ad8ba2 | blueswir1 | tmp = T1 & 0xffffffffUL;
|
| 1966 | 81ad8ba2 | blueswir1 | helper_ld_asi(env->asi, 4, 0); |
| 1967 | 81ad8ba2 | blueswir1 | if (tmp == T1) {
|
| 1968 | 81ad8ba2 | blueswir1 | tmp = T1; |
| 1969 | 81ad8ba2 | blueswir1 | T1 = T2 & 0xffffffffUL;
|
| 1970 | 81ad8ba2 | blueswir1 | helper_st_asi(env->asi, 4);
|
| 1971 | 81ad8ba2 | blueswir1 | T1 = tmp; |
| 1972 | 81ad8ba2 | blueswir1 | } |
| 1973 | 81ad8ba2 | blueswir1 | T1 &= 0xffffffffUL;
|
| 1974 | 81ad8ba2 | blueswir1 | } |
| 1975 | 81ad8ba2 | blueswir1 | |
| 1976 | 81ad8ba2 | blueswir1 | void OPPROTO op_casx_asi() /* XXX: should be atomically */ |
| 1977 | 81ad8ba2 | blueswir1 | {
|
| 1978 | 81ad8ba2 | blueswir1 | target_ulong tmp; |
| 1979 | 81ad8ba2 | blueswir1 | |
| 1980 | 81ad8ba2 | blueswir1 | tmp = T1; |
| 1981 | 81ad8ba2 | blueswir1 | helper_ld_asi(PARAM1, 8, 0); |
| 1982 | 81ad8ba2 | blueswir1 | if (tmp == T1) {
|
| 1983 | 81ad8ba2 | blueswir1 | tmp = T1; |
| 1984 | 81ad8ba2 | blueswir1 | T1 = T2; |
| 1985 | 81ad8ba2 | blueswir1 | helper_st_asi(PARAM1, 8);
|
| 1986 | 81ad8ba2 | blueswir1 | T1 = tmp; |
| 1987 | 81ad8ba2 | blueswir1 | } |
| 1988 | 81ad8ba2 | blueswir1 | } |
| 1989 | 81ad8ba2 | blueswir1 | |
| 1990 | 81ad8ba2 | blueswir1 | void OPPROTO op_casx_asi_reg() /* XXX: should be atomically */ |
| 1991 | 81ad8ba2 | blueswir1 | {
|
| 1992 | 81ad8ba2 | blueswir1 | target_ulong tmp; |
| 1993 | 81ad8ba2 | blueswir1 | |
| 1994 | 81ad8ba2 | blueswir1 | T0 += PARAM1; |
| 1995 | 81ad8ba2 | blueswir1 | tmp = T1; |
| 1996 | 81ad8ba2 | blueswir1 | helper_ld_asi(env->asi, 8, 0); |
| 1997 | 81ad8ba2 | blueswir1 | if (tmp == T1) {
|
| 1998 | 81ad8ba2 | blueswir1 | tmp = T1; |
| 1999 | 81ad8ba2 | blueswir1 | T1 = T2; |
| 2000 | 81ad8ba2 | blueswir1 | helper_st_asi(env->asi, 8);
|
| 2001 | 81ad8ba2 | blueswir1 | T1 = tmp; |
| 2002 | 81ad8ba2 | blueswir1 | } |
| 2003 | 3475187d | bellard | } |
| 2004 | 3475187d | bellard | #endif
|
| 2005 | 3475187d | bellard | |
| 2006 | 81ad8ba2 | blueswir1 | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
| 2007 | e8af50a3 | bellard | void OPPROTO op_ld_asi()
|
| 2008 | e8af50a3 | bellard | {
|
| 2009 | e8af50a3 | bellard | helper_ld_asi(PARAM1, PARAM2, PARAM3); |
| 2010 | e8af50a3 | bellard | } |
| 2011 | e8af50a3 | bellard | |
| 2012 | e8af50a3 | bellard | void OPPROTO op_st_asi()
|
| 2013 | e8af50a3 | bellard | {
|
| 2014 | 81ad8ba2 | blueswir1 | helper_st_asi(PARAM1, PARAM2); |
| 2015 | e8af50a3 | bellard | } |
| 2016 | e8af50a3 | bellard | |
| 2017 | 81ad8ba2 | blueswir1 | void OPPROTO op_ldstub_asi() /* XXX: should be atomically */ |
| 2018 | 81ad8ba2 | blueswir1 | {
|
| 2019 | 81ad8ba2 | blueswir1 | target_ulong tmp; |
| 2020 | 81ad8ba2 | blueswir1 | |
| 2021 | 81ad8ba2 | blueswir1 | helper_ld_asi(PARAM1, 1, 0); |
| 2022 | 81ad8ba2 | blueswir1 | tmp = T1; |
| 2023 | 81ad8ba2 | blueswir1 | T1 = 0xff;
|
| 2024 | 81ad8ba2 | blueswir1 | helper_st_asi(PARAM1, 1);
|
| 2025 | 81ad8ba2 | blueswir1 | T1 = tmp; |
| 2026 | 81ad8ba2 | blueswir1 | } |
| 2027 | 81ad8ba2 | blueswir1 | |
| 2028 | 81ad8ba2 | blueswir1 | void OPPROTO op_swap_asi() /* XXX: should be atomically */ |
| 2029 | 81ad8ba2 | blueswir1 | {
|
| 2030 | 81ad8ba2 | blueswir1 | target_ulong tmp1, tmp2; |
| 2031 | 81ad8ba2 | blueswir1 | |
| 2032 | 81ad8ba2 | blueswir1 | tmp1 = T1; |
| 2033 | 81ad8ba2 | blueswir1 | helper_ld_asi(PARAM1, 4, 0); |
| 2034 | 81ad8ba2 | blueswir1 | tmp2 = T1; |
| 2035 | 81ad8ba2 | blueswir1 | T1 = tmp1; |
| 2036 | 81ad8ba2 | blueswir1 | helper_st_asi(PARAM1, 4);
|
| 2037 | 81ad8ba2 | blueswir1 | T1 = tmp2; |
| 2038 | 81ad8ba2 | blueswir1 | } |
| 2039 | 81ad8ba2 | blueswir1 | #endif
|
| 2040 | 81ad8ba2 | blueswir1 | |
| 2041 | 725cb90b | bellard | #ifdef TARGET_SPARC64
|
| 2042 | e9ebed4d | blueswir1 | // This function uses non-native bit order
|
| 2043 | e9ebed4d | blueswir1 | #define GET_FIELD(X, FROM, TO) \
|
| 2044 | e9ebed4d | blueswir1 | ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1)) |
| 2045 | e9ebed4d | blueswir1 | |
| 2046 | e9ebed4d | blueswir1 | // This function uses the order in the manuals, i.e. bit 0 is 2^0
|
| 2047 | e9ebed4d | blueswir1 | #define GET_FIELD_SP(X, FROM, TO) \
|
| 2048 | e9ebed4d | blueswir1 | GET_FIELD(X, 63 - (TO), 63 - (FROM)) |
| 2049 | e9ebed4d | blueswir1 | |
| 2050 | e9ebed4d | blueswir1 | void OPPROTO op_array8()
|
| 2051 | e9ebed4d | blueswir1 | {
|
| 2052 | e9ebed4d | blueswir1 | T0 = (GET_FIELD_SP(T0, 60, 63) << (17 + 2 * T1)) | |
| 2053 | e9ebed4d | blueswir1 | (GET_FIELD_SP(T0, 39, 39 + T1 - 1) << (17 + T1)) | |
| 2054 | e9ebed4d | blueswir1 | (GET_FIELD_SP(T0, 17 + T1 - 1, 17) << 17) | |
| 2055 | e9ebed4d | blueswir1 | (GET_FIELD_SP(T0, 56, 59) << 13) | (GET_FIELD_SP(T0, 35, 38) << 9) | |
| 2056 | e9ebed4d | blueswir1 | (GET_FIELD_SP(T0, 13, 16) << 5) | (((T0 >> 55) & 1) << 4) | |
| 2057 | e9ebed4d | blueswir1 | (GET_FIELD_SP(T0, 33, 34) << 2) | GET_FIELD_SP(T0, 11, 12); |
| 2058 | e9ebed4d | blueswir1 | } |
| 2059 | e9ebed4d | blueswir1 | |
| 2060 | e9ebed4d | blueswir1 | void OPPROTO op_array16()
|
| 2061 | e9ebed4d | blueswir1 | {
|
| 2062 | e9ebed4d | blueswir1 | T0 = ((GET_FIELD_SP(T0, 60, 63) << (17 + 2 * T1)) | |
| 2063 | e9ebed4d | blueswir1 | (GET_FIELD_SP(T0, 39, 39 + T1 - 1) << (17 + T1)) | |
| 2064 | e9ebed4d | blueswir1 | (GET_FIELD_SP(T0, 17 + T1 - 1, 17) << 17) | |
| 2065 | e9ebed4d | blueswir1 | (GET_FIELD_SP(T0, 56, 59) << 13) | (GET_FIELD_SP(T0, 35, 38) << 9) | |
| 2066 | e9ebed4d | blueswir1 | (GET_FIELD_SP(T0, 13, 16) << 5) | (((T0 >> 55) & 1) << 4) | |
| 2067 | e9ebed4d | blueswir1 | (GET_FIELD_SP(T0, 33, 34) << 2) | GET_FIELD_SP(T0, 11, 12)) << 1; |
| 2068 | e9ebed4d | blueswir1 | } |
| 2069 | e9ebed4d | blueswir1 | |
| 2070 | e9ebed4d | blueswir1 | void OPPROTO op_array32()
|
| 2071 | e9ebed4d | blueswir1 | {
|
| 2072 | e9ebed4d | blueswir1 | T0 = ((GET_FIELD_SP(T0, 60, 63) << (17 + 2 * T1)) | |
| 2073 | e9ebed4d | blueswir1 | (GET_FIELD_SP(T0, 39, 39 + T1 - 1) << (17 + T1)) | |
| 2074 | e9ebed4d | blueswir1 | (GET_FIELD_SP(T0, 17 + T1 - 1, 17) << 17) | |
| 2075 | e9ebed4d | blueswir1 | (GET_FIELD_SP(T0, 56, 59) << 13) | (GET_FIELD_SP(T0, 35, 38) << 9) | |
| 2076 | e9ebed4d | blueswir1 | (GET_FIELD_SP(T0, 13, 16) << 5) | (((T0 >> 55) & 1) << 4) | |
| 2077 | e9ebed4d | blueswir1 | (GET_FIELD_SP(T0, 33, 34) << 2) | GET_FIELD_SP(T0, 11, 12)) << 2; |
| 2078 | e9ebed4d | blueswir1 | } |
| 2079 | e9ebed4d | blueswir1 | |
| 2080 | 725cb90b | bellard | void OPPROTO op_alignaddr()
|
| 2081 | 725cb90b | bellard | {
|
| 2082 | 725cb90b | bellard | uint64_t tmp; |
| 2083 | 725cb90b | bellard | |
| 2084 | 725cb90b | bellard | tmp = T0 + T1; |
| 2085 | 725cb90b | bellard | env->gsr &= ~7ULL;
|
| 2086 | 725cb90b | bellard | env->gsr |= tmp & 7ULL;
|
| 2087 | 725cb90b | bellard | T0 = tmp & ~7ULL;
|
| 2088 | 725cb90b | bellard | } |
| 2089 | 725cb90b | bellard | |
| 2090 | 725cb90b | bellard | void OPPROTO op_faligndata()
|
| 2091 | 725cb90b | bellard | {
|
| 2092 | 725cb90b | bellard | uint64_t tmp; |
| 2093 | 725cb90b | bellard | |
| 2094 | 725cb90b | bellard | tmp = (*((uint64_t *)&DT0)) << ((env->gsr & 7) * 8); |
| 2095 | 725cb90b | bellard | tmp |= (*((uint64_t *)&DT1)) >> (64 - (env->gsr & 7) * 8); |
| 2096 | e9ebed4d | blueswir1 | *((uint64_t *)&DT0) = tmp; |
| 2097 | 725cb90b | bellard | } |
| 2098 | 3299908c | blueswir1 | |
| 2099 | 3299908c | blueswir1 | void OPPROTO op_movl_FT0_0(void) |
| 2100 | 3299908c | blueswir1 | {
|
| 2101 | e9ebed4d | blueswir1 | *((uint32_t *)&FT0) = 0;
|
| 2102 | 3299908c | blueswir1 | } |
| 2103 | 3299908c | blueswir1 | |
| 2104 | 3299908c | blueswir1 | void OPPROTO op_movl_DT0_0(void) |
| 2105 | 3299908c | blueswir1 | {
|
| 2106 | e9ebed4d | blueswir1 | *((uint64_t *)&DT0) = 0;
|
| 2107 | 3299908c | blueswir1 | } |
| 2108 | 3299908c | blueswir1 | |
| 2109 | 3299908c | blueswir1 | void OPPROTO op_movl_FT0_1(void) |
| 2110 | 3299908c | blueswir1 | {
|
| 2111 | e9ebed4d | blueswir1 | *((uint32_t *)&FT0) = 0xffffffff;
|
| 2112 | 3299908c | blueswir1 | } |
| 2113 | 3299908c | blueswir1 | |
| 2114 | 3299908c | blueswir1 | void OPPROTO op_movl_DT0_1(void) |
| 2115 | 3299908c | blueswir1 | {
|
| 2116 | e9ebed4d | blueswir1 | *((uint64_t *)&DT0) = 0xffffffffffffffffULL;
|
| 2117 | e9ebed4d | blueswir1 | } |
| 2118 | e9ebed4d | blueswir1 | |
| 2119 | e9ebed4d | blueswir1 | void OPPROTO op_fnot(void) |
| 2120 | e9ebed4d | blueswir1 | {
|
| 2121 | e9ebed4d | blueswir1 | *(uint64_t *)&DT0 = ~*(uint64_t *)&DT1; |
| 2122 | e9ebed4d | blueswir1 | } |
| 2123 | e9ebed4d | blueswir1 | |
| 2124 | e9ebed4d | blueswir1 | void OPPROTO op_fnots(void) |
| 2125 | e9ebed4d | blueswir1 | {
|
| 2126 | e9ebed4d | blueswir1 | *(uint32_t *)&FT0 = ~*(uint32_t *)&FT1; |
| 2127 | e9ebed4d | blueswir1 | } |
| 2128 | e9ebed4d | blueswir1 | |
| 2129 | e9ebed4d | blueswir1 | void OPPROTO op_fnor(void) |
| 2130 | e9ebed4d | blueswir1 | {
|
| 2131 | e9ebed4d | blueswir1 | *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 | *(uint64_t *)&DT1); |
| 2132 | e9ebed4d | blueswir1 | } |
| 2133 | e9ebed4d | blueswir1 | |
| 2134 | e9ebed4d | blueswir1 | void OPPROTO op_fnors(void) |
| 2135 | e9ebed4d | blueswir1 | {
|
| 2136 | e9ebed4d | blueswir1 | *(uint32_t *)&FT0 = ~(*(uint32_t *)&FT0 | *(uint32_t *)&FT1); |
| 2137 | e9ebed4d | blueswir1 | } |
| 2138 | e9ebed4d | blueswir1 | |
| 2139 | e9ebed4d | blueswir1 | void OPPROTO op_for(void) |
| 2140 | e9ebed4d | blueswir1 | {
|
| 2141 | e9ebed4d | blueswir1 | *(uint64_t *)&DT0 |= *(uint64_t *)&DT1; |
| 2142 | e9ebed4d | blueswir1 | } |
| 2143 | e9ebed4d | blueswir1 | |
| 2144 | e9ebed4d | blueswir1 | void OPPROTO op_fors(void) |
| 2145 | e9ebed4d | blueswir1 | {
|
| 2146 | e9ebed4d | blueswir1 | *(uint32_t *)&FT0 |= *(uint32_t *)&FT1; |
| 2147 | e9ebed4d | blueswir1 | } |
| 2148 | e9ebed4d | blueswir1 | |
| 2149 | e9ebed4d | blueswir1 | void OPPROTO op_fxor(void) |
| 2150 | e9ebed4d | blueswir1 | {
|
| 2151 | e9ebed4d | blueswir1 | *(uint64_t *)&DT0 ^= *(uint64_t *)&DT1; |
| 2152 | e9ebed4d | blueswir1 | } |
| 2153 | e9ebed4d | blueswir1 | |
| 2154 | e9ebed4d | blueswir1 | void OPPROTO op_fxors(void) |
| 2155 | e9ebed4d | blueswir1 | {
|
| 2156 | e9ebed4d | blueswir1 | *(uint32_t *)&FT0 ^= *(uint32_t *)&FT1; |
| 2157 | e9ebed4d | blueswir1 | } |
| 2158 | e9ebed4d | blueswir1 | |
| 2159 | e9ebed4d | blueswir1 | void OPPROTO op_fand(void) |
| 2160 | e9ebed4d | blueswir1 | {
|
| 2161 | e9ebed4d | blueswir1 | *(uint64_t *)&DT0 &= *(uint64_t *)&DT1; |
| 2162 | e9ebed4d | blueswir1 | } |
| 2163 | e9ebed4d | blueswir1 | |
| 2164 | e9ebed4d | blueswir1 | void OPPROTO op_fands(void) |
| 2165 | e9ebed4d | blueswir1 | {
|
| 2166 | e9ebed4d | blueswir1 | *(uint32_t *)&FT0 &= *(uint32_t *)&FT1; |
| 2167 | e9ebed4d | blueswir1 | } |
| 2168 | e9ebed4d | blueswir1 | |
| 2169 | e9ebed4d | blueswir1 | void OPPROTO op_fornot(void) |
| 2170 | e9ebed4d | blueswir1 | {
|
| 2171 | e9ebed4d | blueswir1 | *(uint64_t *)&DT0 = *(uint64_t *)&DT0 | ~*(uint64_t *)&DT1; |
| 2172 | e9ebed4d | blueswir1 | } |
| 2173 | e9ebed4d | blueswir1 | |
| 2174 | e9ebed4d | blueswir1 | void OPPROTO op_fornots(void) |
| 2175 | e9ebed4d | blueswir1 | {
|
| 2176 | e9ebed4d | blueswir1 | *(uint32_t *)&FT0 = *(uint32_t *)&FT0 | ~*(uint32_t *)&FT1; |
| 2177 | e9ebed4d | blueswir1 | } |
| 2178 | e9ebed4d | blueswir1 | |
| 2179 | e9ebed4d | blueswir1 | void OPPROTO op_fandnot(void) |
| 2180 | e9ebed4d | blueswir1 | {
|
| 2181 | e9ebed4d | blueswir1 | *(uint64_t *)&DT0 = *(uint64_t *)&DT0 & ~*(uint64_t *)&DT1; |
| 2182 | e9ebed4d | blueswir1 | } |
| 2183 | e9ebed4d | blueswir1 | |
| 2184 | e9ebed4d | blueswir1 | void OPPROTO op_fandnots(void) |
| 2185 | e9ebed4d | blueswir1 | {
|
| 2186 | e9ebed4d | blueswir1 | *(uint32_t *)&FT0 = *(uint32_t *)&FT0 & ~*(uint32_t *)&FT1; |
| 2187 | e9ebed4d | blueswir1 | } |
| 2188 | e9ebed4d | blueswir1 | |
| 2189 | e9ebed4d | blueswir1 | void OPPROTO op_fnand(void) |
| 2190 | e9ebed4d | blueswir1 | {
|
| 2191 | e9ebed4d | blueswir1 | *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 & *(uint64_t *)&DT1); |
| 2192 | e9ebed4d | blueswir1 | } |
| 2193 | e9ebed4d | blueswir1 | |
| 2194 | e9ebed4d | blueswir1 | void OPPROTO op_fnands(void) |
| 2195 | e9ebed4d | blueswir1 | {
|
| 2196 | e9ebed4d | blueswir1 | *(uint32_t *)&FT0 = ~(*(uint32_t *)&FT0 & *(uint32_t *)&FT1); |
| 2197 | e9ebed4d | blueswir1 | } |
| 2198 | e9ebed4d | blueswir1 | |
| 2199 | e9ebed4d | blueswir1 | void OPPROTO op_fxnor(void) |
| 2200 | e9ebed4d | blueswir1 | {
|
| 2201 | e9ebed4d | blueswir1 | *(uint64_t *)&DT0 ^= ~*(uint64_t *)&DT1; |
| 2202 | e9ebed4d | blueswir1 | } |
| 2203 | e9ebed4d | blueswir1 | |
| 2204 | e9ebed4d | blueswir1 | void OPPROTO op_fxnors(void) |
| 2205 | e9ebed4d | blueswir1 | {
|
| 2206 | e9ebed4d | blueswir1 | *(uint32_t *)&FT0 ^= ~*(uint32_t *)&FT1; |
| 2207 | e9ebed4d | blueswir1 | } |
| 2208 | e9ebed4d | blueswir1 | |
| 2209 | e9ebed4d | blueswir1 | #ifdef WORDS_BIGENDIAN
|
| 2210 | e9ebed4d | blueswir1 | #define VIS_B64(n) b[7 - (n)] |
| 2211 | e9ebed4d | blueswir1 | #define VIS_W64(n) w[3 - (n)] |
| 2212 | e9ebed4d | blueswir1 | #define VIS_SW64(n) sw[3 - (n)] |
| 2213 | e9ebed4d | blueswir1 | #define VIS_L64(n) l[1 - (n)] |
| 2214 | e9ebed4d | blueswir1 | #define VIS_B32(n) b[3 - (n)] |
| 2215 | e9ebed4d | blueswir1 | #define VIS_W32(n) w[1 - (n)] |
| 2216 | e9ebed4d | blueswir1 | #else
|
| 2217 | e9ebed4d | blueswir1 | #define VIS_B64(n) b[n]
|
| 2218 | e9ebed4d | blueswir1 | #define VIS_W64(n) w[n]
|
| 2219 | e9ebed4d | blueswir1 | #define VIS_SW64(n) sw[n]
|
| 2220 | e9ebed4d | blueswir1 | #define VIS_L64(n) l[n]
|
| 2221 | e9ebed4d | blueswir1 | #define VIS_B32(n) b[n]
|
| 2222 | e9ebed4d | blueswir1 | #define VIS_W32(n) w[n]
|
| 2223 | e9ebed4d | blueswir1 | #endif
|
| 2224 | e9ebed4d | blueswir1 | |
| 2225 | e9ebed4d | blueswir1 | typedef union { |
| 2226 | e9ebed4d | blueswir1 | uint8_t b[8];
|
| 2227 | e9ebed4d | blueswir1 | uint16_t w[4];
|
| 2228 | e9ebed4d | blueswir1 | int16_t sw[4];
|
| 2229 | e9ebed4d | blueswir1 | uint32_t l[2];
|
| 2230 | e9ebed4d | blueswir1 | float64 d; |
| 2231 | e9ebed4d | blueswir1 | } vis64; |
| 2232 | e9ebed4d | blueswir1 | |
| 2233 | e9ebed4d | blueswir1 | typedef union { |
| 2234 | e9ebed4d | blueswir1 | uint8_t b[4];
|
| 2235 | e9ebed4d | blueswir1 | uint16_t w[2];
|
| 2236 | e9ebed4d | blueswir1 | uint32_t l; |
| 2237 | e9ebed4d | blueswir1 | float32 f; |
| 2238 | e9ebed4d | blueswir1 | } vis32; |
| 2239 | e9ebed4d | blueswir1 | |
| 2240 | e9ebed4d | blueswir1 | void OPPROTO op_fpmerge(void) |
| 2241 | e9ebed4d | blueswir1 | {
|
| 2242 | e9ebed4d | blueswir1 | vis64 s, d; |
| 2243 | e9ebed4d | blueswir1 | |
| 2244 | e9ebed4d | blueswir1 | s.d = DT0; |
| 2245 | e9ebed4d | blueswir1 | d.d = DT1; |
| 2246 | e9ebed4d | blueswir1 | |
| 2247 | e9ebed4d | blueswir1 | // Reverse calculation order to handle overlap
|
| 2248 | e9ebed4d | blueswir1 | d.VIS_B64(7) = s.VIS_B64(3); |
| 2249 | e9ebed4d | blueswir1 | d.VIS_B64(6) = d.VIS_B64(3); |
| 2250 | e9ebed4d | blueswir1 | d.VIS_B64(5) = s.VIS_B64(2); |
| 2251 | e9ebed4d | blueswir1 | d.VIS_B64(4) = d.VIS_B64(2); |
| 2252 | e9ebed4d | blueswir1 | d.VIS_B64(3) = s.VIS_B64(1); |
| 2253 | e9ebed4d | blueswir1 | d.VIS_B64(2) = d.VIS_B64(1); |
| 2254 | e9ebed4d | blueswir1 | d.VIS_B64(1) = s.VIS_B64(0); |
| 2255 | e9ebed4d | blueswir1 | //d.VIS_B64(0) = d.VIS_B64(0);
|
| 2256 | e9ebed4d | blueswir1 | |
| 2257 | e9ebed4d | blueswir1 | DT0 = d.d; |
| 2258 | e9ebed4d | blueswir1 | } |
| 2259 | e9ebed4d | blueswir1 | |
| 2260 | e9ebed4d | blueswir1 | void OPPROTO op_fmul8x16(void) |
| 2261 | e9ebed4d | blueswir1 | {
|
| 2262 | e9ebed4d | blueswir1 | vis64 s, d; |
| 2263 | e9ebed4d | blueswir1 | uint32_t tmp; |
| 2264 | e9ebed4d | blueswir1 | |
| 2265 | e9ebed4d | blueswir1 | s.d = DT0; |
| 2266 | e9ebed4d | blueswir1 | d.d = DT1; |
| 2267 | e9ebed4d | blueswir1 | |
| 2268 | e9ebed4d | blueswir1 | #define PMUL(r) \
|
| 2269 | e9ebed4d | blueswir1 | tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \ |
| 2270 | e9ebed4d | blueswir1 | if ((tmp & 0xff) > 0x7f) \ |
| 2271 | e9ebed4d | blueswir1 | tmp += 0x100; \
|
| 2272 | e9ebed4d | blueswir1 | d.VIS_W64(r) = tmp >> 8;
|
| 2273 | e9ebed4d | blueswir1 | |
| 2274 | e9ebed4d | blueswir1 | PMUL(0);
|
| 2275 | e9ebed4d | blueswir1 | PMUL(1);
|
| 2276 | e9ebed4d | blueswir1 | PMUL(2);
|
| 2277 | e9ebed4d | blueswir1 | PMUL(3);
|
| 2278 | e9ebed4d | blueswir1 | #undef PMUL
|
| 2279 | e9ebed4d | blueswir1 | |
| 2280 | e9ebed4d | blueswir1 | DT0 = d.d; |
| 2281 | e9ebed4d | blueswir1 | } |
| 2282 | e9ebed4d | blueswir1 | |
| 2283 | e9ebed4d | blueswir1 | void OPPROTO op_fmul8x16al(void) |
| 2284 | e9ebed4d | blueswir1 | {
|
| 2285 | e9ebed4d | blueswir1 | vis64 s, d; |
| 2286 | e9ebed4d | blueswir1 | uint32_t tmp; |
| 2287 | e9ebed4d | blueswir1 | |
| 2288 | e9ebed4d | blueswir1 | s.d = DT0; |
| 2289 | e9ebed4d | blueswir1 | d.d = DT1; |
| 2290 | e9ebed4d | blueswir1 | |
| 2291 | e9ebed4d | blueswir1 | #define PMUL(r) \
|
| 2292 | e9ebed4d | blueswir1 | tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \
|
| 2293 | e9ebed4d | blueswir1 | if ((tmp & 0xff) > 0x7f) \ |
| 2294 | e9ebed4d | blueswir1 | tmp += 0x100; \
|
| 2295 | e9ebed4d | blueswir1 | d.VIS_W64(r) = tmp >> 8;
|
| 2296 | e9ebed4d | blueswir1 | |
| 2297 | e9ebed4d | blueswir1 | PMUL(0);
|
| 2298 | e9ebed4d | blueswir1 | PMUL(1);
|
| 2299 | e9ebed4d | blueswir1 | PMUL(2);
|
| 2300 | e9ebed4d | blueswir1 | PMUL(3);
|
| 2301 | e9ebed4d | blueswir1 | #undef PMUL
|
| 2302 | e9ebed4d | blueswir1 | |
| 2303 | e9ebed4d | blueswir1 | DT0 = d.d; |
| 2304 | 3299908c | blueswir1 | } |
| 2305 | e9ebed4d | blueswir1 | |
| 2306 | e9ebed4d | blueswir1 | void OPPROTO op_fmul8x16au(void) |
| 2307 | e9ebed4d | blueswir1 | {
|
| 2308 | e9ebed4d | blueswir1 | vis64 s, d; |
| 2309 | e9ebed4d | blueswir1 | uint32_t tmp; |
| 2310 | e9ebed4d | blueswir1 | |
| 2311 | e9ebed4d | blueswir1 | s.d = DT0; |
| 2312 | e9ebed4d | blueswir1 | d.d = DT1; |
| 2313 | e9ebed4d | blueswir1 | |
| 2314 | e9ebed4d | blueswir1 | #define PMUL(r) \
|
| 2315 | e9ebed4d | blueswir1 | tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \
|
| 2316 | e9ebed4d | blueswir1 | if ((tmp & 0xff) > 0x7f) \ |
| 2317 | e9ebed4d | blueswir1 | tmp += 0x100; \
|
| 2318 | e9ebed4d | blueswir1 | d.VIS_W64(r) = tmp >> 8;
|
| 2319 | e9ebed4d | blueswir1 | |
| 2320 | e9ebed4d | blueswir1 | PMUL(0);
|
| 2321 | e9ebed4d | blueswir1 | PMUL(1);
|
| 2322 | e9ebed4d | blueswir1 | PMUL(2);
|
| 2323 | e9ebed4d | blueswir1 | PMUL(3);
|
| 2324 | e9ebed4d | blueswir1 | #undef PMUL
|
| 2325 | e9ebed4d | blueswir1 | |
| 2326 | e9ebed4d | blueswir1 | DT0 = d.d; |
| 2327 | e9ebed4d | blueswir1 | } |
| 2328 | e9ebed4d | blueswir1 | |
| 2329 | e9ebed4d | blueswir1 | void OPPROTO op_fmul8sux16(void) |
| 2330 | e9ebed4d | blueswir1 | {
|
| 2331 | e9ebed4d | blueswir1 | vis64 s, d; |
| 2332 | e9ebed4d | blueswir1 | uint32_t tmp; |
| 2333 | e9ebed4d | blueswir1 | |
| 2334 | e9ebed4d | blueswir1 | s.d = DT0; |
| 2335 | e9ebed4d | blueswir1 | d.d = DT1; |
| 2336 | e9ebed4d | blueswir1 | |
| 2337 | e9ebed4d | blueswir1 | #define PMUL(r) \
|
| 2338 | e9ebed4d | blueswir1 | tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
|
| 2339 | e9ebed4d | blueswir1 | if ((tmp & 0xff) > 0x7f) \ |
| 2340 | e9ebed4d | blueswir1 | tmp += 0x100; \
|
| 2341 | e9ebed4d | blueswir1 | d.VIS_W64(r) = tmp >> 8;
|
| 2342 | e9ebed4d | blueswir1 | |
| 2343 | e9ebed4d | blueswir1 | PMUL(0);
|
| 2344 | e9ebed4d | blueswir1 | PMUL(1);
|
| 2345 | e9ebed4d | blueswir1 | PMUL(2);
|
| 2346 | e9ebed4d | blueswir1 | PMUL(3);
|
| 2347 | e9ebed4d | blueswir1 | #undef PMUL
|
| 2348 | e9ebed4d | blueswir1 | |
| 2349 | e9ebed4d | blueswir1 | DT0 = d.d; |
| 2350 | e9ebed4d | blueswir1 | } |
| 2351 | e9ebed4d | blueswir1 | |
| 2352 | e9ebed4d | blueswir1 | void OPPROTO op_fmul8ulx16(void) |
| 2353 | e9ebed4d | blueswir1 | {
|
| 2354 | e9ebed4d | blueswir1 | vis64 s, d; |
| 2355 | e9ebed4d | blueswir1 | uint32_t tmp; |
| 2356 | e9ebed4d | blueswir1 | |
| 2357 | e9ebed4d | blueswir1 | s.d = DT0; |
| 2358 | e9ebed4d | blueswir1 | d.d = DT1; |
| 2359 | e9ebed4d | blueswir1 | |
| 2360 | e9ebed4d | blueswir1 | #define PMUL(r) \
|
| 2361 | e9ebed4d | blueswir1 | tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
|
| 2362 | e9ebed4d | blueswir1 | if ((tmp & 0xff) > 0x7f) \ |
| 2363 | e9ebed4d | blueswir1 | tmp += 0x100; \
|
| 2364 | e9ebed4d | blueswir1 | d.VIS_W64(r) = tmp >> 8;
|
| 2365 | e9ebed4d | blueswir1 | |
| 2366 | e9ebed4d | blueswir1 | PMUL(0);
|
| 2367 | e9ebed4d | blueswir1 | PMUL(1);
|
| 2368 | e9ebed4d | blueswir1 | PMUL(2);
|
| 2369 | e9ebed4d | blueswir1 | PMUL(3);
|
| 2370 | e9ebed4d | blueswir1 | #undef PMUL
|
| 2371 | e9ebed4d | blueswir1 | |
| 2372 | e9ebed4d | blueswir1 | DT0 = d.d; |
| 2373 | e9ebed4d | blueswir1 | } |
| 2374 | e9ebed4d | blueswir1 | |
| 2375 | e9ebed4d | blueswir1 | void OPPROTO op_fmuld8sux16(void) |
| 2376 | e9ebed4d | blueswir1 | {
|
| 2377 | e9ebed4d | blueswir1 | vis64 s, d; |
| 2378 | e9ebed4d | blueswir1 | uint32_t tmp; |
| 2379 | e9ebed4d | blueswir1 | |
| 2380 | e9ebed4d | blueswir1 | s.d = DT0; |
| 2381 | e9ebed4d | blueswir1 | d.d = DT1; |
| 2382 | e9ebed4d | blueswir1 | |
| 2383 | e9ebed4d | blueswir1 | #define PMUL(r) \
|
| 2384 | e9ebed4d | blueswir1 | tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
|
| 2385 | e9ebed4d | blueswir1 | if ((tmp & 0xff) > 0x7f) \ |
| 2386 | e9ebed4d | blueswir1 | tmp += 0x100; \
|
| 2387 | e9ebed4d | blueswir1 | d.VIS_L64(r) = tmp; |
| 2388 | e9ebed4d | blueswir1 | |
| 2389 | e9ebed4d | blueswir1 | // Reverse calculation order to handle overlap
|
| 2390 | e9ebed4d | blueswir1 | PMUL(1);
|
| 2391 | e9ebed4d | blueswir1 | PMUL(0);
|
| 2392 | e9ebed4d | blueswir1 | #undef PMUL
|
| 2393 | e9ebed4d | blueswir1 | |
| 2394 | e9ebed4d | blueswir1 | DT0 = d.d; |
| 2395 | e9ebed4d | blueswir1 | } |
| 2396 | e9ebed4d | blueswir1 | |
| 2397 | e9ebed4d | blueswir1 | void OPPROTO op_fmuld8ulx16(void) |
| 2398 | e9ebed4d | blueswir1 | {
|
| 2399 | e9ebed4d | blueswir1 | vis64 s, d; |
| 2400 | e9ebed4d | blueswir1 | uint32_t tmp; |
| 2401 | e9ebed4d | blueswir1 | |
| 2402 | e9ebed4d | blueswir1 | s.d = DT0; |
| 2403 | e9ebed4d | blueswir1 | d.d = DT1; |
| 2404 | e9ebed4d | blueswir1 | |
| 2405 | e9ebed4d | blueswir1 | #define PMUL(r) \
|
| 2406 | e9ebed4d | blueswir1 | tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
|
| 2407 | e9ebed4d | blueswir1 | if ((tmp & 0xff) > 0x7f) \ |
| 2408 | e9ebed4d | blueswir1 | tmp += 0x100; \
|
| 2409 | e9ebed4d | blueswir1 | d.VIS_L64(r) = tmp; |
| 2410 | e9ebed4d | blueswir1 | |
| 2411 | e9ebed4d | blueswir1 | // Reverse calculation order to handle overlap
|
| 2412 | e9ebed4d | blueswir1 | PMUL(1);
|
| 2413 | e9ebed4d | blueswir1 | PMUL(0);
|
| 2414 | e9ebed4d | blueswir1 | #undef PMUL
|
| 2415 | e9ebed4d | blueswir1 | |
| 2416 | e9ebed4d | blueswir1 | DT0 = d.d; |
| 2417 | e9ebed4d | blueswir1 | } |
| 2418 | e9ebed4d | blueswir1 | |
| 2419 | e9ebed4d | blueswir1 | void OPPROTO op_fexpand(void) |
| 2420 | e9ebed4d | blueswir1 | {
|
| 2421 | e9ebed4d | blueswir1 | vis32 s; |
| 2422 | e9ebed4d | blueswir1 | vis64 d; |
| 2423 | e9ebed4d | blueswir1 | |
| 2424 | e9ebed4d | blueswir1 | s.l = (uint32_t)(*(uint64_t *)&DT0 & 0xffffffff);
|
| 2425 | e9ebed4d | blueswir1 | d.d = DT1; |
| 2426 | e9ebed4d | blueswir1 | d.VIS_L64(0) = s.VIS_W32(0) << 4; |
| 2427 | e9ebed4d | blueswir1 | d.VIS_L64(1) = s.VIS_W32(1) << 4; |
| 2428 | e9ebed4d | blueswir1 | d.VIS_L64(2) = s.VIS_W32(2) << 4; |
| 2429 | e9ebed4d | blueswir1 | d.VIS_L64(3) = s.VIS_W32(3) << 4; |
| 2430 | e9ebed4d | blueswir1 | |
| 2431 | e9ebed4d | blueswir1 | DT0 = d.d; |
| 2432 | e9ebed4d | blueswir1 | } |
| 2433 | e9ebed4d | blueswir1 | |
| 2434 | e9ebed4d | blueswir1 | #define VIS_OP(name, F) \
|
| 2435 | e9ebed4d | blueswir1 | void OPPROTO name##16(void) \ |
| 2436 | e9ebed4d | blueswir1 | { \
|
| 2437 | e9ebed4d | blueswir1 | vis64 s, d; \ |
| 2438 | e9ebed4d | blueswir1 | \ |
| 2439 | e9ebed4d | blueswir1 | s.d = DT0; \ |
| 2440 | e9ebed4d | blueswir1 | d.d = DT1; \ |
| 2441 | e9ebed4d | blueswir1 | \ |
| 2442 | e9ebed4d | blueswir1 | d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \ |
| 2443 | e9ebed4d | blueswir1 | d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \ |
| 2444 | e9ebed4d | blueswir1 | d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \ |
| 2445 | e9ebed4d | blueswir1 | d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \ |
| 2446 | e9ebed4d | blueswir1 | \ |
| 2447 | e9ebed4d | blueswir1 | DT0 = d.d; \ |
| 2448 | e9ebed4d | blueswir1 | } \ |
| 2449 | e9ebed4d | blueswir1 | \ |
| 2450 | e9ebed4d | blueswir1 | void OPPROTO name##16s(void) \ |
| 2451 | e9ebed4d | blueswir1 | { \
|
| 2452 | e9ebed4d | blueswir1 | vis32 s, d; \ |
| 2453 | e9ebed4d | blueswir1 | \ |
| 2454 | e9ebed4d | blueswir1 | s.f = FT0; \ |
| 2455 | e9ebed4d | blueswir1 | d.f = FT1; \ |
| 2456 | e9ebed4d | blueswir1 | \ |
| 2457 | e9ebed4d | blueswir1 | d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \ |
| 2458 | e9ebed4d | blueswir1 | d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \ |
| 2459 | e9ebed4d | blueswir1 | \ |
| 2460 | e9ebed4d | blueswir1 | FT0 = d.f; \ |
| 2461 | e9ebed4d | blueswir1 | } \ |
| 2462 | e9ebed4d | blueswir1 | \ |
| 2463 | e9ebed4d | blueswir1 | void OPPROTO name##32(void) \ |
| 2464 | e9ebed4d | blueswir1 | { \
|
| 2465 | e9ebed4d | blueswir1 | vis64 s, d; \ |
| 2466 | e9ebed4d | blueswir1 | \ |
| 2467 | e9ebed4d | blueswir1 | s.d = DT0; \ |
| 2468 | e9ebed4d | blueswir1 | d.d = DT1; \ |
| 2469 | e9ebed4d | blueswir1 | \ |
| 2470 | e9ebed4d | blueswir1 | d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \ |
| 2471 | e9ebed4d | blueswir1 | d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \ |
| 2472 | e9ebed4d | blueswir1 | \ |
| 2473 | e9ebed4d | blueswir1 | DT0 = d.d; \ |
| 2474 | e9ebed4d | blueswir1 | } \ |
| 2475 | e9ebed4d | blueswir1 | \ |
| 2476 | e9ebed4d | blueswir1 | void OPPROTO name##32s(void) \ |
| 2477 | e9ebed4d | blueswir1 | { \
|
| 2478 | e9ebed4d | blueswir1 | vis32 s, d; \ |
| 2479 | e9ebed4d | blueswir1 | \ |
| 2480 | e9ebed4d | blueswir1 | s.f = FT0; \ |
| 2481 | e9ebed4d | blueswir1 | d.f = FT1; \ |
| 2482 | e9ebed4d | blueswir1 | \ |
| 2483 | e9ebed4d | blueswir1 | d.l = F(d.l, s.l); \ |
| 2484 | e9ebed4d | blueswir1 | \ |
| 2485 | e9ebed4d | blueswir1 | FT0 = d.f; \ |
| 2486 | e9ebed4d | blueswir1 | } |
| 2487 | e9ebed4d | blueswir1 | |
| 2488 | e9ebed4d | blueswir1 | #define FADD(a, b) ((a) + (b))
|
| 2489 | e9ebed4d | blueswir1 | #define FSUB(a, b) ((a) - (b))
|
| 2490 | e9ebed4d | blueswir1 | VIS_OP(op_fpadd, FADD) |
| 2491 | e9ebed4d | blueswir1 | VIS_OP(op_fpsub, FSUB) |
| 2492 | e9ebed4d | blueswir1 | |
| 2493 | e9ebed4d | blueswir1 | #define VIS_CMPOP(name, F) \
|
| 2494 | e9ebed4d | blueswir1 | void OPPROTO name##16(void) \ |
| 2495 | e9ebed4d | blueswir1 | { \
|
| 2496 | e9ebed4d | blueswir1 | vis64 s, d; \ |
| 2497 | e9ebed4d | blueswir1 | \ |
| 2498 | e9ebed4d | blueswir1 | s.d = DT0; \ |
| 2499 | e9ebed4d | blueswir1 | d.d = DT1; \ |
| 2500 | e9ebed4d | blueswir1 | \ |
| 2501 | e9ebed4d | blueswir1 | d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0; \ |
| 2502 | e9ebed4d | blueswir1 | d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0; \ |
| 2503 | e9ebed4d | blueswir1 | d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0; \ |
| 2504 | e9ebed4d | blueswir1 | d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0; \ |
| 2505 | e9ebed4d | blueswir1 | \ |
| 2506 | e9ebed4d | blueswir1 | DT0 = d.d; \ |
| 2507 | e9ebed4d | blueswir1 | } \ |
| 2508 | e9ebed4d | blueswir1 | \ |
| 2509 | e9ebed4d | blueswir1 | void OPPROTO name##32(void) \ |
| 2510 | e9ebed4d | blueswir1 | { \
|
| 2511 | e9ebed4d | blueswir1 | vis64 s, d; \ |
| 2512 | e9ebed4d | blueswir1 | \ |
| 2513 | e9ebed4d | blueswir1 | s.d = DT0; \ |
| 2514 | e9ebed4d | blueswir1 | d.d = DT1; \ |
| 2515 | e9ebed4d | blueswir1 | \ |
| 2516 | e9ebed4d | blueswir1 | d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0; \ |
| 2517 | e9ebed4d | blueswir1 | d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0; \ |
| 2518 | e9ebed4d | blueswir1 | \ |
| 2519 | e9ebed4d | blueswir1 | DT0 = d.d; \ |
| 2520 | e9ebed4d | blueswir1 | } |
| 2521 | e9ebed4d | blueswir1 | |
| 2522 | e9ebed4d | blueswir1 | #define FCMPGT(a, b) ((a) > (b))
|
| 2523 | e9ebed4d | blueswir1 | #define FCMPEQ(a, b) ((a) == (b))
|
| 2524 | e9ebed4d | blueswir1 | #define FCMPLE(a, b) ((a) <= (b))
|
| 2525 | e9ebed4d | blueswir1 | #define FCMPNE(a, b) ((a) != (b))
|
| 2526 | e9ebed4d | blueswir1 | |
| 2527 | e9ebed4d | blueswir1 | VIS_CMPOP(op_fcmpgt, FCMPGT) |
| 2528 | e9ebed4d | blueswir1 | VIS_CMPOP(op_fcmpeq, FCMPEQ) |
| 2529 | e9ebed4d | blueswir1 | VIS_CMPOP(op_fcmple, FCMPLE) |
| 2530 | e9ebed4d | blueswir1 | VIS_CMPOP(op_fcmpne, FCMPNE) |
| 2531 | e9ebed4d | blueswir1 | |
| 2532 | 725cb90b | bellard | #endif
|
| 2533 | 6ea4a6c8 | blueswir1 | |
| 2534 | 6ea4a6c8 | blueswir1 | #define CHECK_ALIGN_OP(align) \
|
| 2535 | 6ea4a6c8 | blueswir1 | void OPPROTO op_check_align_T0_ ## align (void) \ |
| 2536 | 6ea4a6c8 | blueswir1 | { \
|
| 2537 | 6ea4a6c8 | blueswir1 | if (T0 & align) \
|
| 2538 | 6ea4a6c8 | blueswir1 | raise_exception(TT_UNALIGNED); \ |
| 2539 | 6ea4a6c8 | blueswir1 | FORCE_RET(); \ |
| 2540 | 6ea4a6c8 | blueswir1 | } |
| 2541 | 6ea4a6c8 | blueswir1 | |
| 2542 | 6ea4a6c8 | blueswir1 | CHECK_ALIGN_OP(1)
|
| 2543 | 6ea4a6c8 | blueswir1 | CHECK_ALIGN_OP(3)
|
| 2544 | 6ea4a6c8 | blueswir1 | CHECK_ALIGN_OP(7) |