Archipelago » qemu

libdis-$(CONFIG_IA64_DIS) += ia64-dis.o

  ia64*)

    echo "CONFIG_IA64_DIS=y"  >> $config_target_mak

    echo "CONFIG_IA64_DIS=y"  >> $libdis_config_mak

  ;;

  bfd_arch_ia64,      /* HP/Intel ia64 */

#define bfd_mach_ia64_elf64    64

#define bfd_mach_ia64_elf32    32

extern int print_insn_ia64              (bfd_vma, disassemble_info*);

bfd_vma bfd_getl64 (const bfd_byte *addr);

bfd_vma bfd_getl64 (const bfd_byte *addr)

{

  unsigned long long v;

  v = (unsigned long long) addr[0];

  v |= (unsigned long long) addr[1] << 8;

  v |= (unsigned long long) addr[2] << 16;

  v |= (unsigned long long) addr[3] << 24;

  v |= (unsigned long long) addr[4] << 32;

  v |= (unsigned long long) addr[5] << 40;

  v |= (unsigned long long) addr[6] << 48;

  v |= (unsigned long long) addr[7] << 56;

  return (bfd_vma) v;

}

#elif defined(__ia64__)

    print_insn = print_insn_ia64;

/* ia64-dis.c -- Disassemble ia64 instructions

   Copyright 1998, 1999, 2000, 2002 Free Software Foundation, Inc.

   Contributed by David Mosberger-Tang <davidm@hpl.hp.com>

   This file is part of GDB, GAS, and the GNU binutils.

   GDB, GAS, and the GNU binutils are free software; you can redistribute

   them and/or modify them under the terms of the GNU General Public

   License as published by the Free Software Foundation; either version

   2, or (at your option) any later version.

   GDB, GAS, and the GNU binutils are distributed in the hope that they

   will be useful, but WITHOUT ANY WARRANTY; without even the implied

   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See

   the GNU General Public License for more details.

   You should have received a copy of the GNU General Public License

   along with this file; see the file COPYING.  If not, see

   <http://www.gnu.org/licenses/>. */

#include <assert.h>

#include <string.h>

#include "dis-asm.h"

/* ia64.h -- Header file for ia64 opcode table

   Copyright (C) 1998, 1999, 2000, 2002, 2005, 2006

   Free Software Foundation, Inc.

   Contributed by David Mosberger-Tang <davidm@hpl.hp.com> */

#include <sys/types.h>

typedef uint64_t ia64_insn;

enum ia64_insn_type

  {

    IA64_TYPE_NIL = 0,	/* illegal type */

    IA64_TYPE_A,	/* integer alu (I- or M-unit) */

    IA64_TYPE_I,	/* non-alu integer (I-unit) */

    IA64_TYPE_M,	/* memory (M-unit) */

    IA64_TYPE_B,	/* branch (B-unit) */

    IA64_TYPE_F,	/* floating-point (F-unit) */

    IA64_TYPE_X,	/* long encoding (X-unit) */

    IA64_TYPE_DYN,	/* Dynamic opcode */

    IA64_NUM_TYPES

  };

enum ia64_unit

  {

    IA64_UNIT_NIL = 0,	/* illegal unit */

    IA64_UNIT_I,	/* integer unit */

    IA64_UNIT_M,	/* memory unit */

    IA64_UNIT_B,	/* branching unit */

    IA64_UNIT_F,	/* floating-point unit */

    IA64_UNIT_L,	/* long "unit" */

    IA64_UNIT_X,	/* may be integer or branch unit */

    IA64_NUM_UNITS

  };

/* Changes to this enumeration must be propagated to the operand table in

   bfd/cpu-ia64-opc.c

 */

enum ia64_opnd

  {

    IA64_OPND_NIL,	/* no operand---MUST BE FIRST!*/

    /* constants */

    IA64_OPND_AR_CSD,	/* application register csd (ar.csd) */

    IA64_OPND_AR_CCV,	/* application register ccv (ar.ccv) */

    IA64_OPND_AR_PFS,	/* application register pfs (ar.pfs) */

    IA64_OPND_C1,	/* the constant 1 */

    IA64_OPND_C8,	/* the constant 8 */

    IA64_OPND_C16,	/* the constant 16 */

    IA64_OPND_GR0,	/* gr0 */

    IA64_OPND_IP,	/* instruction pointer (ip) */

    IA64_OPND_PR,	/* predicate register (pr) */

    IA64_OPND_PR_ROT,	/* rotating predicate register (pr.rot) */

    IA64_OPND_PSR,	/* processor status register (psr) */

    IA64_OPND_PSR_L,	/* processor status register L (psr.l) */

    IA64_OPND_PSR_UM,	/* processor status register UM (psr.um) */

    /* register operands: */

    IA64_OPND_AR3,	/* third application register # (bits 20-26) */

    IA64_OPND_B1,	/* branch register # (bits 6-8) */

    IA64_OPND_B2,	/* branch register # (bits 13-15) */

    IA64_OPND_CR3,	/* third control register # (bits 20-26) */

    IA64_OPND_F1,	/* first floating-point register # */

    IA64_OPND_F2,	/* second floating-point register # */

    IA64_OPND_F3,	/* third floating-point register # */

    IA64_OPND_F4,	/* fourth floating-point register # */

    IA64_OPND_P1,	/* first predicate # */

    IA64_OPND_P2,	/* second predicate # */

    IA64_OPND_R1,	/* first register # */

    IA64_OPND_R2,	/* second register # */

    IA64_OPND_R3,	/* third register # */

    IA64_OPND_R3_2,	/* third register # (limited to gr0-gr3) */

    /* memory operands: */

    IA64_OPND_MR3,	/* memory at addr of third register # */

    /* indirect operands: */

    IA64_OPND_CPUID_R3,	/* cpuid[reg] */

    IA64_OPND_DBR_R3,	/* dbr[reg] */

    IA64_OPND_DTR_R3,	/* dtr[reg] */

    IA64_OPND_ITR_R3,	/* itr[reg] */

    IA64_OPND_IBR_R3,	/* ibr[reg] */

    IA64_OPND_MSR_R3,	/* msr[reg] */

    IA64_OPND_PKR_R3,	/* pkr[reg] */

    IA64_OPND_PMC_R3,	/* pmc[reg] */

    IA64_OPND_PMD_R3,	/* pmd[reg] */

    IA64_OPND_RR_R3,	/* rr[reg] */

    /* immediate operands: */

    IA64_OPND_CCNT5,	/* 5-bit count (31 - bits 20-24) */

    IA64_OPND_CNT2a,	/* 2-bit count (1 + bits 27-28) */

    IA64_OPND_CNT2b,	/* 2-bit count (bits 27-28): 1, 2, 3 */

    IA64_OPND_CNT2c,	/* 2-bit count (bits 30-31): 0, 7, 15, or 16 */

    IA64_OPND_CNT5,	/* 5-bit count (bits 14-18) */

    IA64_OPND_CNT6,	/* 6-bit count (bits 27-32) */

    IA64_OPND_CPOS6a,	/* 6-bit count (63 - bits 20-25) */

    IA64_OPND_CPOS6b,	/* 6-bit count (63 - bits 14-19) */

    IA64_OPND_CPOS6c,	/* 6-bit count (63 - bits 31-36) */

    IA64_OPND_IMM1,	/* signed 1-bit immediate (bit 36) */

    IA64_OPND_IMMU2,	/* unsigned 2-bit immediate (bits 13-14) */

    IA64_OPND_IMMU5b,	/* unsigned 5-bit immediate (32 + bits 14-18) */

    IA64_OPND_IMMU7a,	/* unsigned 7-bit immediate (bits 13-19) */

    IA64_OPND_IMMU7b,	/* unsigned 7-bit immediate (bits 20-26) */

    IA64_OPND_SOF,	/* 8-bit stack frame size */

    IA64_OPND_SOL,	/* 8-bit size of locals */

    IA64_OPND_SOR,	/* 6-bit number of rotating registers (scaled by 8) */

    IA64_OPND_IMM8,	/* signed 8-bit immediate (bits 13-19 & 36) */

    IA64_OPND_IMM8U4,	/* cmp4*u signed 8-bit immediate (bits 13-19 & 36) */

    IA64_OPND_IMM8M1,	/* signed 8-bit immediate -1 (bits 13-19 & 36) */

    IA64_OPND_IMM8M1U4,	/* cmp4*u signed 8-bit immediate -1 (bits 13-19 & 36)*/

    IA64_OPND_IMM8M1U8,	/* cmp*u signed 8-bit immediate -1 (bits 13-19 & 36) */

    IA64_OPND_IMMU9,	/* unsigned 9-bit immediate (bits 33-34, 20-26) */

    IA64_OPND_IMM9a,	/* signed 9-bit immediate (bits 6-12, 27, 36) */

    IA64_OPND_IMM9b,	/* signed 9-bit immediate (bits 13-19, 27, 36) */

    IA64_OPND_IMM14,	/* signed 14-bit immediate (bits 13-19, 27-32, 36) */

    IA64_OPND_IMM17,	/* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */

    IA64_OPND_IMMU21,	/* unsigned 21-bit immediate (bits 6-25, 36) */

    IA64_OPND_IMM22,	/* signed 22-bit immediate (bits 13-19, 22-36) */

    IA64_OPND_IMMU24,	/* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */

    IA64_OPND_IMM44,	/* signed 44-bit immediate (2^16*bits 6-32, 36) */

    IA64_OPND_IMMU62,	/* unsigned 62-bit immediate */

    IA64_OPND_IMMU64,	/* unsigned 64-bit immediate (lotsa bits...) */

    IA64_OPND_INC3,	/* signed 3-bit (bits 13-15): +/-1, 4, 8, 16 */

    IA64_OPND_LEN4,	/* 4-bit count (bits 27-30 + 1) */

    IA64_OPND_LEN6,	/* 6-bit count (bits 27-32 + 1) */

    IA64_OPND_MBTYPE4,	/* 4-bit mux type (bits 20-23) */

    IA64_OPND_MHTYPE8,	/* 8-bit mux type (bits 20-27) */

    IA64_OPND_POS6,	/* 6-bit count (bits 14-19) */

    IA64_OPND_TAG13,	/* signed 13-bit tag (ip + 16*bits 6-12, 33-34) */

    IA64_OPND_TAG13b,	/* signed 13-bit tag (ip + 16*bits 24-32) */

    IA64_OPND_TGT25,	/* signed 25-bit (ip + 16*bits 6-25, 36) */

    IA64_OPND_TGT25b,	/* signed 25-bit (ip + 16*bits 6-12, 20-32, 36) */

    IA64_OPND_TGT25c,	/* signed 25-bit (ip + 16*bits 13-32, 36) */

    IA64_OPND_TGT64,    /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */

    IA64_OPND_LDXMOV,	/* any symbol, generates R_IA64_LDXMOV.  */

    IA64_OPND_COUNT	/* # of operand types (MUST BE LAST!) */

  };

enum ia64_dependency_mode

{

  IA64_DV_RAW,

  IA64_DV_WAW,

  IA64_DV_WAR,

};

enum ia64_dependency_semantics

{

  IA64_DVS_NONE,

  IA64_DVS_IMPLIED,

  IA64_DVS_IMPLIEDF,

  IA64_DVS_DATA,

  IA64_DVS_INSTR,

  IA64_DVS_SPECIFIC,

  IA64_DVS_STOP,

  IA64_DVS_OTHER,

};

enum ia64_resource_specifier

{

  IA64_RS_ANY,

  IA64_RS_AR_K,

  IA64_RS_AR_UNAT,

  IA64_RS_AR, /* 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111 */

  IA64_RS_ARb, /* 48-63, 112-127 */

  IA64_RS_BR,

  IA64_RS_CFM,

  IA64_RS_CPUID,

  IA64_RS_CR_IRR,

  IA64_RS_CR_LRR,

  IA64_RS_CR, /* 3-7,10-15,18,26-63,75-79,82-127 */

  IA64_RS_DBR,

  IA64_RS_FR,

  IA64_RS_FRb,

  IA64_RS_GR0,

  IA64_RS_GR,

  IA64_RS_IBR,

  IA64_RS_INSERVICE, /* CR[EOI] or CR[IVR] */

  IA64_RS_MSR,

  IA64_RS_PKR,

  IA64_RS_PMC,

  IA64_RS_PMD,

  IA64_RS_PR,  /* non-rotating, 1-15 */

  IA64_RS_PRr, /* rotating, 16-62 */

  IA64_RS_PR63,

  IA64_RS_RR,

  IA64_RS_ARX, /* ARs not in RS_AR or RS_ARb */

  IA64_RS_CRX, /* CRs not in RS_CR */

  IA64_RS_PSR, /* PSR bits */

  IA64_RS_RSE, /* implementation-specific RSE resources */

  IA64_RS_AR_FPSR,

};

enum ia64_rse_resource

{

  IA64_RSE_N_STACKED_PHYS,

  IA64_RSE_BOF,

  IA64_RSE_STORE_REG,

  IA64_RSE_LOAD_REG,

  IA64_RSE_BSPLOAD,

  IA64_RSE_RNATBITINDEX,

  IA64_RSE_CFLE,

  IA64_RSE_NDIRTY,

};

/* Information about a given resource dependency */

struct ia64_dependency

{

  /* Name of the resource */

  const char *name;

  /* Does this dependency need further specification? */

  enum ia64_resource_specifier specifier;

  /* Mode of dependency */

  enum ia64_dependency_mode mode;

  /* Dependency semantics */

  enum ia64_dependency_semantics semantics;

  /* Register index, if applicable (distinguishes AR, CR, and PSR deps) */

#define REG_NONE (-1)

  int regindex;

  /* Special info on semantics */

  const char *info;

};

/* Two arrays of indexes into the ia64_dependency table.

   chks are dependencies to check for conflicts when an opcode is

   encountered; regs are dependencies to register (mark as used) when an

   opcode is used.  chks correspond to readers (RAW) or writers (WAW or

   WAR) of a resource, while regs correspond to writers (RAW or WAW) and

   readers (WAR) of a resource.  */

struct ia64_opcode_dependency

{

  int nchks;

  const unsigned short *chks;

  int nregs;

  const unsigned short *regs;

};

/* encode/extract the note/index for a dependency */

#define RDEP(N,X) (((N)<<11)|(X))

#define NOTE(X) (((X)>>11)&0x1F)

#define DEP(X) ((X)&0x7FF)

/* A template descriptor describes the execution units that are active

   for each of the three slots.  It also specifies the location of

   instruction group boundaries that may be present between two slots.  */

struct ia64_templ_desc

  {

    int group_boundary;	/* 0=no boundary, 1=between slot 0 & 1, etc. */

    enum ia64_unit exec_unit[3];

    const char *name;

  };

/* The opcode table is an array of struct ia64_opcode.  */

struct ia64_opcode

  {

    /* The opcode name.  */

    const char *name;

    /* The type of the instruction: */

    enum ia64_insn_type type;

    /* Number of output operands: */

    int num_outputs;

    /* The opcode itself.  Those bits which will be filled in with

       operands are zeroes.  */

    ia64_insn opcode;

    /* The opcode mask.  This is used by the disassembler.  This is a

       mask containing ones indicating those bits which must match the

       opcode field, and zeroes indicating those bits which need not

       match (and are presumably filled in by operands).  */

    ia64_insn mask;

    /* An array of operand codes.  Each code is an index into the

       operand table.  They appear in the order which the operands must

       appear in assembly code, and are terminated by a zero.  */

    enum ia64_opnd operands[5];

    /* One bit flags for the opcode.  These are primarily used to

       indicate specific processors and environments support the

       instructions.  The defined values are listed below. */

    unsigned int flags;

    /* Used by ia64_find_next_opcode (). */

    short ent_index;

    /* Opcode dependencies. */

    const struct ia64_opcode_dependency *dependencies;

  };

/* Values defined for the flags field of a struct ia64_opcode.  */

#define IA64_OPCODE_FIRST	(1<<0)	/* must be first in an insn group */

#define IA64_OPCODE_X_IN_MLX	(1<<1)	/* insn is allowed in X slot of MLX */

#define IA64_OPCODE_LAST	(1<<2)	/* must be last in an insn group */

#define IA64_OPCODE_PRIV	(1<<3)	/* privileged instruct */

#define IA64_OPCODE_SLOT2	(1<<4)	/* insn allowed in slot 2 only */

#define IA64_OPCODE_NO_PRED	(1<<5)	/* insn cannot be predicated */

#define IA64_OPCODE_PSEUDO	(1<<6)	/* insn is a pseudo-op */

#define IA64_OPCODE_F2_EQ_F3	(1<<7)	/* constraint: F2 == F3 */

#define IA64_OPCODE_LEN_EQ_64MCNT	(1<<8)	/* constraint: LEN == 64-CNT */

#define IA64_OPCODE_MOD_RRBS    (1<<9)	/* modifies all rrbs in CFM */

#define IA64_OPCODE_POSTINC	(1<<10)	/* postincrement MR3 operand */

/* A macro to extract the major opcode from an instruction.  */

#define IA64_OP(i)	(((i) >> 37) & 0xf)

enum ia64_operand_class

  {

    IA64_OPND_CLASS_CST,	/* constant */

    IA64_OPND_CLASS_REG,	/* register */

    IA64_OPND_CLASS_IND,	/* indirect register */

    IA64_OPND_CLASS_ABS,	/* absolute value */

    IA64_OPND_CLASS_REL,	/* IP-relative value */

  };

/* The operands table is an array of struct ia64_operand.  */

struct ia64_operand

{

  enum ia64_operand_class class;

  /* Set VALUE as the operand bits for the operand of type SELF in the

     instruction pointed to by CODE.  If an error occurs, *CODE is not

     modified and the returned string describes the cause of the

     error.  If no error occurs, NULL is returned.  */

  const char *(*insert) (const struct ia64_operand *self, ia64_insn value,

			 ia64_insn *code);

  /* Extract the operand bits for an operand of type SELF from

     instruction CODE store them in *VALUE.  If an error occurs, the

     cause of the error is described by the string returned.  If no

     error occurs, NULL is returned.  */

  const char *(*extract) (const struct ia64_operand *self, ia64_insn code,

			  ia64_insn *value);

  /* A string whose meaning depends on the operand class.  */

  const char *str;

  struct bit_field

    {

      /* The number of bits in the operand.  */

      int bits;

      /* How far the operand is left shifted in the instruction.  */

      int shift;

    }

  field[4];		/* no operand has more than this many bit-fields */

  unsigned int flags;

  const char *desc;	/* brief description */

};

/* Values defined for the flags field of a struct ia64_operand.  */

/* Disassemble as signed decimal (instead of hex): */

#define IA64_OPND_FLAG_DECIMAL_SIGNED	(1<<0)

/* Disassemble as unsigned decimal (instead of hex): */

#define IA64_OPND_FLAG_DECIMAL_UNSIGNED	(1<<1)

#define NELEMS(a)	((int) (sizeof (a) / sizeof (a[0])))

static const char*

ins_rsvd (const struct ia64_operand *self ATTRIBUTE_UNUSED,

	  ia64_insn value ATTRIBUTE_UNUSED, ia64_insn *code ATTRIBUTE_UNUSED)

{

  return "internal error---this shouldn't happen";

}

static const char*

ext_rsvd (const struct ia64_operand *self ATTRIBUTE_UNUSED,

	  ia64_insn code ATTRIBUTE_UNUSED, ia64_insn *valuep ATTRIBUTE_UNUSED)

{

  return "internal error---this shouldn't happen";

}

static const char*

ins_const (const struct ia64_operand *self ATTRIBUTE_UNUSED,

	   ia64_insn value ATTRIBUTE_UNUSED, ia64_insn *code ATTRIBUTE_UNUSED)

{

  return 0;

}

static const char*

ext_const (const struct ia64_operand *self ATTRIBUTE_UNUSED,

	   ia64_insn code ATTRIBUTE_UNUSED, ia64_insn *valuep ATTRIBUTE_UNUSED)

{

  return 0;

}

static const char*

ins_reg (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)

{

  if (value >= 1u << self->field[0].bits)

    return "register number out of range";

  *code |= value << self->field[0].shift;

  return 0;

}

static const char*

ext_reg (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)

{

  *valuep = ((code >> self->field[0].shift)

	     & ((1u << self->field[0].bits) - 1));

  return 0;

}

static const char*

ins_immu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)

{

  ia64_insn new = 0;

  int i;

  for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)

    {

      new |= ((value & ((((ia64_insn) 1) << self->field[i].bits) - 1))

	      << self->field[i].shift);

      value >>= self->field[i].bits;

    }

  if (value)

    return "integer operand out of range";

  *code |= new;

  return 0;

}

static const char*

ext_immu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)

{

  uint64_t value = 0;

  int i, bits = 0, total = 0;

  for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)

    {

      bits = self->field[i].bits;

      value |= ((code >> self->field[i].shift)

		& ((((uint64_t) 1) << bits) - 1)) << total;

      total += bits;

    }

  *valuep = value;

  return 0;

}

static const char*

ins_immu5b (const struct ia64_operand *self, ia64_insn value,

	    ia64_insn *code)

{

  if (value < 32 || value > 63)

    return "value must be between 32 and 63";

  return ins_immu (self, value - 32, code);

}

static const char*

ext_immu5b (const struct ia64_operand *self, ia64_insn code,

	    ia64_insn *valuep)

{

  const char *result;

  result = ext_immu (self, code, valuep);

  if (result)

    return result;

  *valuep = *valuep + 32;

  return 0;

}

static const char*

ins_immus8 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)

{

  if (value & 0x7)

    return "value not an integer multiple of 8";

  return ins_immu (self, value >> 3, code);

}

static const char*

ext_immus8 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)

{

  const char *result;

  result = ext_immu (self, code, valuep);

  if (result)

    return result;

  *valuep = *valuep << 3;

  return 0;

}

static const char*

ins_imms_scaled (const struct ia64_operand *self, ia64_insn value,

		 ia64_insn *code, int scale)

{

  int64_t svalue = value, sign_bit = 0;

  ia64_insn new = 0;

  int i;

  svalue >>= scale;

  for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)

    {

      new |= ((svalue & ((((ia64_insn) 1) << self->field[i].bits) - 1))

	      << self->field[i].shift);

      sign_bit = (svalue >> (self->field[i].bits - 1)) & 1;

      svalue >>= self->field[i].bits;

    }

  if ((!sign_bit && svalue != 0) || (sign_bit && svalue != -1))

    return "integer operand out of range";

  *code |= new;

  return 0;

}

static const char*

ext_imms_scaled (const struct ia64_operand *self, ia64_insn code,

		 ia64_insn *valuep, int scale)

{

  int i, bits = 0, total = 0;

  int64_t val = 0, sign;

  for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)

    {

      bits = self->field[i].bits;

      val |= ((code >> self->field[i].shift)

	      & ((((uint64_t) 1) << bits) - 1)) << total;

      total += bits;

    }

  /* sign extend: */

  sign = (int64_t) 1 << (total - 1);

  val = (val ^ sign) - sign;

  *valuep = (val << scale);

  return 0;

}

static const char*

ins_imms (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)

{

  return ins_imms_scaled (self, value, code, 0);

}

static const char*

ins_immsu4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)

{

  value = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;

  return ins_imms_scaled (self, value, code, 0);

}

static const char*

ext_imms (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)

{

  return ext_imms_scaled (self, code, valuep, 0);

}

static const char*

ins_immsm1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)

{

  --value;

  return ins_imms_scaled (self, value, code, 0);

}

static const char*

ins_immsm1u4 (const struct ia64_operand *self, ia64_insn value,

	      ia64_insn *code)

{

  value = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;

  --value;

  return ins_imms_scaled (self, value, code, 0);

}

static const char*

ext_immsm1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)

{

  const char *res = ext_imms_scaled (self, code, valuep, 0);

  ++*valuep;

  return res;

}

static const char*

ins_imms1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)

{

  return ins_imms_scaled (self, value, code, 1);

}

static const char*

ext_imms1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)

{

  return ext_imms_scaled (self, code, valuep, 1);

}

static const char*

ins_imms4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)

{

  return ins_imms_scaled (self, value, code, 4);

}

static const char*

ext_imms4 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)

{

  return ext_imms_scaled (self, code, valuep, 4);

}

static const char*

ins_imms16 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)

{

  return ins_imms_scaled (self, value, code, 16);

}

static const char*

ext_imms16 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)

{

  return ext_imms_scaled (self, code, valuep, 16);

}

static const char*

ins_cimmu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)

{

  ia64_insn mask = (((ia64_insn) 1) << self->field[0].bits) - 1;

  return ins_immu (self, value ^ mask, code);

}

static const char*

ext_cimmu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)

{

  const char *result;

  ia64_insn mask;

  mask = (((ia64_insn) 1) << self->field[0].bits) - 1;

  result = ext_immu (self, code, valuep);

  if (!result)

    {

      mask = (((ia64_insn) 1) << self->field[0].bits) - 1;

      *valuep ^= mask;

    }

  return result;

}

static const char*

ins_cnt (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)

{

  --value;

  if (value >= ((uint64_t) 1) << self->field[0].bits)

    return "count out of range";

  *code |= value << self->field[0].shift;

  return 0;

}

static const char*

ext_cnt (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)

{

  *valuep = ((code >> self->field[0].shift)

	     & ((((uint64_t) 1) << self->field[0].bits) - 1)) + 1;

  return 0;

}

static const char*

ins_cnt2b (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)

{

  --value;

  if (value > 2)

    return "count must be in range 1..3";

  *code |= value << self->field[0].shift;

  return 0;

}

static const char*

ext_cnt2b (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)

{

  *valuep = ((code >> self->field[0].shift) & 0x3) + 1;

  return 0;

}

static const char*

ins_cnt2c (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)

{

  switch (value)

    {

    case 0:	value = 0; break;

    case 7:	value = 1; break;

    case 15:	value = 2; break;

    case 16:	value = 3; break;

    default:	return "count must be 0, 7, 15, or 16";

    }

  *code |= value << self->field[0].shift;

  return 0;

}

static const char*

ext_cnt2c (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)

{

  ia64_insn value;

  value = (code >> self->field[0].shift) & 0x3;

  switch (value)

    {

    case 0: value =  0; break;

    case 1: value =  7; break;

    case 2: value = 15; break;

    case 3: value = 16; break;

    }

  *valuep = value;

  return 0;

}

static const char*

ins_inc3 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)

{

  int64_t val = value;

  uint64_t sign = 0;

  if (val < 0)

    {

      sign = 0x4;

      value = -value;

    }

  switch (value)

    {

    case  1:	value = 3; break;

    case  4:	value = 2; break;

    case  8:	value = 1; break;

    case 16:	value = 0; break;

    default:	return "count must be +/- 1, 4, 8, or 16";

    }

  *code |= (sign | value) << self->field[0].shift;

  return 0;

}

static const char*

ext_inc3 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)

{

  int64_t val;

  int negate;

  val = (code >> self->field[0].shift) & 0x7;

  negate = val & 0x4;

  switch (val & 0x3)

    {

    case 0: val = 16; break;

    case 1: val =  8; break;

    case 2: val =  4; break;

    case 3: val =  1; break;

    }

  if (negate)

    val = -val;

  *valuep = val;

  return 0;

}

#define CST	IA64_OPND_CLASS_CST

#define REG	IA64_OPND_CLASS_REG

#define IND	IA64_OPND_CLASS_IND

#define ABS	IA64_OPND_CLASS_ABS

#define REL	IA64_OPND_CLASS_REL

#define SDEC	IA64_OPND_FLAG_DECIMAL_SIGNED

#define UDEC	IA64_OPND_FLAG_DECIMAL_UNSIGNED

const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] =

  {

    /* constants: */

    { CST, ins_const, ext_const, "NIL",		{{ 0, 0}}, 0, "<none>" },

    { CST, ins_const, ext_const, "ar.csd",	{{ 0, 0}}, 0, "ar.csd" },

    { CST, ins_const, ext_const, "ar.ccv",	{{ 0, 0}}, 0, "ar.ccv" },

    { CST, ins_const, ext_const, "ar.pfs",	{{ 0, 0}}, 0, "ar.pfs" },

    { CST, ins_const, ext_const, "1",		{{ 0, 0}}, 0, "1" },

    { CST, ins_const, ext_const, "8",		{{ 0, 0}}, 0, "8" },

    { CST, ins_const, ext_const, "16",		{{ 0, 0}}, 0, "16" },

    { CST, ins_const, ext_const, "r0",		{{ 0, 0}}, 0, "r0" },

    { CST, ins_const, ext_const, "ip",		{{ 0, 0}}, 0, "ip" },

    { CST, ins_const, ext_const, "pr",		{{ 0, 0}}, 0, "pr" },

    { CST, ins_const, ext_const, "pr.rot",	{{ 0, 0}}, 0, "pr.rot" },

    { CST, ins_const, ext_const, "psr",		{{ 0, 0}}, 0, "psr" },

    { CST, ins_const, ext_const, "psr.l",	{{ 0, 0}}, 0, "psr.l" },

    { CST, ins_const, ext_const, "psr.um",	{{ 0, 0}}, 0, "psr.um" },

    /* register operands: */

    { REG, ins_reg,   ext_reg,	"ar", {{ 7, 20}}, 0,		/* AR3 */

      "an application register" },

    { REG, ins_reg,   ext_reg,	 "b", {{ 3,  6}}, 0,		/* B1 */

      "a branch register" },

    { REG, ins_reg,   ext_reg,	 "b", {{ 3, 13}}, 0,		/* B2 */

      "a branch register"},

    { REG, ins_reg,   ext_reg,	"cr", {{ 7, 20}}, 0,		/* CR */

      "a control register"},

    { REG, ins_reg,   ext_reg,	 "f", {{ 7,  6}}, 0,		/* F1 */

      "a floating-point register" },

    { REG, ins_reg,   ext_reg,	 "f", {{ 7, 13}}, 0,		/* F2 */

      "a floating-point register" },

    { REG, ins_reg,   ext_reg,	 "f", {{ 7, 20}}, 0,		/* F3 */

      "a floating-point register" },

    { REG, ins_reg,   ext_reg,	 "f", {{ 7, 27}}, 0,		/* F4 */

      "a floating-point register" },

    { REG, ins_reg,   ext_reg,	 "p", {{ 6,  6}}, 0,		/* P1 */

      "a predicate register" },

    { REG, ins_reg,   ext_reg,	 "p", {{ 6, 27}}, 0,		/* P2 */

      "a predicate register" },

    { REG, ins_reg,   ext_reg,	 "r", {{ 7,  6}}, 0,		/* R1 */

      "a general register" },

    { REG, ins_reg,   ext_reg,	 "r", {{ 7, 13}}, 0,		/* R2 */

      "a general register" },

    { REG, ins_reg,   ext_reg,	 "r", {{ 7, 20}}, 0,		/* R3 */

      "a general register" },

    { REG, ins_reg,   ext_reg,	 "r", {{ 2, 20}}, 0,		/* R3_2 */

      "a general register r0-r3" },

    /* memory operands: */

    { IND, ins_reg,   ext_reg,	"",      {{7, 20}}, 0,		/* MR3 */

      "a memory address" },

    /* indirect operands: */

    { IND, ins_reg,   ext_reg,	"cpuid", {{7, 20}}, 0,		/* CPUID_R3 */

      "a cpuid register" },

    { IND, ins_reg,   ext_reg,	"dbr",   {{7, 20}}, 0,		/* DBR_R3 */

      "a dbr register" },

    { IND, ins_reg,   ext_reg,	"dtr",   {{7, 20}}, 0,		/* DTR_R3 */

      "a dtr register" },

    { IND, ins_reg,   ext_reg,	"itr",   {{7, 20}}, 0,		/* ITR_R3 */

      "an itr register" },

    { IND, ins_reg,   ext_reg,	"ibr",   {{7, 20}}, 0,		/* IBR_R3 */

      "an ibr register" },

    { IND, ins_reg,   ext_reg,	"msr",   {{7, 20}}, 0,		/* MSR_R3 */

      "an msr register" },

    { IND, ins_reg,   ext_reg,	"pkr",   {{7, 20}}, 0,		/* PKR_R3 */

      "a pkr register" },

    { IND, ins_reg,   ext_reg,	"pmc",   {{7, 20}}, 0,		/* PMC_R3 */

      "a pmc register" },

    { IND, ins_reg,   ext_reg,	"pmd",   {{7, 20}}, 0,		/* PMD_R3 */

      "a pmd register" },

    { IND, ins_reg,   ext_reg,	"rr",    {{7, 20}}, 0,		/* RR_R3 */

      "an rr register" },

    /* immediate operands: */

    { ABS, ins_cimmu, ext_cimmu, 0, {{ 5, 20 }}, UDEC,		/* CCNT5 */

      "a 5-bit count (0-31)" },

    { ABS, ins_cnt,   ext_cnt,   0, {{ 2, 27 }}, UDEC,		/* CNT2a */

      "a 2-bit count (1-4)" },

    { ABS, ins_cnt2b, ext_cnt2b, 0, {{ 2, 27 }}, UDEC,		/* CNT2b */

      "a 2-bit count (1-3)" },

    { ABS, ins_cnt2c, ext_cnt2c, 0, {{ 2, 30 }}, UDEC,		/* CNT2c */

      "a count (0, 7, 15, or 16)" },

    { ABS, ins_immu,  ext_immu,  0, {{ 5, 14}}, UDEC,		/* CNT5 */

      "a 5-bit count (0-31)" },

    { ABS, ins_immu,  ext_immu,  0, {{ 6, 27}}, UDEC,		/* CNT6 */

      "a 6-bit count (0-63)" },

    { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 20}}, UDEC,		/* CPOS6a */

      "a 6-bit bit pos (0-63)" },

    { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 14}}, UDEC,		/* CPOS6b */

      "a 6-bit bit pos (0-63)" },

    { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 31}}, UDEC,		/* CPOS6c */

      "a 6-bit bit pos (0-63)" },

    { ABS, ins_imms,  ext_imms,  0, {{ 1, 36}}, SDEC,		/* IMM1 */

      "a 1-bit integer (-1, 0)" },

    { ABS, ins_immu,  ext_immu,  0, {{ 2, 13}}, UDEC,		/* IMMU2 */

      "a 2-bit unsigned (0-3)" },

    { ABS, ins_immu5b,  ext_immu5b,  0, {{ 5, 14}}, UDEC,	/* IMMU5b */

      "a 5-bit unsigned (32 + (0-31))" },

    { ABS, ins_immu,  ext_immu,  0, {{ 7, 13}}, 0,		/* IMMU7a */

      "a 7-bit unsigned (0-127)" },

    { ABS, ins_immu,  ext_immu,  0, {{ 7, 20}}, 0,		/* IMMU7b */

      "a 7-bit unsigned (0-127)" },

    { ABS, ins_immu,  ext_immu,  0, {{ 7, 13}}, UDEC,		/* SOF */

      "a frame size (register count)" },

    { ABS, ins_immu,  ext_immu,  0, {{ 7, 20}}, UDEC,		/* SOL */

      "a local register count" },

    { ABS, ins_immus8,ext_immus8,0, {{ 4, 27}}, UDEC,		/* SOR */

      "a rotating register count (integer multiple of 8)" },

    { ABS, ins_imms,  ext_imms,  0,				/* IMM8 */

      {{ 7, 13}, { 1, 36}}, SDEC,

      "an 8-bit integer (-128-127)" },

    { ABS, ins_immsu4,  ext_imms,  0,				/* IMM8U4 */

      {{ 7, 13}, { 1, 36}}, SDEC,

      "an 8-bit signed integer for 32-bit unsigned compare (-128-127)" },

    { ABS, ins_immsm1,  ext_immsm1,  0,				/* IMM8M1 */

      {{ 7, 13}, { 1, 36}}, SDEC,

      "an 8-bit integer (-127-128)" },

    { ABS, ins_immsm1u4,  ext_immsm1,  0,			/* IMM8M1U4 */

      {{ 7, 13}, { 1, 36}}, SDEC,

      "an 8-bit integer for 32-bit unsigned compare (-127-(-1),1-128,0x100000000)" },

    { ABS, ins_immsm1,  ext_immsm1,  0,				/* IMM8M1U8 */

      {{ 7, 13}, { 1, 36}}, SDEC,

      "an 8-bit integer for 64-bit unsigned compare (-127-(-1),1-128,0x10000000000000000)" },

    { ABS, ins_immu,  ext_immu,  0, {{ 2, 33}, { 7, 20}}, 0,	/* IMMU9 */

      "a 9-bit unsigned (0-511)" },

    { ABS, ins_imms,  ext_imms,  0,				/* IMM9a */

      {{ 7,  6}, { 1, 27}, { 1, 36}}, SDEC,

      "a 9-bit integer (-256-255)" },

    { ABS, ins_imms,  ext_imms, 0,				/* IMM9b */

      {{ 7, 13}, { 1, 27}, { 1, 36}}, SDEC,

      "a 9-bit integer (-256-255)" },

    { ABS, ins_imms,  ext_imms, 0,				/* IMM14 */

      {{ 7, 13}, { 6, 27}, { 1, 36}}, SDEC,

      "a 14-bit integer (-8192-8191)" },

    { ABS, ins_imms1, ext_imms1, 0,				/* IMM17 */

      {{ 7,  6}, { 8, 24}, { 1, 36}}, 0,

      "a 17-bit integer (-65536-65535)" },

    { ABS, ins_immu,  ext_immu,  0, {{20,  6}, { 1, 36}}, 0,	/* IMMU21 */

      "a 21-bit unsigned" },

    { ABS, ins_imms,  ext_imms,  0,				/* IMM22 */

      {{ 7, 13}, { 9, 27}, { 5, 22}, { 1, 36}}, SDEC,

      "a 22-bit signed integer" },

    { ABS, ins_immu,  ext_immu,  0,				/* IMMU24 */

      {{21,  6}, { 2, 31}, { 1, 36}}, 0,

      "a 24-bit unsigned" },

    { ABS, ins_imms16,ext_imms16,0, {{27,  6}, { 1, 36}}, 0,	/* IMM44 */

      "a 44-bit unsigned (least 16 bits ignored/zeroes)" },

    { ABS, ins_rsvd,  ext_rsvd,	0, {{0,  0}}, 0,		/* IMMU62 */

      "a 62-bit unsigned" },

    { ABS, ins_rsvd,  ext_rsvd,	0, {{0,  0}}, 0,		/* IMMU64 */

      "a 64-bit unsigned" },

    { ABS, ins_inc3,  ext_inc3,  0, {{ 3, 13}}, SDEC,		/* INC3 */

      "an increment (+/- 1, 4, 8, or 16)" },

    { ABS, ins_cnt,   ext_cnt,   0, {{ 4, 27}}, UDEC,		/* LEN4 */

      "a 4-bit length (1-16)" },

    { ABS, ins_cnt,   ext_cnt,   0, {{ 6, 27}}, UDEC,		/* LEN6 */

      "a 6-bit length (1-64)" },

    { ABS, ins_immu,  ext_immu,  0, {{ 4, 20}},	0,		/* MBTYPE4 */

      "a mix type (@rev, @mix, @shuf, @alt, or @brcst)" },

    { ABS, ins_immu,  ext_immu,  0, {{ 8, 20}},	0,		/* MBTYPE8 */

      "an 8-bit mix type" },

    { ABS, ins_immu,  ext_immu,  0, {{ 6, 14}}, UDEC,		/* POS6 */

      "a 6-bit bit pos (0-63)" },

    { REL, ins_imms4, ext_imms4, 0, {{ 7,  6}, { 2, 33}}, 0,	/* TAG13 */

      "a branch tag" },

    { REL, ins_imms4, ext_imms4, 0, {{ 9, 24}}, 0,		/* TAG13b */

      "a branch tag" },

    { REL, ins_imms4, ext_imms4, 0, {{20,  6}, { 1, 36}}, 0,	/* TGT25 */

      "a branch target" },

    { REL, ins_imms4, ext_imms4, 0,				/* TGT25b */

      {{ 7,  6}, {13, 20}, { 1, 36}}, 0,

      "a branch target" },

    { REL, ins_imms4, ext_imms4, 0, {{20, 13}, { 1, 36}}, 0,	/* TGT25c */

      "a branch target" },

    { REL, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0,                  /* TGT64  */

      "a branch target" },

    { ABS, ins_const, ext_const, 0, {{0, 0}}, 0,		/* LDXMOV */

      "ldxmov target" },

  };

/* ia64-asmtab.h -- Header for compacted IA-64 opcode tables.

   Copyright 1999, 2000 Free Software Foundation, Inc.

   Contributed by Bob Manson of Cygnus Support <manson@cygnus.com>

   This file is part of GDB, GAS, and the GNU binutils.

   GDB, GAS, and the GNU binutils are free software; you can redistribute

   them and/or modify them under the terms of the GNU General Public

   License as published by the Free Software Foundation; either version

   2, or (at your option) any later version.

   GDB, GAS, and the GNU binutils are distributed in the hope that they

   will be useful, but WITHOUT ANY WARRANTY; without even the implied

   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See

   the GNU General Public License for more details.

   You should have received a copy of the GNU General Public License

   along with this file; see the file COPYING.  If not, write to the

   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA

   02110-1301, USA.  */

/* The primary opcode table is made up of the following: */

struct ia64_main_table

{

  /* The entry in the string table that corresponds to the name of this

     opcode. */

  unsigned short name_index;

  /* The type of opcode; corresponds to the TYPE field in

     struct ia64_opcode. */

  unsigned char opcode_type;

  /* The number of outputs for this opcode. */

  unsigned char num_outputs;

  /* The base insn value for this opcode.  It may be modified by completers. */

  ia64_insn opcode;

  /* The mask of valid bits in OPCODE. Zeros indicate operand fields. */

  ia64_insn mask;

  /* The operands of this instruction.  Corresponds to the OPERANDS field

     in struct ia64_opcode. */

  unsigned char operands[5];

  /* The flags for this instruction.  Corresponds to the FLAGS field in

     struct ia64_opcode. */

  short flags;

  /* The tree of completers for this instruction; this is an offset into

     completer_table. */

  short completers;

};

/* Each instruction has a set of possible "completers", or additional

   suffixes that can alter the instruction's behavior, and which has

   potentially different dependencies.

   The completer entries modify certain bits in the instruction opcode.

   Which bits are to be modified are marked by the BITS, MASK and

   OFFSET fields.  The completer entry may also note dependencies for the

   opcode.

   These completers are arranged in a DAG; the pointers are indexes

   into the completer_table array.  The completer DAG is searched by

   find_completer () and ia64_find_matching_opcode ().

   Note that each completer needs to be applied in turn, so that if we

   have the instruction

	cmp.lt.unc

   the completer entries for both "lt" and "unc" would need to be applied

   to the opcode's value.

   Some instructions do not require any completers; these contain an

   empty completer entry.  Instructions that require a completer do

   not contain an empty entry.

   Terminal completers (those completers that validly complete an

   instruction) are marked by having the TERMINAL_COMPLETER flag set.

   Only dependencies listed in the terminal completer for an opcode are

   considered to apply to that opcode instance. */

struct ia64_completer_table

{

  /* The bit value that this completer sets. */

  unsigned int bits;

  /* And its mask. 1s are bits that are to be modified in the

     instruction. */

  unsigned int mask;

  /* The entry in the string table that corresponds to the name of this

     completer. */

  unsigned short name_index;

  /* An alternative completer, or -1 if this is the end of the chain. */

  short alternative;

  /* A pointer to the DAG of completers that can potentially follow

     this one, or -1. */

  short subentries;

  /* The bit offset in the instruction where BITS and MASK should be

     applied. */

  unsigned char offset : 7;

  unsigned char terminal_completer : 1;

  /* Index into the dependency list table */

  short dependencies;

};

/* This contains sufficient information for the disassembler to resolve

   the complete name of the original instruction.  */

struct ia64_dis_names

{

  /* COMPLETER_INDEX represents the tree of completers that make up

     the instruction.  The LSB represents the top of the tree for the

     specified instruction.

     A 0 bit indicates to go to the next alternate completer via the

     alternative field; a 1 bit indicates that the current completer

     is part of the instruction, and to go down the subentries index.

     We know we've reached the final completer when we run out of 1

     bits.

     There is always at least one 1 bit. */

  unsigned int completer_index : 20;

  /* The index in the main_table[] array for the instruction. */

  unsigned short insn_index : 11;

  /* If set, the next entry in this table is an alternate possibility

     for this instruction encoding.  Which one to use is determined by

     the instruction type and other factors (see opcode_verify ()).  */

  unsigned int next_flag : 1;

  /* The disassembly priority of this entry among instructions. */

  unsigned short priority;

};

static const char * const ia64_strings[] = {

  "", "0", "1", "a", "acq", "add", "addl", "addp4", "adds", "alloc", "and",

  "andcm", "b", "bias", "br", "break", "brl", "brp", "bsw", "c", "call",

  "cexit", "chk", "cloop", "clr", "clrrrb", "cmp", "cmp4", "cmp8xchg16",

  "cmpxchg1", "cmpxchg2", "cmpxchg4", "cmpxchg8", "cond", "cover", "ctop",

  "czx1", "czx2", "d", "dep", "dpnt", "dptk", "e", "epc", "eq", "excl",

  "exit", "exp", "extr", "f", "fabs", "fadd", "famax", "famin", "fand",

  "fandcm", "fault", "fc", "fchkf", "fclass", "fclrf", "fcmp", "fcvt",

  "fetchadd4", "fetchadd8", "few", "fill", "flushrs", "fma", "fmax",

  "fmerge", "fmin", "fmix", "fmpy", "fms", "fneg", "fnegabs", "fnma",

  "fnmpy", "fnorm", "for", "fpabs", "fpack", "fpamax", "fpamin", "fpcmp",

  "fpcvt", "fpma", "fpmax", "fpmerge", "fpmin", "fpmpy", "fpms", "fpneg",

  "fpnegabs", "fpnma", "fpnmpy", "fprcpa", "fprsqrta", "frcpa", "frsqrta",

  "fselect", "fsetc", "fsub", "fswap", "fsxt", "fwb", "fx", "fxor", "fxu",

  "g", "ga", "ge", "getf", "geu", "gt", "gtu", "h", "hint", "hu", "i", "ia",

  "imp", "invala", "itc", "itr", "l", "ld1", "ld16", "ld2", "ld4", "ld8",

  "ldf", "ldf8", "ldfd", "ldfe", "ldfp8", "ldfpd", "ldfps", "ldfs", "le",

  "leu", "lfetch", "loadrs", "loop", "lr", "lt", "ltu", "lu", "m", "many",

  "mf", "mix1", "mix2", "mix4", "mov", "movl", "mux1", "mux2", "nc", "ne",

  "neq", "nge", "ngt", "nl", "nle", "nlt", "nm", "nop", "nr", "ns", "nt1",

  "nt2", "nta", "nz", "or", "orcm", "ord", "pack2", "pack4", "padd1",

  "padd2", "padd4", "pavg1", "pavg2", "pavgsub1", "pavgsub2", "pcmp1",

  "pcmp2", "pcmp4", "pmax1", "pmax2", "pmin1", "pmin2", "pmpy2", "pmpyshr2",

  "popcnt", "pr", "probe", "psad1", "pshl2", "pshl4", "pshladd2", "pshr2",

  "pshr4", "pshradd2", "psub1", "psub2", "psub4", "ptc", "ptr", "r", "raz",

  "rel", "ret", "rfi", "rsm", "rum", "rw", "s", "s0", "s1", "s2", "s3",

  "sa", "se", "setf", "shl", "shladd", "shladdp4", "shr", "shrp", "sig",

  "spill", "spnt", "sptk", "srlz", "ssm", "sss", "st1", "st16", "st2",

  "st4", "st8", "stf", "stf8", "stfd", "stfe", "stfs", "sub", "sum", "sxt1",

  "sxt2", "sxt4", "sync", "tak", "tbit", "tf", "thash", "tnat", "tpa",

  "trunc", "ttag", "u", "unc", "unord", "unpack1", "unpack2", "unpack4",

  "uss", "uus", "uuu", "vmsw", "w", "wexit", "wtop", "x", "xchg1", "xchg2",

  "xchg4", "xchg8", "xf", "xma", "xmpy", "xor", "xuf", "z", "zxt1", "zxt2",

  "zxt4",

};

static const struct ia64_dependency

dependencies[] = {

  { "ALAT", 0, 0, 0, -1, NULL, },

  { "AR[BSP]", 26, 0, 2, 17, NULL, },

  { "AR[BSPSTORE]", 26, 0, 2, 18, NULL, },

  { "AR[CCV]", 26, 0, 2, 32, NULL, },

  { "AR[CFLG]", 26, 0, 2, 27, NULL, },

  { "AR[CSD]", 26, 0, 2, 25, NULL, },

  { "AR[EC]", 26, 0, 2, 66, NULL, },

  { "AR[EFLAG]", 26, 0, 2, 24, NULL, },

  { "AR[FCR]", 26, 0, 2, 21, NULL, },

  { "AR[FDR]", 26, 0, 2, 30, NULL, },

  { "AR[FIR]", 26, 0, 2, 29, NULL, },

  { "AR[FPSR].sf0.controls", 30, 0, 2, -1, NULL, },

  { "AR[FPSR].sf1.controls", 30, 0, 2, -1, NULL, },

  { "AR[FPSR].sf2.controls", 30, 0, 2, -1, NULL, },

  { "AR[FPSR].sf3.controls", 30, 0, 2, -1, NULL, },

  { "AR[FPSR].sf0.flags", 30, 0, 2, -1, NULL, },

  { "AR[FPSR].sf1.flags", 30, 0, 2, -1, NULL, },

  { "AR[FPSR].sf2.flags", 30, 0, 2, -1, NULL, },

  { "AR[FPSR].sf3.flags", 30, 0, 2, -1, NULL, },

  { "AR[FPSR].traps", 30, 0, 2, -1, NULL, },

  { "AR[FPSR].rv", 30, 0, 2, -1, NULL, },

  { "AR[FSR]", 26, 0, 2, 28, NULL, },

  { "AR[ITC]", 26, 0, 2, 44, NULL, },

  { "AR[K%], % in 0 - 7", 1, 0, 2, -1, NULL, },

  { "AR[LC]", 26, 0, 2, 65, NULL, },

  { "AR[PFS]", 26, 0, 2, 64, NULL, },

  { "AR[PFS]", 26, 0, 2, 64, NULL, },

  { "AR[PFS]", 26, 0, 0, 64, NULL, },

  { "AR[RNAT]", 26, 0, 2, 19, NULL, },

  { "AR[RSC]", 26, 0, 2, 16, NULL, },

  { "AR[SSD]", 26, 0, 2, 26, NULL, },

  { "AR[UNAT]{%}, % in 0 - 63", 2, 0, 2, -1, NULL, },

  { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111", 3, 0, 0, -1, NULL, },

  { "AR%, % in 48-63, 112-127", 4, 0, 2, -1, NULL, },

  { "BR%, % in 0 - 7", 5, 0, 2, -1, NULL, },

  { "BR%, % in 0 - 7", 5, 0, 0, -1, NULL, },

  { "BR%, % in 0 - 7", 5, 0, 2, -1, NULL, },

  { "CFM", 6, 0, 2, -1, NULL, },

  { "CFM", 6, 0, 2, -1, NULL, },

  { "CFM", 6, 0, 2, -1, NULL, },

  { "CFM", 6, 0, 2, -1, NULL, },

  { "CFM", 6, 0, 0, -1, NULL, },

  { "CPUID#", 7, 0, 5, -1, NULL, },

  { "CR[CMCV]", 27, 0, 3, 74, NULL, },

  { "CR[DCR]", 27, 0, 3, 0, NULL, },

  { "CR[EOI]", 27, 0, 7, 67, "SC Section 5.8.3.4, \"End of External Interrupt Register (EOI Ð CR67)\" on page 2:119", },

  { "CR[GPTA]", 27, 0, 3, 9, NULL, },

  { "CR[IFA]", 27, 0, 1, 20, NULL, },

  { "CR[IFA]", 27, 0, 3, 20, NULL, },

  { "CR[IFS]", 27, 0, 3, 23, NULL, },

  { "CR[IFS]", 27, 0, 1, 23, NULL, },

  { "CR[IFS]", 27, 0, 1, 23, NULL, },

  { "CR[IHA]", 27, 0, 3, 25, NULL, },

  { "CR[IIM]", 27, 0, 3, 24, NULL, },

  { "CR[IIP]", 27, 0, 3, 19, NULL, },

  { "CR[IIP]", 27, 0, 1, 19, NULL, },

  { "CR[IIPA]", 27, 0, 3, 22, NULL, },

  { "CR[IPSR]", 27, 0, 3, 16, NULL, },

  { "CR[IPSR]", 27, 0, 1, 16, NULL, },

  { "CR[IRR%], % in 0 - 3", 8, 0, 3, -1, NULL, },

  { "CR[ISR]", 27, 0, 3, 17, NULL, },

  { "CR[ITIR]", 27, 0, 3, 21, NULL, },

  { "CR[ITIR]", 27, 0, 1, 21, NULL, },

  { "CR[ITM]", 27, 0, 3, 1, NULL, },

  { "CR[ITV]", 27, 0, 3, 72, NULL, },

  { "CR[IVA]", 27, 0, 4, 2, NULL, },

  { "CR[IVR]", 27, 0, 7, 65, "SC Section 5.8.3.2, \"External Interrupt Vector Register (IVR Ð CR65)\" on page 2:118", },

  { "CR[LID]", 27, 0, 7, 64, "SC Section 5.8.3.1, \"Local ID (LID Ð CR64)\" on page 2:117", },

  { "CR[LRR%], % in 0 - 1", 9, 0, 3, -1, NULL, },

  { "CR[PMV]", 27, 0, 3, 73, NULL, },

  { "CR[PTA]", 27, 0, 3, 8, NULL, },

  { "CR[TPR]", 27, 0, 3, 66, NULL, },

  { "CR[TPR]", 27, 0, 7, 66, "SC Section 5.8.3.3, \"Task Priority Register (TPR Ð CR66)\" on page 2:119", },

  { "CR[TPR]", 27, 0, 1, 66, NULL, },

  { "CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127", 10, 0, 0, -1, NULL, },

  { "DBR#", 11, 0, 2, -1, NULL, },

  { "DBR#", 11, 0, 3, -1, NULL, },

  { "DTC", 0, 0, 3, -1, NULL, },

  { "DTC", 0, 0, 2, -1, NULL, },

  { "DTC", 0, 0, 0, -1, NULL, },

  { "DTC", 0, 0, 2, -1, NULL, },

  { "DTC_LIMIT*", 0, 0, 2, -1, NULL, },

  { "DTR", 0, 0, 3, -1, NULL, },

  { "DTR", 0, 0, 2, -1, NULL, },

  { "DTR", 0, 0, 3, -1, NULL, },

  { "DTR", 0, 0, 0, -1, NULL, },

  { "DTR", 0, 0, 2, -1, NULL, },

  { "FR%, % in 0 - 1", 12, 0, 0, -1, NULL, },

  { "FR%, % in 2 - 127", 13, 0, 2, -1, NULL, },

  { "FR%, % in 2 - 127", 13, 0, 0, -1, NULL, },

  { "GR0", 14, 0, 0, -1, NULL, },

  { "GR%, % in 1 - 127", 15, 0, 0, -1, NULL, },

  { "GR%, % in 1 - 127", 15, 0, 2, -1, NULL, },

  { "IBR#", 16, 0, 2, -1, NULL, },

  { "InService*", 17, 0, 3, -1, NULL, },

  { "InService*", 17, 0, 2, -1, NULL, },

  { "InService*", 17, 0, 2, -1, NULL, },

  { "IP", 0, 0, 0, -1, NULL, },

  { "ITC", 0, 0, 4, -1, NULL, },

  { "ITC", 0, 0, 2, -1, NULL, },

  { "ITC", 0, 0, 0, -1, NULL, },

  { "ITC", 0, 0, 4, -1, NULL, },

  { "ITC", 0, 0, 2, -1, NULL, },

  { "ITC_LIMIT*", 0, 0, 2, -1, NULL, },

  { "ITR", 0, 0, 2, -1, NULL, },

  { "ITR", 0, 0, 4, -1, NULL, },

  { "ITR", 0, 0, 2, -1, NULL, },

  { "ITR", 0, 0, 0, -1, NULL, },

  { "ITR", 0, 0, 4, -1, NULL, },

  { "memory", 0, 0, 0, -1, NULL, },

  { "MSR#", 18, 0, 5, -1, NULL, },

  { "PKR#", 19, 0, 3, -1, NULL, },

  { "PKR#", 19, 0, 0, -1, NULL, },

  { "PKR#", 19, 0, 2, -1, NULL, },

  { "PKR#", 19, 0, 2, -1, NULL, },

  { "PMC#", 20, 0, 2, -1, NULL, },

  { "PMC#", 20, 0, 7, -1, "SC Section 7.2.1, \"Generic Performance Counter Registers\" for PMC[0].fr on page 2:150", },

  { "PMD#", 21, 0, 2, -1, NULL, },

  { "PR0", 0, 0, 0, -1, NULL, },

  { "PR%, % in 1 - 15", 22, 0, 2, -1, NULL, },

  { "PR%, % in 1 - 15", 22, 0, 2, -1, NULL, },

  { "PR%, % in 1 - 15", 22, 0, 0, -1, NULL, },

  { "PR%, % in 16 - 62", 23, 0, 2, -1, NULL, },

  { "PR%, % in 16 - 62", 23, 0, 2, -1, NULL, },

  { "PR%, % in 16 - 62", 23, 0, 0, -1, NULL, },

  { "PR63", 24, 0, 2, -1, NULL, },

  { "PR63", 24, 0, 2, -1, NULL, },

  { "PR63", 24, 0, 0, -1, NULL, },

  { "PSR.ac", 28, 0, 1, 3, NULL, },

  { "PSR.ac", 28, 0, 3, 3, NULL, },

  { "PSR.ac", 28, 0, 2, 3, NULL, },

  { "PSR.ac", 28, 0, 2, 3, NULL, },

  { "PSR.be", 28, 0, 1, 1, NULL, },

  { "PSR.be", 28, 0, 3, 1, NULL, },

  { "PSR.be", 28, 0, 2, 1, NULL, },

  { "PSR.be", 28, 0, 2, 1, NULL, },

  { "PSR.bn", 28, 0, 2, 44, NULL, },

  { "PSR.cpl", 28, 0, 1, 32, NULL, },

  { "PSR.cpl", 28, 0, 2, 32, NULL, },

  { "PSR.da", 28, 0, 2, 38, NULL, },

  { "PSR.db", 28, 0, 3, 24, NULL, },

  { "PSR.db", 28, 0, 2, 24, NULL, },

  { "PSR.db", 28, 0, 2, 24, NULL, },

  { "PSR.dd", 28, 0, 2, 39, NULL, },

  { "PSR.dfh", 28, 0, 3, 19, NULL, },

  { "PSR.dfh", 28, 0, 2, 19, NULL, },

  { "PSR.dfh", 28, 0, 2, 19, NULL, },

  { "PSR.dfl", 28, 0, 3, 18, NULL, },

  { "PSR.dfl", 28, 0, 2, 18, NULL, },

  { "PSR.dfl", 28, 0, 2, 18, NULL, },

  { "PSR.di", 28, 0, 3, 22, NULL, },

  { "PSR.di", 28, 0, 2, 22, NULL, },

  { "PSR.di", 28, 0, 2, 22, NULL, },

  { "PSR.dt", 28, 0, 3, 17, NULL, },

  { "PSR.dt", 28, 0, 2, 17, NULL, },

  { "PSR.dt", 28, 0, 2, 17, NULL, },

  { "PSR.ed", 28, 0, 2, 43, NULL, },

  { "PSR.i", 28, 0, 2, 14, NULL, },

  { "PSR.ia", 28, 0, 0, 14, NULL, },

  { "PSR.ic", 28, 0, 2, 13, NULL, },

  { "PSR.ic", 28, 0, 3, 13, NULL, },

  { "PSR.ic", 28, 0, 2, 13, NULL, },

  { "PSR.id", 28, 0, 0, 14, NULL, },

  { "PSR.is", 28, 0, 0, 14, NULL, },

  { "PSR.it", 28, 0, 2, 14, NULL, },

  { "PSR.lp", 28, 0, 2, 25, NULL, },

  { "PSR.lp", 28, 0, 3, 25, NULL, },

  { "PSR.lp", 28, 0, 2, 25, NULL, },

  { "PSR.mc", 28, 0, 2, 35, NULL, },

  { "PSR.mfh", 28, 0, 2, 5, NULL, },

  { "PSR.mfl", 28, 0, 2, 4, NULL, },

  { "PSR.pk", 28, 0, 3, 15, NULL, },

  { "PSR.pk", 28, 0, 2, 15, NULL, },

  { "PSR.pk", 28, 0, 2, 15, NULL, },

  { "PSR.pp", 28, 0, 2, 21, NULL, },

  { "PSR.ri", 28, 0, 0, 41, NULL, },

  { "PSR.rt", 28, 0, 2, 27, NULL, },

  { "PSR.rt", 28, 0, 3, 27, NULL, },

  { "PSR.rt", 28, 0, 2, 27, NULL, },

  { "PSR.si", 28, 0, 2, 23, NULL, },

  { "PSR.si", 28, 0, 3, 23, NULL, },

  { "PSR.si", 28, 0, 2, 23, NULL, },

  { "PSR.sp", 28, 0, 2, 20, NULL, },

  { "PSR.sp", 28, 0, 3, 20, NULL, },

  { "PSR.sp", 28, 0, 2, 20, NULL, },

  { "PSR.ss", 28, 0, 2, 40, NULL, },

  { "PSR.tb", 28, 0, 3, 26, NULL, },

  { "PSR.tb", 28, 0, 2, 26, NULL, },

  { "PSR.tb", 28, 0, 2, 26, NULL, },

  { "PSR.up", 28, 0, 2, 2, NULL, },

  { "PSR.vm", 28, 0, 1, 46, NULL, },

  { "PSR.vm", 28, 0, 2, 46, NULL, },

  { "RR#", 25, 0, 3, -1, NULL, },

  { "RR#", 25, 0, 2, -1, NULL, },

  { "RSE", 29, 0, 2, -1, NULL, },

  { "ALAT", 0, 1, 0, -1, NULL, },

  { "AR[BSP]", 26, 1, 2, 17, NULL, },

  { "AR[BSPSTORE]", 26, 1, 2, 18, NULL, },

  { "AR[CCV]", 26, 1, 2, 32, NULL, },

  { "AR[CFLG]", 26, 1, 2, 27, NULL, },

  { "AR[CSD]", 26, 1, 2, 25, NULL, },

  { "AR[EC]", 26, 1, 2, 66, NULL, },

  { "AR[EFLAG]", 26, 1, 2, 24, NULL, },

  { "AR[FCR]", 26, 1, 2, 21, NULL, },

  { "AR[FDR]", 26, 1, 2, 30, NULL, },

  { "AR[FIR]", 26, 1, 2, 29, NULL, },

  { "AR[FPSR].sf0.controls", 30, 1, 2, -1, NULL, },

  { "AR[FPSR].sf1.controls", 30, 1, 2, -1, NULL, },

  { "AR[FPSR].sf2.controls", 30, 1, 2, -1, NULL, },

  { "AR[FPSR].sf3.controls", 30, 1, 2, -1, NULL, },

  { "AR[FPSR].sf0.flags", 30, 1, 0, -1, NULL, },

  { "AR[FPSR].sf0.flags", 30, 1, 2, -1, NULL, },

  { "AR[FPSR].sf0.flags", 30, 1, 2, -1, NULL, },

  { "AR[FPSR].sf1.flags", 30, 1, 0, -1, NULL, },

  { "AR[FPSR].sf1.flags", 30, 1, 2, -1, NULL, },

  { "AR[FPSR].sf1.flags", 30, 1, 2, -1, NULL, },

  { "AR[FPSR].sf2.flags", 30, 1, 0, -1, NULL, },

  { "AR[FPSR].sf2.flags", 30, 1, 2, -1, NULL, },

  { "AR[FPSR].sf2.flags", 30, 1, 2, -1, NULL, },

  { "AR[FPSR].sf3.flags", 30, 1, 0, -1, NULL, },

  { "AR[FPSR].sf3.flags", 30, 1, 2, -1, NULL, },

  { "AR[FPSR].sf3.flags", 30, 1, 2, -1, NULL, },

  { "AR[FPSR].rv", 30, 1, 2, -1, NULL, },

  { "AR[FPSR].traps", 30, 1, 2, -1, NULL, },

  { "AR[FSR]", 26, 1, 2, 28, NULL, },

  { "AR[ITC]", 26, 1, 2, 44, NULL, },

  { "AR[K%], % in 0 - 7", 1, 1, 2, -1, NULL, },

  { "AR[LC]", 26, 1, 2, 65, NULL, },

  { "AR[PFS]", 26, 1, 0, 64, NULL, },

  { "AR[PFS]", 26, 1, 2, 64, NULL, },

  { "AR[PFS]", 26, 1, 2, 64, NULL, },

  { "AR[RNAT]", 26, 1, 2, 19, NULL, },

  { "AR[RSC]", 26, 1, 2, 16, NULL, },

  { "AR[SSD]", 26, 1, 2, 26, NULL, },

  { "AR[UNAT]{%}, % in 0 - 63", 2, 1, 2, -1, NULL, },

  { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111", 3, 1, 0, -1, NULL, },

  { "AR%, % in 48 - 63, 112-127", 4, 1, 2, -1, NULL, },

  { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, },