root / hw / mips_r4k.c @ 9042c0e2
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1 | e16fe40c | ths | /*
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2 | e16fe40c | ths | * QEMU/MIPS pseudo-board
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3 | e16fe40c | ths | *
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4 | e16fe40c | ths | * emulates a simple machine with ISA-like bus.
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5 | e16fe40c | ths | * ISA IO space mapped to the 0x14000000 (PHYS) and
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6 | e16fe40c | ths | * ISA memory at the 0x10000000 (PHYS, 16Mb in size).
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7 | e16fe40c | ths | * All peripherial devices are attached to this "bus" with
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8 | e16fe40c | ths | * the standard PC ISA addresses.
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9 | e16fe40c | ths | */
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10 | 6af0bf9c | bellard | #include "vl.h" |
11 | 6af0bf9c | bellard | |
12 | 6af0bf9c | bellard | #define BIOS_FILENAME "mips_bios.bin" |
13 | 6af0bf9c | bellard | //#define BIOS_FILENAME "system.bin"
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14 | 5dc4b744 | ths | #ifdef MIPS_HAS_MIPS64
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15 | 5dc4b744 | ths | #define INITRD_LOAD_ADDR (int64_t)0x80800000 |
16 | 5dc4b744 | ths | #else
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17 | 5dc4b744 | ths | #define INITRD_LOAD_ADDR (int32_t)0x80800000 |
18 | 5dc4b744 | ths | #endif
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19 | 6af0bf9c | bellard | |
20 | 5dc4b744 | ths | #define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000)) |
21 | 66a93e0f | bellard | |
22 | 58126404 | pbrook | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
23 | 58126404 | pbrook | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; |
24 | 58126404 | pbrook | static const int ide_irq[2] = { 14, 15 }; |
25 | 58126404 | pbrook | |
26 | eddbd288 | ths | static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; |
27 | eddbd288 | ths | static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; |
28 | eddbd288 | ths | |
29 | 6af0bf9c | bellard | extern FILE *logfile;
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30 | 6af0bf9c | bellard | |
31 | e16fe40c | ths | static PITState *pit; /* PIT i8254 */ |
32 | 697584ab | bellard | |
33 | e16fe40c | ths | /*i8254 PIT is attached to the IRQ0 at PIC i8259 */
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34 | e16fe40c | ths | /*The PIC is attached to the MIPS CPU INT0 pin */
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35 | 73133662 | bellard | static void pic_irq_request(void *opaque, int level) |
36 | 6af0bf9c | bellard | { |
37 | c68ea704 | bellard | CPUState *env = first_cpu; |
38 | 73133662 | bellard | if (level) {
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39 | c68ea704 | bellard | env->CP0_Cause |= 0x00000400;
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40 | c68ea704 | bellard | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
41 | 6af0bf9c | bellard | } else {
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42 | c68ea704 | bellard | env->CP0_Cause &= ~0x00000400;
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43 | c68ea704 | bellard | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
44 | 6af0bf9c | bellard | } |
45 | 6af0bf9c | bellard | } |
46 | 6af0bf9c | bellard | |
47 | 6ae81775 | ths | static void mips_qemu_writel (void *opaque, target_phys_addr_t addr, |
48 | 6ae81775 | ths | uint32_t val) |
49 | 6ae81775 | ths | { |
50 | 6ae81775 | ths | if ((addr & 0xffff) == 0 && val == 42) |
51 | 6ae81775 | ths | qemu_system_reset_request (); |
52 | 6ae81775 | ths | else if ((addr & 0xffff) == 4 && val == 42) |
53 | 6ae81775 | ths | qemu_system_shutdown_request (); |
54 | 6ae81775 | ths | } |
55 | 6ae81775 | ths | |
56 | 6ae81775 | ths | static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr) |
57 | 6ae81775 | ths | { |
58 | 6ae81775 | ths | return 0; |
59 | 6ae81775 | ths | } |
60 | 6ae81775 | ths | |
61 | 6ae81775 | ths | static CPUWriteMemoryFunc *mips_qemu_write[] = {
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62 | 6ae81775 | ths | &mips_qemu_writel, |
63 | 6ae81775 | ths | &mips_qemu_writel, |
64 | 6ae81775 | ths | &mips_qemu_writel, |
65 | 6ae81775 | ths | }; |
66 | 6ae81775 | ths | |
67 | 6ae81775 | ths | static CPUReadMemoryFunc *mips_qemu_read[] = {
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68 | 6ae81775 | ths | &mips_qemu_readl, |
69 | 6ae81775 | ths | &mips_qemu_readl, |
70 | 6ae81775 | ths | &mips_qemu_readl, |
71 | 6ae81775 | ths | }; |
72 | 6ae81775 | ths | |
73 | 6ae81775 | ths | static int mips_qemu_iomemtype = 0; |
74 | 6ae81775 | ths | |
75 | 6ae81775 | ths | void load_kernel (CPUState *env, int ram_size, const char *kernel_filename, |
76 | 6ae81775 | ths | const char *kernel_cmdline, |
77 | 6ae81775 | ths | const char *initrd_filename) |
78 | 6ae81775 | ths | { |
79 | 6ae81775 | ths | int64_t entry = 0;
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80 | 6ae81775 | ths | long kernel_size, initrd_size;
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81 | 6ae81775 | ths | |
82 | 6ae81775 | ths | kernel_size = load_elf(kernel_filename, VIRT_TO_PHYS_ADDEND, &entry); |
83 | c570fd16 | ths | if (kernel_size >= 0) { |
84 | c570fd16 | ths | if ((entry & ~0x7fffffffULL) == 0x80000000) |
85 | 5dc4b744 | ths | entry = (int32_t)entry; |
86 | 6ae81775 | ths | env->PC = entry; |
87 | c570fd16 | ths | } else {
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88 | 9042c0e2 | ths | fprintf(stderr, "qemu: could not load kernel '%s'\n",
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89 | 9042c0e2 | ths | kernel_filename); |
90 | 9042c0e2 | ths | exit(1);
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91 | 6ae81775 | ths | } |
92 | 6ae81775 | ths | |
93 | 6ae81775 | ths | /* load initrd */
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94 | 6ae81775 | ths | initrd_size = 0;
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95 | 6ae81775 | ths | if (initrd_filename) {
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96 | 6ae81775 | ths | initrd_size = load_image(initrd_filename, |
97 | 6ae81775 | ths | phys_ram_base + INITRD_LOAD_ADDR + VIRT_TO_PHYS_ADDEND); |
98 | 6ae81775 | ths | if (initrd_size == (target_ulong) -1) { |
99 | 6ae81775 | ths | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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100 | 6ae81775 | ths | initrd_filename); |
101 | 6ae81775 | ths | exit(1);
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102 | 6ae81775 | ths | } |
103 | 6ae81775 | ths | } |
104 | 6ae81775 | ths | |
105 | 6ae81775 | ths | /* Store command line. */
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106 | 6ae81775 | ths | if (initrd_size > 0) { |
107 | 6ae81775 | ths | int ret;
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108 | 6ae81775 | ths | ret = sprintf(phys_ram_base + (16 << 20) - 256, |
109 | c570fd16 | ths | "rd_start=0x" TLSZ " rd_size=%li ", |
110 | 6ae81775 | ths | INITRD_LOAD_ADDR, |
111 | 6ae81775 | ths | initrd_size); |
112 | 6ae81775 | ths | strcpy (phys_ram_base + (16 << 20) - 256 + ret, kernel_cmdline); |
113 | 6ae81775 | ths | } |
114 | 6ae81775 | ths | else {
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115 | 6ae81775 | ths | strcpy (phys_ram_base + (16 << 20) - 256, kernel_cmdline); |
116 | 6ae81775 | ths | } |
117 | 6ae81775 | ths | |
118 | 6ae81775 | ths | *(int *)(phys_ram_base + (16 << 20) - 260) = tswap32 (0x12345678); |
119 | 6ae81775 | ths | *(int *)(phys_ram_base + (16 << 20) - 264) = tswap32 (ram_size); |
120 | 6ae81775 | ths | } |
121 | 6ae81775 | ths | |
122 | 6ae81775 | ths | static void main_cpu_reset(void *opaque) |
123 | 6ae81775 | ths | { |
124 | 6ae81775 | ths | CPUState *env = opaque; |
125 | 6ae81775 | ths | cpu_reset(env); |
126 | 6ae81775 | ths | |
127 | 6ae81775 | ths | if (env->kernel_filename)
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128 | 6ae81775 | ths | load_kernel (env, env->ram_size, env->kernel_filename, |
129 | 6ae81775 | ths | env->kernel_cmdline, env->initrd_filename); |
130 | 6ae81775 | ths | } |
131 | 66a93e0f | bellard | |
132 | 6af0bf9c | bellard | void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device, |
133 | 6af0bf9c | bellard | DisplayState *ds, const char **fd_filename, int snapshot, |
134 | 6af0bf9c | bellard | const char *kernel_filename, const char *kernel_cmdline, |
135 | 6af0bf9c | bellard | const char *initrd_filename) |
136 | 6af0bf9c | bellard | { |
137 | 6af0bf9c | bellard | char buf[1024]; |
138 | 6af0bf9c | bellard | unsigned long bios_offset; |
139 | 6af0bf9c | bellard | int ret;
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140 | c68ea704 | bellard | CPUState *env; |
141 | afdfa781 | ths | static RTCState *rtc_state;
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142 | 58126404 | pbrook | int i;
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143 | c68ea704 | bellard | |
144 | c68ea704 | bellard | env = cpu_init(); |
145 | c68ea704 | bellard | register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); |
146 | 6ae81775 | ths | qemu_register_reset(main_cpu_reset, env); |
147 | c68ea704 | bellard | |
148 | 6af0bf9c | bellard | /* allocate RAM */
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149 | 6af0bf9c | bellard | cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
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150 | 66a93e0f | bellard | |
151 | 6ae81775 | ths | if (!mips_qemu_iomemtype) {
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152 | 6ae81775 | ths | mips_qemu_iomemtype = cpu_register_io_memory(0, mips_qemu_read,
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153 | 6ae81775 | ths | mips_qemu_write, NULL);
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154 | 6ae81775 | ths | } |
155 | 6ae81775 | ths | cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype); |
156 | 6ae81775 | ths | |
157 | 66a93e0f | bellard | /* Try to load a BIOS image. If this fails, we continue regardless,
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158 | 66a93e0f | bellard | but initialize the hardware ourselves. When a kernel gets
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159 | 66a93e0f | bellard | preloaded we also initialize the hardware, since the BIOS wasn't
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160 | 66a93e0f | bellard | run. */
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161 | 6af0bf9c | bellard | bios_offset = ram_size + vga_ram_size; |
162 | 6af0bf9c | bellard | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME); |
163 | 6af0bf9c | bellard | ret = load_image(buf, phys_ram_base + bios_offset); |
164 | 66a93e0f | bellard | if (ret == BIOS_SIZE) {
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165 | 66a93e0f | bellard | cpu_register_physical_memory((uint32_t)(0x1fc00000),
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166 | 66a93e0f | bellard | BIOS_SIZE, bios_offset | IO_MEM_ROM); |
167 | 66a93e0f | bellard | } else {
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168 | 66a93e0f | bellard | /* not fatal */
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169 | 66a93e0f | bellard | fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
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170 | 66a93e0f | bellard | buf); |
171 | 6af0bf9c | bellard | } |
172 | 66a93e0f | bellard | |
173 | 66a93e0f | bellard | if (kernel_filename) {
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174 | 6ae81775 | ths | load_kernel (env, ram_size, kernel_filename, kernel_cmdline, |
175 | 6ae81775 | ths | initrd_filename); |
176 | 6ae81775 | ths | env->ram_size = ram_size; |
177 | 6ae81775 | ths | env->kernel_filename = kernel_filename; |
178 | 6ae81775 | ths | env->kernel_cmdline = kernel_cmdline; |
179 | 6ae81775 | ths | env->initrd_filename = initrd_filename; |
180 | 6af0bf9c | bellard | } |
181 | 6af0bf9c | bellard | |
182 | e16fe40c | ths | /* Init CPU internal devices */
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183 | c68ea704 | bellard | cpu_mips_clock_init(env); |
184 | 6af0bf9c | bellard | cpu_mips_irqctrl_init(); |
185 | 6af0bf9c | bellard | |
186 | afdfa781 | ths | rtc_state = rtc_init(0x70, 8); |
187 | afdfa781 | ths | |
188 | 0699b548 | bellard | /* Register 64 KB of ISA IO space at 0x14000000 */
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189 | aef445bd | pbrook | isa_mmio_init(0x14000000, 0x00010000); |
190 | 0699b548 | bellard | isa_mem_base = 0x10000000;
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191 | 0699b548 | bellard | |
192 | c68ea704 | bellard | isa_pic = pic_init(pic_irq_request, env); |
193 | 697584ab | bellard | pit = pit_init(0x40, 0); |
194 | afdfa781 | ths | |
195 | eddbd288 | ths | for(i = 0; i < MAX_SERIAL_PORTS; i++) { |
196 | eddbd288 | ths | if (serial_hds[i]) {
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197 | eddbd288 | ths | serial_init(&pic_set_irq_new, isa_pic, |
198 | eddbd288 | ths | serial_io[i], serial_irq[i], serial_hds[i]); |
199 | eddbd288 | ths | } |
200 | eddbd288 | ths | } |
201 | eddbd288 | ths | |
202 | 89b6b508 | bellard | isa_vga_init(ds, phys_ram_base + ram_size, ram_size, |
203 | 89b6b508 | bellard | vga_ram_size); |
204 | 9827e95c | bellard | |
205 | a41b2ff2 | pbrook | if (nd_table[0].vlan) { |
206 | a41b2ff2 | pbrook | if (nd_table[0].model == NULL |
207 | a41b2ff2 | pbrook | || strcmp(nd_table[0].model, "ne2k_isa") == 0) { |
208 | a41b2ff2 | pbrook | isa_ne2000_init(0x300, 9, &nd_table[0]); |
209 | a41b2ff2 | pbrook | } else {
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210 | a41b2ff2 | pbrook | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
211 | a41b2ff2 | pbrook | exit (1);
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212 | a41b2ff2 | pbrook | } |
213 | a41b2ff2 | pbrook | } |
214 | 58126404 | pbrook | |
215 | 58126404 | pbrook | for(i = 0; i < 2; i++) |
216 | 58126404 | pbrook | isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i], |
217 | 58126404 | pbrook | bs_table[2 * i], bs_table[2 * i + 1]); |
218 | 6af0bf9c | bellard | } |
219 | 6af0bf9c | bellard | |
220 | 6af0bf9c | bellard | QEMUMachine mips_machine = { |
221 | 6af0bf9c | bellard | "mips",
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222 | 6af0bf9c | bellard | "mips r4k platform",
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223 | 6af0bf9c | bellard | mips_r4k_init, |
224 | 6af0bf9c | bellard | }; |