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1 | 2c0262af | bellard | /*
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2 | 2c0262af | bellard | * ARM virtual CPU header
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3 | 2c0262af | bellard | *
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4 | 2c0262af | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 2c0262af | bellard | *
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6 | 2c0262af | bellard | * This library is free software; you can redistribute it and/or
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7 | 2c0262af | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 2c0262af | bellard | * License as published by the Free Software Foundation; either
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9 | 2c0262af | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 2c0262af | bellard | *
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11 | 2c0262af | bellard | * This library is distributed in the hope that it will be useful,
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12 | 2c0262af | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 2c0262af | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 2c0262af | bellard | * Lesser General Public License for more details.
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15 | 2c0262af | bellard | *
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16 | 2c0262af | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 2c0262af | bellard | * License along with this library; if not, write to the Free Software
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18 | 2c0262af | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 2c0262af | bellard | */
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20 | 2c0262af | bellard | #ifndef CPU_ARM_H
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21 | 2c0262af | bellard | #define CPU_ARM_H
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22 | 2c0262af | bellard | |
23 | 3cf1e035 | bellard | #define TARGET_LONG_BITS 32 |
24 | 3cf1e035 | bellard | |
25 | 9042c0e2 | ths | #define ELF_MACHINE EM_ARM
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26 | 9042c0e2 | ths | |
27 | 2c0262af | bellard | #include "cpu-defs.h" |
28 | 2c0262af | bellard | |
29 | 53cd6637 | bellard | #include "softfloat.h" |
30 | 53cd6637 | bellard | |
31 | 1fddef4b | bellard | #define TARGET_HAS_ICE 1 |
32 | 1fddef4b | bellard | |
33 | b8a9e8f1 | bellard | #define EXCP_UDEF 1 /* undefined instruction */ |
34 | b8a9e8f1 | bellard | #define EXCP_SWI 2 /* software interrupt */ |
35 | b8a9e8f1 | bellard | #define EXCP_PREFETCH_ABORT 3 |
36 | b8a9e8f1 | bellard | #define EXCP_DATA_ABORT 4 |
37 | b5ff1b31 | bellard | #define EXCP_IRQ 5 |
38 | b5ff1b31 | bellard | #define EXCP_FIQ 6 |
39 | 06c949e6 | pbrook | #define EXCP_BKPT 7 |
40 | 2c0262af | bellard | |
41 | b7bcbe95 | bellard | /* We currently assume float and double are IEEE single and double
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42 | b7bcbe95 | bellard | precision respectively.
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43 | b7bcbe95 | bellard | Doing runtime conversions is tricky because VFP registers may contain
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44 | b7bcbe95 | bellard | integer values (eg. as the result of a FTOSI instruction).
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45 | 8e96005d | bellard | s<2n> maps to the least significant half of d<n>
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46 | 8e96005d | bellard | s<2n+1> maps to the most significant half of d<n>
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47 | 8e96005d | bellard | */
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48 | b7bcbe95 | bellard | |
49 | 2c0262af | bellard | typedef struct CPUARMState { |
50 | b5ff1b31 | bellard | /* Regs for current mode. */
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51 | 2c0262af | bellard | uint32_t regs[16];
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52 | b5ff1b31 | bellard | /* Frequently accessed CPSR bits are stored separately for efficiently.
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53 | d37aca66 | pbrook | This contains all the other bits. Use cpsr_{read,write} to access
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54 | b5ff1b31 | bellard | the whole CPSR. */
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55 | b5ff1b31 | bellard | uint32_t uncached_cpsr; |
56 | b5ff1b31 | bellard | uint32_t spsr; |
57 | b5ff1b31 | bellard | |
58 | b5ff1b31 | bellard | /* Banked registers. */
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59 | b5ff1b31 | bellard | uint32_t banked_spsr[6];
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60 | b5ff1b31 | bellard | uint32_t banked_r13[6];
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61 | b5ff1b31 | bellard | uint32_t banked_r14[6];
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62 | b5ff1b31 | bellard | |
63 | b5ff1b31 | bellard | /* These hold r8-r12. */
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64 | b5ff1b31 | bellard | uint32_t usr_regs[5];
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65 | b5ff1b31 | bellard | uint32_t fiq_regs[5];
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66 | 2c0262af | bellard | |
67 | 2c0262af | bellard | /* cpsr flag cache for faster execution */
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68 | 2c0262af | bellard | uint32_t CF; /* 0 or 1 */
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69 | 2c0262af | bellard | uint32_t VF; /* V is the bit 31. All other bits are undefined */
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70 | 2c0262af | bellard | uint32_t NZF; /* N is bit 31. Z is computed from NZF */
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71 | 99c475ab | bellard | uint32_t QF; /* 0 or 1 */
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72 | 99c475ab | bellard | |
73 | 99c475ab | bellard | int thumb; /* 0 = arm mode, 1 = thumb mode */ |
74 | 2c0262af | bellard | |
75 | b5ff1b31 | bellard | /* System control coprocessor (cp15) */
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76 | b5ff1b31 | bellard | struct {
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77 | 40f137e1 | pbrook | uint32_t c0_cpuid; |
78 | b5ff1b31 | bellard | uint32_t c1_sys; /* System control register. */
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79 | b5ff1b31 | bellard | uint32_t c1_coproc; /* Coprocessor access register. */
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80 | b5ff1b31 | bellard | uint32_t c2; /* MMU translation table base. */
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81 | b5ff1b31 | bellard | uint32_t c3; /* MMU domain access control register. */
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82 | b5ff1b31 | bellard | uint32_t c5_insn; /* Fault status registers. */
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83 | b5ff1b31 | bellard | uint32_t c5_data; |
84 | b5ff1b31 | bellard | uint32_t c6_insn; /* Fault address registers. */
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85 | b5ff1b31 | bellard | uint32_t c6_data; |
86 | b5ff1b31 | bellard | uint32_t c9_insn; /* Cache lockdown registers. */
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87 | b5ff1b31 | bellard | uint32_t c9_data; |
88 | b5ff1b31 | bellard | uint32_t c13_fcse; /* FCSE PID. */
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89 | b5ff1b31 | bellard | uint32_t c13_context; /* Context ID. */
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90 | b5ff1b31 | bellard | } cp15; |
91 | 40f137e1 | pbrook | |
92 | 40f137e1 | pbrook | /* Internal CPU feature flags. */
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93 | 40f137e1 | pbrook | uint32_t features; |
94 | 40f137e1 | pbrook | |
95 | 2c0262af | bellard | /* exception/interrupt handling */
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96 | 2c0262af | bellard | jmp_buf jmp_env; |
97 | 2c0262af | bellard | int exception_index;
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98 | 2c0262af | bellard | int interrupt_request;
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99 | 2c0262af | bellard | int user_mode_only;
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100 | 9332f9da | bellard | int halted;
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101 | 2c0262af | bellard | |
102 | b7bcbe95 | bellard | /* VFP coprocessor state. */
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103 | b7bcbe95 | bellard | struct {
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104 | 8e96005d | bellard | float64 regs[16];
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105 | b7bcbe95 | bellard | |
106 | 40f137e1 | pbrook | uint32_t xregs[16];
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107 | b7bcbe95 | bellard | /* We store these fpcsr fields separately for convenience. */
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108 | b7bcbe95 | bellard | int vec_len;
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109 | b7bcbe95 | bellard | int vec_stride;
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110 | b7bcbe95 | bellard | |
111 | b7bcbe95 | bellard | /* Temporary variables if we don't have spare fp regs. */
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112 | 53cd6637 | bellard | float32 tmp0s, tmp1s; |
113 | 53cd6637 | bellard | float64 tmp0d, tmp1d; |
114 | 53cd6637 | bellard | |
115 | 53cd6637 | bellard | float_status fp_status; |
116 | b7bcbe95 | bellard | } vfp; |
117 | b7bcbe95 | bellard | |
118 | ce4defa0 | pbrook | #if defined(CONFIG_USER_ONLY)
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119 | ce4defa0 | pbrook | /* For usermode syscall translation. */
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120 | ce4defa0 | pbrook | int eabi;
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121 | ce4defa0 | pbrook | #endif
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122 | ce4defa0 | pbrook | |
123 | a316d335 | bellard | CPU_COMMON |
124 | a316d335 | bellard | |
125 | 2c0262af | bellard | } CPUARMState; |
126 | 2c0262af | bellard | |
127 | 2c0262af | bellard | CPUARMState *cpu_arm_init(void);
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128 | 2c0262af | bellard | int cpu_arm_exec(CPUARMState *s);
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129 | 2c0262af | bellard | void cpu_arm_close(CPUARMState *s);
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130 | b5ff1b31 | bellard | void do_interrupt(CPUARMState *);
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131 | b5ff1b31 | bellard | void switch_mode(CPUARMState *, int); |
132 | b5ff1b31 | bellard | |
133 | 2c0262af | bellard | /* you can call this signal handler from your SIGBUS and SIGSEGV
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134 | 2c0262af | bellard | signal handlers to inform the virtual CPU of exceptions. non zero
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135 | 2c0262af | bellard | is returned if the signal was handled by the virtual CPU. */
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136 | 2c0262af | bellard | struct siginfo;
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137 | 2c0262af | bellard | int cpu_arm_signal_handler(int host_signum, struct siginfo *info, |
138 | 2c0262af | bellard | void *puc);
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139 | 2c0262af | bellard | |
140 | b5ff1b31 | bellard | #define CPSR_M (0x1f) |
141 | b5ff1b31 | bellard | #define CPSR_T (1 << 5) |
142 | b5ff1b31 | bellard | #define CPSR_F (1 << 6) |
143 | b5ff1b31 | bellard | #define CPSR_I (1 << 7) |
144 | b5ff1b31 | bellard | #define CPSR_A (1 << 8) |
145 | b5ff1b31 | bellard | #define CPSR_E (1 << 9) |
146 | b5ff1b31 | bellard | #define CPSR_IT_2_7 (0xfc00) |
147 | b5ff1b31 | bellard | /* Bits 20-23 reserved. */
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148 | b5ff1b31 | bellard | #define CPSR_J (1 << 24) |
149 | b5ff1b31 | bellard | #define CPSR_IT_0_1 (3 << 25) |
150 | b5ff1b31 | bellard | #define CPSR_Q (1 << 27) |
151 | b5ff1b31 | bellard | #define CPSR_NZCV (0xf << 28) |
152 | b5ff1b31 | bellard | |
153 | b5ff1b31 | bellard | #define CACHED_CPSR_BITS (CPSR_T | CPSR_Q | CPSR_NZCV)
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154 | b5ff1b31 | bellard | /* Return the current CPSR value. */
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155 | b5ff1b31 | bellard | static inline uint32_t cpsr_read(CPUARMState *env) |
156 | b5ff1b31 | bellard | { |
157 | b5ff1b31 | bellard | int ZF;
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158 | b5ff1b31 | bellard | ZF = (env->NZF == 0);
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159 | b5ff1b31 | bellard | return env->uncached_cpsr | (env->NZF & 0x80000000) | (ZF << 30) | |
160 | b5ff1b31 | bellard | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
161 | b5ff1b31 | bellard | | (env->thumb << 5);
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162 | b5ff1b31 | bellard | } |
163 | b5ff1b31 | bellard | |
164 | b5ff1b31 | bellard | /* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */
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165 | b5ff1b31 | bellard | static inline void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) |
166 | b5ff1b31 | bellard | { |
167 | b5ff1b31 | bellard | /* NOTE: N = 1 and Z = 1 cannot be stored currently */
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168 | b5ff1b31 | bellard | if (mask & CPSR_NZCV) {
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169 | b5ff1b31 | bellard | env->NZF = (val & 0xc0000000) ^ 0x40000000; |
170 | b5ff1b31 | bellard | env->CF = (val >> 29) & 1; |
171 | b5ff1b31 | bellard | env->VF = (val << 3) & 0x80000000; |
172 | b5ff1b31 | bellard | } |
173 | b5ff1b31 | bellard | if (mask & CPSR_Q)
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174 | b5ff1b31 | bellard | env->QF = ((val & CPSR_Q) != 0);
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175 | b5ff1b31 | bellard | if (mask & CPSR_T)
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176 | b5ff1b31 | bellard | env->thumb = ((val & CPSR_T) != 0);
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177 | b5ff1b31 | bellard | |
178 | b5ff1b31 | bellard | if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
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179 | b5ff1b31 | bellard | switch_mode(env, val & CPSR_M); |
180 | b5ff1b31 | bellard | } |
181 | b5ff1b31 | bellard | mask &= ~CACHED_CPSR_BITS; |
182 | b5ff1b31 | bellard | env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); |
183 | b5ff1b31 | bellard | } |
184 | b5ff1b31 | bellard | |
185 | b5ff1b31 | bellard | enum arm_cpu_mode {
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186 | b5ff1b31 | bellard | ARM_CPU_MODE_USR = 0x10,
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187 | b5ff1b31 | bellard | ARM_CPU_MODE_FIQ = 0x11,
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188 | b5ff1b31 | bellard | ARM_CPU_MODE_IRQ = 0x12,
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189 | b5ff1b31 | bellard | ARM_CPU_MODE_SVC = 0x13,
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190 | b5ff1b31 | bellard | ARM_CPU_MODE_ABT = 0x17,
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191 | b5ff1b31 | bellard | ARM_CPU_MODE_UND = 0x1b,
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192 | b5ff1b31 | bellard | ARM_CPU_MODE_SYS = 0x1f
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193 | b5ff1b31 | bellard | }; |
194 | b5ff1b31 | bellard | |
195 | 40f137e1 | pbrook | /* VFP system registers. */
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196 | 40f137e1 | pbrook | #define ARM_VFP_FPSID 0 |
197 | 40f137e1 | pbrook | #define ARM_VFP_FPSCR 1 |
198 | 40f137e1 | pbrook | #define ARM_VFP_FPEXC 8 |
199 | 40f137e1 | pbrook | #define ARM_VFP_FPINST 9 |
200 | 40f137e1 | pbrook | #define ARM_VFP_FPINST2 10 |
201 | 40f137e1 | pbrook | |
202 | 40f137e1 | pbrook | |
203 | 40f137e1 | pbrook | enum arm_features {
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204 | 40f137e1 | pbrook | ARM_FEATURE_VFP, |
205 | 40f137e1 | pbrook | ARM_FEATURE_AUXCR /* ARM1026 Auxiliary control register. */
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206 | 40f137e1 | pbrook | }; |
207 | 40f137e1 | pbrook | |
208 | 40f137e1 | pbrook | static inline int arm_feature(CPUARMState *env, int feature) |
209 | 40f137e1 | pbrook | { |
210 | 40f137e1 | pbrook | return (env->features & (1u << feature)) != 0; |
211 | 40f137e1 | pbrook | } |
212 | 40f137e1 | pbrook | |
213 | 40f137e1 | pbrook | void cpu_arm_set_model(CPUARMState *env, uint32_t id);
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214 | 40f137e1 | pbrook | |
215 | 40f137e1 | pbrook | #define ARM_CPUID_ARM1026 0x4106a262 |
216 | 40f137e1 | pbrook | #define ARM_CPUID_ARM926 0x41069265 |
217 | 40f137e1 | pbrook | |
218 | b5ff1b31 | bellard | #if defined(CONFIG_USER_ONLY)
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219 | 2c0262af | bellard | #define TARGET_PAGE_BITS 12 |
220 | b5ff1b31 | bellard | #else
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221 | b5ff1b31 | bellard | /* The ARM MMU allows 1k pages. */
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222 | b5ff1b31 | bellard | /* ??? Linux doesn't actually use these, and they're deprecated in recent
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223 | b5ff1b31 | bellard | architecture revisions. Maybe an a configure option to disable them. */
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224 | b5ff1b31 | bellard | #define TARGET_PAGE_BITS 10 |
225 | b5ff1b31 | bellard | #endif
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226 | 2c0262af | bellard | #include "cpu-all.h" |
227 | 2c0262af | bellard | |
228 | 2c0262af | bellard | #endif |