root / hw / mips_r4k.c @ 9042c0e2
History | View | Annotate | Download (6.5 kB)
1 |
/*
|
---|---|
2 |
* QEMU/MIPS pseudo-board
|
3 |
*
|
4 |
* emulates a simple machine with ISA-like bus.
|
5 |
* ISA IO space mapped to the 0x14000000 (PHYS) and
|
6 |
* ISA memory at the 0x10000000 (PHYS, 16Mb in size).
|
7 |
* All peripherial devices are attached to this "bus" with
|
8 |
* the standard PC ISA addresses.
|
9 |
*/
|
10 |
#include "vl.h" |
11 |
|
12 |
#define BIOS_FILENAME "mips_bios.bin" |
13 |
//#define BIOS_FILENAME "system.bin"
|
14 |
#ifdef MIPS_HAS_MIPS64
|
15 |
#define INITRD_LOAD_ADDR (int64_t)0x80800000 |
16 |
#else
|
17 |
#define INITRD_LOAD_ADDR (int32_t)0x80800000 |
18 |
#endif
|
19 |
|
20 |
#define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000)) |
21 |
|
22 |
static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
23 |
static const int ide_iobase2[2] = { 0x3f6, 0x376 }; |
24 |
static const int ide_irq[2] = { 14, 15 }; |
25 |
|
26 |
static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; |
27 |
static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; |
28 |
|
29 |
extern FILE *logfile;
|
30 |
|
31 |
static PITState *pit; /* PIT i8254 */ |
32 |
|
33 |
/*i8254 PIT is attached to the IRQ0 at PIC i8259 */
|
34 |
/*The PIC is attached to the MIPS CPU INT0 pin */
|
35 |
static void pic_irq_request(void *opaque, int level) |
36 |
{ |
37 |
CPUState *env = first_cpu; |
38 |
if (level) {
|
39 |
env->CP0_Cause |= 0x00000400;
|
40 |
cpu_interrupt(env, CPU_INTERRUPT_HARD); |
41 |
} else {
|
42 |
env->CP0_Cause &= ~0x00000400;
|
43 |
cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
44 |
} |
45 |
} |
46 |
|
47 |
static void mips_qemu_writel (void *opaque, target_phys_addr_t addr, |
48 |
uint32_t val) |
49 |
{ |
50 |
if ((addr & 0xffff) == 0 && val == 42) |
51 |
qemu_system_reset_request (); |
52 |
else if ((addr & 0xffff) == 4 && val == 42) |
53 |
qemu_system_shutdown_request (); |
54 |
} |
55 |
|
56 |
static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr) |
57 |
{ |
58 |
return 0; |
59 |
} |
60 |
|
61 |
static CPUWriteMemoryFunc *mips_qemu_write[] = {
|
62 |
&mips_qemu_writel, |
63 |
&mips_qemu_writel, |
64 |
&mips_qemu_writel, |
65 |
}; |
66 |
|
67 |
static CPUReadMemoryFunc *mips_qemu_read[] = {
|
68 |
&mips_qemu_readl, |
69 |
&mips_qemu_readl, |
70 |
&mips_qemu_readl, |
71 |
}; |
72 |
|
73 |
static int mips_qemu_iomemtype = 0; |
74 |
|
75 |
void load_kernel (CPUState *env, int ram_size, const char *kernel_filename, |
76 |
const char *kernel_cmdline, |
77 |
const char *initrd_filename) |
78 |
{ |
79 |
int64_t entry = 0;
|
80 |
long kernel_size, initrd_size;
|
81 |
|
82 |
kernel_size = load_elf(kernel_filename, VIRT_TO_PHYS_ADDEND, &entry); |
83 |
if (kernel_size >= 0) { |
84 |
if ((entry & ~0x7fffffffULL) == 0x80000000) |
85 |
entry = (int32_t)entry; |
86 |
env->PC = entry; |
87 |
} else {
|
88 |
fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
89 |
kernel_filename); |
90 |
exit(1);
|
91 |
} |
92 |
|
93 |
/* load initrd */
|
94 |
initrd_size = 0;
|
95 |
if (initrd_filename) {
|
96 |
initrd_size = load_image(initrd_filename, |
97 |
phys_ram_base + INITRD_LOAD_ADDR + VIRT_TO_PHYS_ADDEND); |
98 |
if (initrd_size == (target_ulong) -1) { |
99 |
fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
100 |
initrd_filename); |
101 |
exit(1);
|
102 |
} |
103 |
} |
104 |
|
105 |
/* Store command line. */
|
106 |
if (initrd_size > 0) { |
107 |
int ret;
|
108 |
ret = sprintf(phys_ram_base + (16 << 20) - 256, |
109 |
"rd_start=0x" TLSZ " rd_size=%li ", |
110 |
INITRD_LOAD_ADDR, |
111 |
initrd_size); |
112 |
strcpy (phys_ram_base + (16 << 20) - 256 + ret, kernel_cmdline); |
113 |
} |
114 |
else {
|
115 |
strcpy (phys_ram_base + (16 << 20) - 256, kernel_cmdline); |
116 |
} |
117 |
|
118 |
*(int *)(phys_ram_base + (16 << 20) - 260) = tswap32 (0x12345678); |
119 |
*(int *)(phys_ram_base + (16 << 20) - 264) = tswap32 (ram_size); |
120 |
} |
121 |
|
122 |
static void main_cpu_reset(void *opaque) |
123 |
{ |
124 |
CPUState *env = opaque; |
125 |
cpu_reset(env); |
126 |
|
127 |
if (env->kernel_filename)
|
128 |
load_kernel (env, env->ram_size, env->kernel_filename, |
129 |
env->kernel_cmdline, env->initrd_filename); |
130 |
} |
131 |
|
132 |
void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device, |
133 |
DisplayState *ds, const char **fd_filename, int snapshot, |
134 |
const char *kernel_filename, const char *kernel_cmdline, |
135 |
const char *initrd_filename) |
136 |
{ |
137 |
char buf[1024]; |
138 |
unsigned long bios_offset; |
139 |
int ret;
|
140 |
CPUState *env; |
141 |
static RTCState *rtc_state;
|
142 |
int i;
|
143 |
|
144 |
env = cpu_init(); |
145 |
register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); |
146 |
qemu_register_reset(main_cpu_reset, env); |
147 |
|
148 |
/* allocate RAM */
|
149 |
cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
|
150 |
|
151 |
if (!mips_qemu_iomemtype) {
|
152 |
mips_qemu_iomemtype = cpu_register_io_memory(0, mips_qemu_read,
|
153 |
mips_qemu_write, NULL);
|
154 |
} |
155 |
cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype); |
156 |
|
157 |
/* Try to load a BIOS image. If this fails, we continue regardless,
|
158 |
but initialize the hardware ourselves. When a kernel gets
|
159 |
preloaded we also initialize the hardware, since the BIOS wasn't
|
160 |
run. */
|
161 |
bios_offset = ram_size + vga_ram_size; |
162 |
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME); |
163 |
ret = load_image(buf, phys_ram_base + bios_offset); |
164 |
if (ret == BIOS_SIZE) {
|
165 |
cpu_register_physical_memory((uint32_t)(0x1fc00000),
|
166 |
BIOS_SIZE, bios_offset | IO_MEM_ROM); |
167 |
} else {
|
168 |
/* not fatal */
|
169 |
fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
|
170 |
buf); |
171 |
} |
172 |
|
173 |
if (kernel_filename) {
|
174 |
load_kernel (env, ram_size, kernel_filename, kernel_cmdline, |
175 |
initrd_filename); |
176 |
env->ram_size = ram_size; |
177 |
env->kernel_filename = kernel_filename; |
178 |
env->kernel_cmdline = kernel_cmdline; |
179 |
env->initrd_filename = initrd_filename; |
180 |
} |
181 |
|
182 |
/* Init CPU internal devices */
|
183 |
cpu_mips_clock_init(env); |
184 |
cpu_mips_irqctrl_init(); |
185 |
|
186 |
rtc_state = rtc_init(0x70, 8); |
187 |
|
188 |
/* Register 64 KB of ISA IO space at 0x14000000 */
|
189 |
isa_mmio_init(0x14000000, 0x00010000); |
190 |
isa_mem_base = 0x10000000;
|
191 |
|
192 |
isa_pic = pic_init(pic_irq_request, env); |
193 |
pit = pit_init(0x40, 0); |
194 |
|
195 |
for(i = 0; i < MAX_SERIAL_PORTS; i++) { |
196 |
if (serial_hds[i]) {
|
197 |
serial_init(&pic_set_irq_new, isa_pic, |
198 |
serial_io[i], serial_irq[i], serial_hds[i]); |
199 |
} |
200 |
} |
201 |
|
202 |
isa_vga_init(ds, phys_ram_base + ram_size, ram_size, |
203 |
vga_ram_size); |
204 |
|
205 |
if (nd_table[0].vlan) { |
206 |
if (nd_table[0].model == NULL |
207 |
|| strcmp(nd_table[0].model, "ne2k_isa") == 0) { |
208 |
isa_ne2000_init(0x300, 9, &nd_table[0]); |
209 |
} else {
|
210 |
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
211 |
exit (1);
|
212 |
} |
213 |
} |
214 |
|
215 |
for(i = 0; i < 2; i++) |
216 |
isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i], |
217 |
bs_table[2 * i], bs_table[2 * i + 1]); |
218 |
} |
219 |
|
220 |
QEMUMachine mips_machine = { |
221 |
"mips",
|
222 |
"mips r4k platform",
|
223 |
mips_r4k_init, |
224 |
}; |