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/*
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 *  PowerPC emulation cpu definitions for qemu.
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 * 
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 *  Copyright (c) 2003-2005 Jocelyn Mayer
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#if !defined (__CPU_PPC_H__)
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#define __CPU_PPC_H__
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#include "config.h"
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#define TARGET_LONG_BITS 32
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#include "cpu-defs.h"
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#include <setjmp.h>
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#include "softfloat.h"
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#define TARGET_HAS_ICE 1
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#define ELF_MACHINE        EM_PPC
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/* XXX: this should be tunable: PowerPC 601 & 64 bits PowerPC
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 *                              have different cache line sizes
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 */
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#define ICACHE_LINE_SIZE 32
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#define DCACHE_LINE_SIZE 32
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/* XXX: put this in a common place */
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#define likely(x)   __builtin_expect(!!(x), 1)
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/*****************************************************************************/
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/* PVR definitions for most known PowerPC */
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enum {
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    /* PowerPC 401 cores */
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    CPU_PPC_401A1     = 0x00210000,
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    CPU_PPC_401B2     = 0x00220000,
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    CPU_PPC_401C2     = 0x00230000,
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    CPU_PPC_401D2     = 0x00240000,
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    CPU_PPC_401E2     = 0x00250000,
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    CPU_PPC_401F2     = 0x00260000,
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    CPU_PPC_401G2     = 0x00270000,
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    CPU_PPC_IOP480    = 0x40100000,
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    /* PowerPC 403 cores */
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    CPU_PPC_403GA     = 0x00200000,
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    CPU_PPC_403GB     = 0x00200100,
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    CPU_PPC_403GC     = 0x00200200,
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    CPU_PPC_403GCX    = 0x00201400,
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    /* PowerPC 405 cores */
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    CPU_PPC_405       = 0x40110000,
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    CPU_PPC_405EP     = 0x51210000,
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    CPU_PPC_405GPR    = 0x50910000,
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    CPU_PPC_405D2     = 0x20010000,
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    CPU_PPC_405D4     = 0x41810000,
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    CPU_PPC_NPE405H   = 0x41410000,
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    CPU_PPC_NPE405L   = 0x41610000,
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#if 0
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    CPU_PPC_STB02     = xxx,
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#endif
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    CPU_PPC_STB03     = 0x40310000,
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#if 0
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    CPU_PPC_STB04     = xxx,
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#endif
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    CPU_PPC_STB25     = 0x51510000,
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#if 0
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    CPU_PPC_STB130    = xxx,
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#endif
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    /* PowerPC 440 cores */
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    CPU_PPC_440EP     = 0x42220000,
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    CPU_PPC_440GP     = 0x40120400,
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    CPU_PPC_440GX     = 0x51B20000,
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    /* PowerPC MPC 8xx cores */
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    CPU_PPC_8540      = 0x80200000,
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    CPU_PPC_8xx       = 0x00500000,
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    CPU_PPC_8240      = 0x00810100,
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    CPU_PPC_8245      = 0x00811014,
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    /* PowerPC 6xx cores */
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    CPU_PPC_601       = 0x00010000,
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    CPU_PPC_602       = 0x00050000,
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    CPU_PPC_603       = 0x00030000,
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    CPU_PPC_603E      = 0x00060000,
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    CPU_PPC_603EV     = 0x00070000,
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    CPU_PPC_603R      = 0x00071000,
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    CPU_PPC_G2        = 0x80810000,
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    CPU_PPC_G2LE      = 0x80820000,
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    CPU_PPC_604       = 0x00040000,
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    CPU_PPC_604E      = 0x00090000,
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    CPU_PPC_604R      = 0x000a0000,
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    /* PowerPC 74x/75x cores (aka G3) */
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    CPU_PPC_74x       = 0x00080000,
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    CPU_PPC_755       = 0x00083000,
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    CPU_PPC_74xP      = 0x10080000,
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    CPU_PPC_750CXE22  = 0x00082202,
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    CPU_PPC_750CXE24  = 0x00082214,
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    CPU_PPC_750CXE24b = 0x00083214,
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    CPU_PPC_750CXE31  = 0x00083211,
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    CPU_PPC_750CXE31b = 0x00083311,
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#define CPU_PPC_750CXE CPU_PPC_750CXE31b
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    CPU_PPC_750FX     = 0x70000000,
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    CPU_PPC_750GX     = 0x70020000,
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    /* PowerPC 74xx cores (aka G4) */
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    CPU_PPC_7400      = 0x000C0000,
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    CPU_PPC_7410      = 0x800C0000,
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    CPU_PPC_7441      = 0x80000200,
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    CPU_PPC_7450      = 0x80000000,
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    CPU_PPC_7451      = 0x80000203,
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    CPU_PPC_7455      = 0x80010000,
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    CPU_PPC_7457      = 0x80020000,
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    CPU_PPC_7457A     = 0x80030000,
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    /* 64 bits PowerPC */
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    CPU_PPC_620       = 0x00140000,
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    CPU_PPC_630       = 0x00400000,
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    CPU_PPC_631       = 0x00410000,
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    CPU_PPC_POWER4    = 0x00350000,
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    CPU_PPC_POWER4P   = 0x00380000,
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    CPU_PPC_POWER5    = 0x003A0000,
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    CPU_PPC_POWER5P   = 0x003B0000,
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    CPU_PPC_970       = 0x00390000,
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    CPU_PPC_970FX     = 0x003C0000,
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    CPU_PPC_RS64      = 0x00330000,
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    CPU_PPC_RS64II    = 0x00340000,
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    CPU_PPC_RS64III   = 0x00360000,
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    CPU_PPC_RS64IV    = 0x00370000,
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    /* Original POWER */
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    /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
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     * POWER2 (RIOS2) & RSC2 (P2SC) here
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     */
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#if 0
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    CPU_POWER         = xxx,
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#endif
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#if 0
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    CPU_POWER2        = xxx,
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#endif
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};
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/* System version register (used on MPC 8xx) */
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enum {
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    PPC_SVR_8540      = 0x80300000,
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    PPC_SVR_8541E     = 0x807A0000,
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    PPC_SVR_8555E     = 0x80790000,
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    PPC_SVR_8560      = 0x80700000,
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};
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/*****************************************************************************/
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/* Instruction types */
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enum {
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    PPC_NONE        = 0x00000000,
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    /* integer operations instructions             */
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    /* flow control instructions                   */
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    /* virtual memory instructions                 */
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    /* ld/st with reservation instructions         */
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    /* cache control instructions                  */
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    /* spr/msr access instructions                 */
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    PPC_INSNS_BASE  = 0x00000001,
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#define PPC_INTEGER PPC_INSNS_BASE
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#define PPC_FLOW    PPC_INSNS_BASE
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#define PPC_MEM     PPC_INSNS_BASE
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#define PPC_RES     PPC_INSNS_BASE
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#define PPC_CACHE   PPC_INSNS_BASE
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#define PPC_MISC    PPC_INSNS_BASE
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    /* floating point operations instructions      */
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    PPC_FLOAT       = 0x00000002,
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    /* more floating point operations instructions */
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    PPC_FLOAT_EXT   = 0x00000004,
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    /* external control instructions               */
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    PPC_EXTERN      = 0x00000008,
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    /* segment register access instructions        */
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    PPC_SEGMENT     = 0x00000010,
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    /* Optional cache control instructions         */
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    PPC_CACHE_OPT   = 0x00000020,
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    /* Optional floating point op instructions     */
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    PPC_FLOAT_OPT   = 0x00000040,
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    /* Optional memory control instructions        */
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    PPC_MEM_TLBIA   = 0x00000080,
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    PPC_MEM_TLBIE   = 0x00000100,
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    PPC_MEM_TLBSYNC = 0x00000200,
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    /* eieio & sync                                */
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    PPC_MEM_SYNC    = 0x00000400,
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    /* PowerPC 6xx TLB management instructions     */
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    PPC_6xx_TLB     = 0x00000800,
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    /* Altivec support                             */
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    PPC_ALTIVEC     = 0x00001000,
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    /* Time base support                           */
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    PPC_TB          = 0x00002000,
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    /* Embedded PowerPC dedicated instructions     */
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    PPC_4xx_COMMON  = 0x00004000,
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    /* PowerPC 40x exception model                 */
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    PPC_40x_EXCP    = 0x00008000,
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    /* PowerPC 40x specific instructions           */
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    PPC_40x_SPEC    = 0x00010000,
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    /* PowerPC 405 Mac instructions                */
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    PPC_405_MAC     = 0x00020000,
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    /* PowerPC 440 specific instructions           */
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    PPC_440_SPEC    = 0x00040000,
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    /* Specific extensions */
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    /* Power-to-PowerPC bridge (601)               */
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    PPC_POWER_BR    = 0x00080000,
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    /* PowerPC 602 specific */
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    PPC_602_SPEC    = 0x00100000,
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    /* Deprecated instructions                     */
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    /* Original POWER instruction set              */
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    PPC_POWER       = 0x00200000,
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    /* POWER2 instruction set extension            */
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    PPC_POWER2      = 0x00400000,
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    /* Power RTC support */
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    PPC_POWER_RTC   = 0x00800000,
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    /* 64 bits PowerPC instructions                */
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    /* 64 bits PowerPC instruction set             */
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    PPC_64B         = 0x01000000,
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    /* 64 bits hypervisor extensions               */
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    PPC_64H         = 0x02000000,
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    /* 64 bits PowerPC "bridge" features           */
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    PPC_64_BRIDGE   = 0x04000000,
228
};
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/* CPU run-time flags (MMU and exception model) */
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enum {
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    /* MMU model */
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#define PPC_FLAGS_MMU_MASK (0x0000000F)
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    /* Standard 32 bits PowerPC MMU */
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    PPC_FLAGS_MMU_32B      = 0x00000000,
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    /* Standard 64 bits PowerPC MMU */
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    PPC_FLAGS_MMU_64B      = 0x00000001,
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    /* PowerPC 601 MMU */
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    PPC_FLAGS_MMU_601      = 0x00000002,
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    /* PowerPC 6xx MMU with software TLB */
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    PPC_FLAGS_MMU_SOFT_6xx = 0x00000003,
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    /* PowerPC 4xx MMU with software TLB */
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    PPC_FLAGS_MMU_SOFT_4xx = 0x00000004,
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    /* PowerPC 403 MMU */
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    PPC_FLAGS_MMU_403      = 0x00000005,
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    /* Exception model */
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#define PPC_FLAGS_EXCP_MASK (0x000000F0)
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    /* Standard PowerPC exception model */
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    PPC_FLAGS_EXCP_STD     = 0x00000000,
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    /* PowerPC 40x exception model */
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    PPC_FLAGS_EXCP_40x     = 0x00000010,
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    /* PowerPC 601 exception model */
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    PPC_FLAGS_EXCP_601     = 0x00000020,
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    /* PowerPC 602 exception model */
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    PPC_FLAGS_EXCP_602     = 0x00000030,
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    /* PowerPC 603 exception model */
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    PPC_FLAGS_EXCP_603     = 0x00000040,
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    /* PowerPC 604 exception model */
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    PPC_FLAGS_EXCP_604     = 0x00000050,
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    /* PowerPC 7x0 exception model */
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    PPC_FLAGS_EXCP_7x0     = 0x00000060,
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    /* PowerPC 7x5 exception model */
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    PPC_FLAGS_EXCP_7x5     = 0x00000070,
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    /* PowerPC 74xx exception model */
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    PPC_FLAGS_EXCP_74xx    = 0x00000080,
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    /* PowerPC 970 exception model */
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    PPC_FLAGS_EXCP_970     = 0x00000090,
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};
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#define PPC_MMU(env) (env->flags & PPC_FLAGS_MMU_MASK)
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#define PPC_EXCP(env) (env->flags & PPC_FLAGS_EXCP_MASK)
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/*****************************************************************************/
274
/* Supported instruction set definitions */
275
/* This generates an empty opcode table... */
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#define PPC_INSNS_TODO (PPC_NONE)
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#define PPC_FLAGS_TODO (0x00000000)
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/* PowerPC 40x instruction set */
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#define PPC_INSNS_4xx (PPC_INSNS_BASE | PPC_MEM_TLBSYNC | PPC_4xx_COMMON)
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/* PowerPC 401 */
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#define PPC_INSNS_401 (PPC_INSNS_TODO)
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#define PPC_FLAGS_401 (PPC_FLAGS_TODO)
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/* PowerPC 403 */
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#define PPC_INSNS_403 (PPC_INSNS_4xx | PPC_MEM_SYNC | PPC_MEM_TLBIA |         \
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                       PPC_40x_EXCP | PPC_40x_SPEC)
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#define PPC_FLAGS_403 (PPC_FLAGS_MMU_403 | PPC_FLAGS_EXCP_40x)
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/* PowerPC 405 */
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#define PPC_INSNS_405 (PPC_INSNS_4xx | PPC_MEM_SYNC | PPC_CACHE_OPT |         \
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                       PPC_MEM_TLBIA | PPC_TB | PPC_40x_SPEC | PPC_40x_EXCP | \
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                       PPC_405_MAC)
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#define PPC_FLAGS_405 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x)
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/* PowerPC 440 */
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#define PPC_INSNS_440 (PPC_INSNS_4xx | PPC_CACHE_OPT | PPC_405_MAC |          \
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                       PPC_440_SPEC)
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#define PPC_FLAGS_440 (PPC_FLAGS_TODO)
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/* Non-embedded PowerPC */
298
#define PPC_INSNS_COMMON  (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC |        \
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                           PPC_SEGMENT | PPC_MEM_TLBIE)
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/* PowerPC 601 */
301
#define PPC_INSNS_601 (PPC_INSNS_COMMON | PPC_EXTERN | PPC_POWER_BR)
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#define PPC_FLAGS_601 (PPC_FLAGS_MMU_601 | PPC_FLAGS_EXCP_601)
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/* PowerPC 602 */
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#define PPC_INSNS_602 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB |       \
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                       PPC_MEM_TLBSYNC | PPC_TB)
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#define PPC_FLAGS_602 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_602)
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/* PowerPC 603 */
308
#define PPC_INSNS_603 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB |       \
309
                       PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB)
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#define PPC_FLAGS_603 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603)
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/* PowerPC G2 */
312
#define PPC_INSNS_G2 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB |        \
313
                      PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB)
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#define PPC_FLAGS_G2 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603)
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/* PowerPC 604 */
316
#define PPC_INSNS_604 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN |        \
317
                       PPC_MEM_TLBSYNC | PPC_TB)
318
#define PPC_FLAGS_604 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_604)
319
/* PowerPC 740/750 (aka G3) */
320
#define PPC_INSNS_7x0 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN |        \
321
                       PPC_MEM_TLBSYNC | PPC_TB)
322
#define PPC_FLAGS_7x0 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_7x0)
323
/* PowerPC 745/755 */
324
#define PPC_INSNS_7x5 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN |        \
325
                       PPC_MEM_TLBSYNC | PPC_TB | PPC_6xx_TLB)
326
#define PPC_FLAGS_7x5 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_7x5)
327
/* PowerPC 74xx (aka G4) */
328
#define PPC_INSNS_74xx (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_ALTIVEC |      \
329
                        PPC_MEM_TLBSYNC | PPC_TB)
330
#define PPC_FLAGS_74xx (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_74xx)
331

    
332
/* Default PowerPC will be 604/970 */
333
#define PPC_INSNS_PPC32 PPC_INSNS_604
334
#define PPC_FLAGS_PPC32 PPC_FLAGS_604
335
#if 0
336
#define PPC_INSNS_PPC64 PPC_INSNS_970
337
#define PPC_FLAGS_PPC64 PPC_FLAGS_970
338
#endif
339
#define PPC_INSNS_DEFAULT PPC_INSNS_604
340
#define PPC_FLAGS_DEFAULT PPC_FLAGS_604
341
typedef struct ppc_def_t ppc_def_t;
342

    
343
/*****************************************************************************/
344
/* Types used to describe some PowerPC registers */
345
typedef struct CPUPPCState CPUPPCState;
346
typedef struct opc_handler_t opc_handler_t;
347
typedef struct ppc_tb_t ppc_tb_t;
348
typedef struct ppc_spr_t ppc_spr_t;
349
typedef struct ppc_dcr_t ppc_dcr_t;
350
typedef struct ppc_avr_t ppc_avr_t;
351

    
352
/* SPR access micro-ops generations callbacks */
353
struct ppc_spr_t {
354
    void (*uea_read)(void *opaque, int spr_num);
355
    void (*uea_write)(void *opaque, int spr_num);
356
    void (*oea_read)(void *opaque, int spr_num);
357
    void (*oea_write)(void *opaque, int spr_num);
358
    const unsigned char *name;
359
};
360

    
361
/* Altivec registers (128 bits) */
362
struct ppc_avr_t {
363
    uint32_t u[4];
364
};
365

    
366
/* Software TLB cache */
367
typedef struct ppc_tlb_t ppc_tlb_t;
368
struct ppc_tlb_t {
369
    /* Physical page number */
370
    target_phys_addr_t RPN;
371
    /* Virtual page number */
372
    target_ulong VPN;
373
    /* Page size */
374
    target_ulong size;
375
    /* Protection bits */
376
    int prot;
377
    int is_user;
378
    uint32_t private;
379
    uint32_t flags;
380
};
381

    
382
/*****************************************************************************/
383
/* Machine state register bits definition                                    */
384
#define MSR_SF   63 /* Sixty-four-bit mode                                   */
385
#define MSR_ISF  61 /* Sixty-four-bit interrupt mode on 630                  */
386
#define MSR_HV   60 /* hypervisor state                                      */
387
#define MSR_VR   25 /* altivec available                                     */
388
#define MSR_AP   23 /* Access privilege state on 602                         */
389
#define MSR_SA   22 /* Supervisor access mode on 602                         */
390
#define MSR_KEY  19 /* key bit on 603e                                       */
391
#define MSR_POW  18 /* Power management                                      */
392
#define MSR_WE   18 /* Wait state enable on embedded PowerPC                 */
393
#define MSR_TGPR 17 /* TGPR usage on 602/603                                 */
394
#define MSR_TLB  17 /* TLB on ?                                              */
395
#define MSR_CE   17 /* Critical interrupt enable on embedded PowerPC         */
396
#define MSR_ILE  16 /* Interrupt little-endian mode                          */
397
#define MSR_EE   15 /* External interrupt enable                             */
398
#define MSR_PR   14 /* Problem state                                         */
399
#define MSR_FP   13 /* Floating point available                              */
400
#define MSR_ME   12 /* Machine check interrupt enable                        */
401
#define MSR_FE0  11 /* Floating point exception mode 0                       */
402
#define MSR_SE   10 /* Single-step trace enable                              */
403
#define MSR_DWE  10 /* Debug wait enable on 405                              */
404
#define MSR_BE   9  /* Branch trace enable                                   */
405
#define MSR_DE   9  /* Debug interrupts enable on embedded PowerPC           */
406
#define MSR_FE1  8  /* Floating point exception mode 1                       */
407
#define MSR_AL   7  /* AL bit on POWER                                       */
408
#define MSR_IP   6  /* Interrupt prefix                                      */
409
#define MSR_IR   5  /* Instruction relocate                                  */
410
#define MSR_IS   5  /* Instruction address space on embedded PowerPC         */
411
#define MSR_DR   4  /* Data relocate                                         */
412
#define MSR_DS   4  /* Data address space on embedded PowerPC                */
413
#define MSR_PE   3  /* Protection enable on 403                              */
414
#define MSR_EP   3  /* Exception prefix on 601                               */
415
#define MSR_PX   2  /* Protection exclusive on 403                           */
416
#define MSR_PMM  2  /* Performance monitor mark on POWER                     */
417
#define MSR_RI   1  /* Recoverable interrupt                                 */
418
#define MSR_LE   0  /* Little-endian mode                                    */
419
#define msr_sf   env->msr[MSR_SF]
420
#define msr_isf  env->msr[MSR_ISF]
421
#define msr_hv   env->msr[MSR_HV]
422
#define msr_vr   env->msr[MSR_VR]
423
#define msr_ap   env->msr[MSR_AP]
424
#define msr_sa   env->msr[MSR_SA]
425
#define msr_key  env->msr[MSR_KEY]
426
#define msr_pow env->msr[MSR_POW]
427
#define msr_we   env->msr[MSR_WE]
428
#define msr_tgpr env->msr[MSR_TGPR]
429
#define msr_tlb  env->msr[MSR_TLB]
430
#define msr_ce   env->msr[MSR_CE]
431
#define msr_ile env->msr[MSR_ILE]
432
#define msr_ee  env->msr[MSR_EE]
433
#define msr_pr  env->msr[MSR_PR]
434
#define msr_fp  env->msr[MSR_FP]
435
#define msr_me  env->msr[MSR_ME]
436
#define msr_fe0 env->msr[MSR_FE0]
437
#define msr_se  env->msr[MSR_SE]
438
#define msr_dwe  env->msr[MSR_DWE]
439
#define msr_be  env->msr[MSR_BE]
440
#define msr_de   env->msr[MSR_DE]
441
#define msr_fe1 env->msr[MSR_FE1]
442
#define msr_al   env->msr[MSR_AL]
443
#define msr_ip  env->msr[MSR_IP]
444
#define msr_ir  env->msr[MSR_IR]
445
#define msr_is   env->msr[MSR_IS]
446
#define msr_dr  env->msr[MSR_DR]
447
#define msr_ds   env->msr[MSR_DS]
448
#define msr_pe   env->msr[MSR_PE]
449
#define msr_ep   env->msr[MSR_EP]
450
#define msr_px   env->msr[MSR_PX]
451
#define msr_pmm  env->msr[MSR_PMM]
452
#define msr_ri  env->msr[MSR_RI]
453
#define msr_le  env->msr[MSR_LE]
454

    
455
/*****************************************************************************/
456
/* The whole PowerPC CPU context */
457
struct CPUPPCState {
458
    /* First are the most commonly used resources
459
     * during translated code execution
460
     */
461
#if TARGET_LONG_BITS > HOST_LONG_BITS
462
    /* temporary fixed-point registers
463
     * used to emulate 64 bits target on 32 bits hosts
464
     */
465
    target_ulong t0, t1, t2;
466
#endif
467
    /* general purpose registers */
468
    target_ulong gpr[32];
469
    /* LR */
470
    target_ulong lr;
471
    /* CTR */
472
    target_ulong ctr;
473
    /* condition register */
474
    uint8_t crf[8];
475
    /* XER */
476
    /* XXX: We use only 5 fields, but we want to keep the structure aligned */
477
    uint8_t xer[8];
478
    /* Reservation address */
479
    target_ulong reserve;
480

    
481
    /* Those ones are used in supervisor mode only */
482
    /* machine state register */
483
    uint8_t msr[64];
484
    /* temporary general purpose registers */
485
    target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
486

    
487
    /* Floating point execution context */
488
     /* temporary float registers */
489
    float64 ft0;
490
    float64 ft1;
491
    float64 ft2;
492
    float_status fp_status;
493
    /* floating point registers */
494
    float64 fpr[32];
495
    /* floating point status and control register */
496
    uint8_t fpscr[8];
497

    
498
    CPU_COMMON
499

    
500
    int halted; /* TRUE if the CPU is in suspend state */
501

    
502
    int access_type; /* when a memory exception occurs, the access
503
                        type is stored here */
504

    
505
    /* MMU context */
506
    /* Address space register */
507
    target_ulong asr;
508
    /* segment registers */
509
    target_ulong sdr1;
510
    target_ulong sr[16];
511
    /* BATs */
512
    int nb_BATs;
513
    target_ulong DBAT[2][8];
514
    target_ulong IBAT[2][8];
515

    
516
    /* Other registers */
517
    /* Special purpose registers */
518
    target_ulong spr[1024];
519
    /* Altivec registers */
520
    ppc_avr_t avr[32];
521
    uint32_t vscr;
522

    
523
    /* Internal devices resources */
524
    /* Time base and decrementer */
525
    ppc_tb_t *tb_env;
526
    /* Device control registers */
527
    int (*dcr_read)(ppc_dcr_t *dcr_env, int dcr_num, target_ulong *val);
528
    int (*dcr_write)(ppc_dcr_t *dcr_env, int dcr_num, target_ulong val);
529
    ppc_dcr_t *dcr_env;
530

    
531
    /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
532
    int nb_tlb;
533
    int nb_ways, last_way;
534
    ppc_tlb_t tlb[128];
535
    /* Callbacks for specific checks on some implementations */
536
    int (*tlb_check_more)(CPUPPCState *env, struct ppc_tlb_t *tlb, int *prot,
537
                          target_ulong vaddr, int rw, int acc_type,
538
                          int is_user);
539
    /* 403 dedicated access protection registers */
540
    target_ulong pb[4];
541

    
542
    /* Those resources are used during exception processing */
543
    /* CPU model definition */
544
    uint64_t msr_mask;
545
    uint32_t flags;
546

    
547
    int exception_index;
548
    int error_code;
549
    int interrupt_request;
550

    
551
    /* Those resources are used only during code translation */
552
    /* Next instruction pointer */
553
    target_ulong nip;
554
    /* SPR translation callbacks */
555
    ppc_spr_t spr_cb[1024];
556
    /* opcode handlers */
557
    opc_handler_t *opcodes[0x40];
558

    
559
    /* Those resources are used only in Qemu core */
560
    jmp_buf jmp_env;
561
    int user_mode_only; /* user mode only simulation */
562
    uint32_t hflags;
563

    
564
    /* Power management */
565
    int power_mode;
566

    
567
    /* temporary hack to handle OSI calls (only used if non NULL) */
568
    int (*osi_call)(struct CPUPPCState *env);
569
};
570

    
571
/*****************************************************************************/
572
CPUPPCState *cpu_ppc_init(void);
573
int cpu_ppc_exec(CPUPPCState *s);
574
void cpu_ppc_close(CPUPPCState *s);
575
/* you can call this signal handler from your SIGBUS and SIGSEGV
576
   signal handlers to inform the virtual CPU of exceptions. non zero
577
   is returned if the signal was handled by the virtual CPU.  */
578
struct siginfo;
579
int cpu_ppc_signal_handler(int host_signum, struct siginfo *info, 
580
                           void *puc);
581

    
582
void do_interrupt (CPUPPCState *env);
583
void cpu_loop_exit(void);
584

    
585
void dump_stack (CPUPPCState *env);
586

    
587
target_ulong do_load_ibatu (CPUPPCState *env, int nr);
588
target_ulong do_load_ibatl (CPUPPCState *env, int nr);
589
void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
590
void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value);
591
target_ulong do_load_dbatu (CPUPPCState *env, int nr);
592
target_ulong do_load_dbatl (CPUPPCState *env, int nr);
593
void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
594
void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
595

    
596
target_ulong do_load_nip (CPUPPCState *env);
597
void do_store_nip (CPUPPCState *env, target_ulong value);
598
target_ulong do_load_sdr1 (CPUPPCState *env);
599
void do_store_sdr1 (CPUPPCState *env, target_ulong value);
600
target_ulong do_load_asr (CPUPPCState *env);
601
void do_store_asr (CPUPPCState *env, target_ulong value);
602
target_ulong do_load_sr (CPUPPCState *env, int srnum);
603
void do_store_sr (CPUPPCState *env, int srnum, target_ulong value);
604
uint32_t do_load_cr (CPUPPCState *env);
605
void do_store_cr (CPUPPCState *env, uint32_t value, uint32_t mask);
606
uint32_t do_load_xer (CPUPPCState *env);
607
void do_store_xer (CPUPPCState *env, uint32_t value);
608
target_ulong do_load_msr (CPUPPCState *env);
609
void do_store_msr (CPUPPCState *env, target_ulong value);
610
float64 do_load_fpscr (CPUPPCState *env);
611
void do_store_fpscr (CPUPPCState *env, float64 f, uint32_t mask);
612

    
613
void do_compute_hflags (CPUPPCState *env);
614

    
615
int ppc_find_by_name (const unsigned char *name, ppc_def_t **def);
616
int ppc_find_by_pvr (uint32_t apvr, ppc_def_t **def);
617
void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
618
int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def);
619

    
620
/* Time-base and decrementer management */
621
#ifndef NO_CPU_IO_DEFS
622
uint32_t cpu_ppc_load_tbl (CPUPPCState *env);
623
uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
624
void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
625
void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
626
uint32_t cpu_ppc_load_decr (CPUPPCState *env);
627
void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
628
#endif
629

    
630
#define TARGET_PAGE_BITS 12
631
#include "cpu-all.h"
632

    
633
/*****************************************************************************/
634
/* Registers definitions */
635
#define ugpr(n) (env->gpr[n])
636

    
637
#define XER_SO 31
638
#define XER_OV 30
639
#define XER_CA 29
640
#define XER_CMP 8
641
#define XER_BC 0
642
#define xer_so  env->xer[4]
643
#define xer_ov  env->xer[6]
644
#define xer_ca  env->xer[2]
645
#define xer_cmp env->xer[1]
646
#define xer_bc env->xer[0]
647

    
648
/* SPR definitions */
649
#define SPR_MQ         (0x000)
650
#define SPR_XER        (0x001)
651
#define SPR_601_VRTCU  (0x004)
652
#define SPR_601_VRTCL  (0x005)
653
#define SPR_601_UDECR  (0x006)
654
#define SPR_LR         (0x008)
655
#define SPR_CTR        (0x009)
656
#define SPR_DSISR      (0x012)
657
#define SPR_DAR        (0x013)
658
#define SPR_601_RTCU   (0x014)
659
#define SPR_601_RTCL   (0x015)
660
#define SPR_DECR       (0x016)
661
#define SPR_SDR1       (0x019)
662
#define SPR_SRR0       (0x01A)
663
#define SPR_SRR1       (0x01B)
664
#define SPR_440_PID    (0x030)
665
#define SPR_440_DECAR  (0x036)
666
#define SPR_CSRR0      (0x03A)
667
#define SPR_CSRR1      (0x03B)
668
#define SPR_440_DEAR   (0x03D)
669
#define SPR_440_ESR    (0x03E)
670
#define SPR_440_IVPR   (0x03F)
671
#define SPR_8xx_EIE    (0x050)
672
#define SPR_8xx_EID    (0x051)
673
#define SPR_8xx_NRE    (0x052)
674
#define SPR_58x_CMPA   (0x090)
675
#define SPR_58x_CMPB   (0x091)
676
#define SPR_58x_CMPC   (0x092)
677
#define SPR_58x_CMPD   (0x093)
678
#define SPR_58x_ICR    (0x094)
679
#define SPR_58x_DER    (0x094)
680
#define SPR_58x_COUNTA (0x096)
681
#define SPR_58x_COUNTB (0x097)
682
#define SPR_58x_CMPE   (0x098)
683
#define SPR_58x_CMPF   (0x099)
684
#define SPR_58x_CMPG   (0x09A)
685
#define SPR_58x_CMPH   (0x09B)
686
#define SPR_58x_LCTRL1 (0x09C)
687
#define SPR_58x_LCTRL2 (0x09D)
688
#define SPR_58x_ICTRL  (0x09E)
689
#define SPR_58x_BAR    (0x09F)
690
#define SPR_VRSAVE     (0x100)
691
#define SPR_USPRG0     (0x100)
692
#define SPR_USPRG4     (0x104)
693
#define SPR_USPRG5     (0x105)
694
#define SPR_USPRG6     (0x106)
695
#define SPR_USPRG7     (0x107)
696
#define SPR_VTBL       (0x10C)
697
#define SPR_VTBU       (0x10D)
698
#define SPR_SPRG0      (0x110)
699
#define SPR_SPRG1      (0x111)
700
#define SPR_SPRG2      (0x112)
701
#define SPR_SPRG3      (0x113)
702
#define SPR_SPRG4      (0x114)
703
#define SPR_SCOMC      (0x114)
704
#define SPR_SPRG5      (0x115)
705
#define SPR_SCOMD      (0x115)
706
#define SPR_SPRG6      (0x116)
707
#define SPR_SPRG7      (0x117)
708
#define SPR_ASR        (0x118)
709
#define SPR_EAR        (0x11A)
710
#define SPR_TBL        (0x11C)
711
#define SPR_TBU        (0x11D)
712
#define SPR_SVR        (0x11E)
713
#define SPR_440_PIR    (0x11E)
714
#define SPR_PVR        (0x11F)
715
#define SPR_HSPRG0     (0x130)
716
#define SPR_440_DBSR   (0x130)
717
#define SPR_HSPRG1     (0x131)
718
#define SPR_440_DBCR0  (0x134)
719
#define SPR_IBCR       (0x135)
720
#define SPR_440_DBCR1  (0x135)
721
#define SPR_DBCR       (0x136)
722
#define SPR_HDEC       (0x136)
723
#define SPR_440_DBCR2  (0x136)
724
#define SPR_HIOR       (0x137)
725
#define SPR_MBAR       (0x137)
726
#define SPR_RMOR       (0x138)
727
#define SPR_440_IAC1   (0x138)
728
#define SPR_HRMOR      (0x139)
729
#define SPR_440_IAC2   (0x139)
730
#define SPR_HSSR0      (0x13A)
731
#define SPR_440_IAC3   (0x13A)
732
#define SPR_HSSR1      (0x13B)
733
#define SPR_440_IAC4   (0x13B)
734
#define SPR_LPCR       (0x13C)
735
#define SPR_440_DAC1   (0x13C)
736
#define SPR_LPIDR      (0x13D)
737
#define SPR_DABR2      (0x13D)
738
#define SPR_440_DAC2   (0x13D)
739
#define SPR_440_DVC1   (0x13E)
740
#define SPR_440_DVC2   (0x13F)
741
#define SPR_440_TSR    (0x150)
742
#define SPR_440_TCR    (0x154)
743
#define SPR_440_IVOR0  (0x190)
744
#define SPR_440_IVOR1  (0x191)
745
#define SPR_440_IVOR2  (0x192)
746
#define SPR_440_IVOR3  (0x193)
747
#define SPR_440_IVOR4  (0x194)
748
#define SPR_440_IVOR5  (0x195)
749
#define SPR_440_IVOR6  (0x196)
750
#define SPR_440_IVOR7  (0x197)
751
#define SPR_440_IVOR8  (0x198)
752
#define SPR_440_IVOR9  (0x199)
753
#define SPR_440_IVOR10 (0x19A)
754
#define SPR_440_IVOR11 (0x19B)
755
#define SPR_440_IVOR12 (0x19C)
756
#define SPR_440_IVOR13 (0x19D)
757
#define SPR_440_IVOR14 (0x19E)
758
#define SPR_440_IVOR15 (0x19F)
759
#define SPR_IBAT0U     (0x210)
760
#define SPR_IBAT0L     (0x211)
761
#define SPR_IBAT1U     (0x212)
762
#define SPR_IBAT1L     (0x213)
763
#define SPR_IBAT2U     (0x214)
764
#define SPR_IBAT2L     (0x215)
765
#define SPR_IBAT3U     (0x216)
766
#define SPR_IBAT3L     (0x217)
767
#define SPR_DBAT0U     (0x218)
768
#define SPR_DBAT0L     (0x219)
769
#define SPR_DBAT1U     (0x21A)
770
#define SPR_DBAT1L     (0x21B)
771
#define SPR_DBAT2U     (0x21C)
772
#define SPR_DBAT2L     (0x21D)
773
#define SPR_DBAT3U     (0x21E)
774
#define SPR_DBAT3L     (0x21F)
775
#define SPR_IBAT4U     (0x230)
776
#define SPR_IBAT4L     (0x231)
777
#define SPR_IBAT5U     (0x232)
778
#define SPR_IBAT5L     (0x233)
779
#define SPR_IBAT6U     (0x234)
780
#define SPR_IBAT6L     (0x235)
781
#define SPR_IBAT7U     (0x236)
782
#define SPR_IBAT7L     (0x237)
783
#define SPR_DBAT4U     (0x238)
784
#define SPR_DBAT4L     (0x239)
785
#define SPR_DBAT5U     (0x23A)
786
#define SPR_DBAT5L     (0x23B)
787
#define SPR_DBAT6U     (0x23C)
788
#define SPR_DBAT6L     (0x23D)
789
#define SPR_DBAT7U     (0x23E)
790
#define SPR_DBAT7L     (0x23F)
791
#define SPR_440_INV0   (0x370)
792
#define SPR_440_INV1   (0x371)
793
#define SPR_440_INV2   (0x372)
794
#define SPR_440_INV3   (0x373)
795
#define SPR_440_IVT0   (0x374)
796
#define SPR_440_IVT1   (0x375)
797
#define SPR_440_IVT2   (0x376)
798
#define SPR_440_IVT3   (0x377)
799
#define SPR_440_DNV0   (0x390)
800
#define SPR_440_DNV1   (0x391)
801
#define SPR_440_DNV2   (0x392)
802
#define SPR_440_DNV3   (0x393)
803
#define SPR_440_DVT0   (0x394)
804
#define SPR_440_DVT1   (0x395)
805
#define SPR_440_DVT2   (0x396)
806
#define SPR_440_DVT3   (0x397)
807
#define SPR_440_DVLIM  (0x398)
808
#define SPR_440_IVLIM  (0x399)
809
#define SPR_440_RSTCFG (0x39B)
810
#define SPR_440_DCBTRL (0x39C)
811
#define SPR_440_DCBTRH (0x39D)
812
#define SPR_440_ICBTRL (0x39E)
813
#define SPR_440_ICBTRH (0x39F)
814
#define SPR_UMMCR0     (0x3A8)
815
#define SPR_UPMC1      (0x3A9)
816
#define SPR_UPMC2      (0x3AA)
817
#define SPR_USIA       (0x3AB)
818
#define SPR_UMMCR1     (0x3AC)
819
#define SPR_UPMC3      (0x3AD)
820
#define SPR_UPMC4      (0x3AE)
821
#define SPR_USDA       (0x3AF)
822
#define SPR_40x_ZPR    (0x3B0)
823
#define SPR_40x_PID    (0x3B1)
824
#define SPR_440_MMUCR  (0x3B2)
825
#define SPR_4xx_CCR0   (0x3B3)
826
#define SPR_405_IAC3   (0x3B4)
827
#define SPR_405_IAC4   (0x3B5)
828
#define SPR_405_DVC1   (0x3B6)
829
#define SPR_405_DVC2   (0x3B7)
830
#define SPR_MMCR0      (0x3B8)
831
#define SPR_PMC1       (0x3B9)
832
#define SPR_40x_SGR    (0x3B9)
833
#define SPR_PMC2       (0x3BA)
834
#define SPR_40x_DCWR   (0x3BA)
835
#define SPR_SIA        (0x3BB)
836
#define SPR_405_SLER   (0x3BB)
837
#define SPR_MMCR1      (0x3BC)
838
#define SPR_405_SU0R   (0x3BC)
839
#define SPR_PMC3       (0x3BD)
840
#define SPR_405_DBCR1  (0x3BD)
841
#define SPR_PMC4       (0x3BE)
842
#define SPR_SDA        (0x3BF)
843
#define SPR_403_VTBL   (0x3CC)
844
#define SPR_403_VTBU   (0x3CD)
845
#define SPR_DMISS      (0x3D0)
846
#define SPR_DCMP       (0x3D1)
847
#define SPR_DHASH1     (0x3D2)
848
#define SPR_DHASH2     (0x3D3)
849
#define SPR_4xx_ICDBDR (0x3D3)
850
#define SPR_IMISS      (0x3D4)
851
#define SPR_40x_ESR    (0x3D4)
852
#define SPR_ICMP       (0x3D5)
853
#define SPR_40x_DEAR   (0x3D5)
854
#define SPR_RPA        (0x3D6)
855
#define SPR_40x_EVPR   (0x3D6)
856
#define SPR_403_CDBCR  (0x3D7)
857
#define SPR_TCR        (0x3D8)
858
#define SPR_40x_TSR    (0x3D8)
859
#define SPR_IBR        (0x3DA)
860
#define SPR_40x_TCR    (0x3DA)
861
#define SPR_ESASR      (0x3DB)
862
#define SPR_40x_PIT    (0x3DB)
863
#define SPR_403_TBL    (0x3DC)
864
#define SPR_403_TBU    (0x3DD)
865
#define SPR_SEBR       (0x3DE)
866
#define SPR_40x_SRR2   (0x3DE)
867
#define SPR_SER        (0x3DF)
868
#define SPR_40x_SRR3   (0x3DF)
869
#define SPR_HID0       (0x3F0)
870
#define SPR_40x_DBSR   (0x3F0)
871
#define SPR_HID1       (0x3F1)
872
#define SPR_IABR       (0x3F2)
873
#define SPR_40x_DBCR0  (0x3F2)
874
#define SPR_601_HID2   (0x3F2)
875
#define SPR_HID2       (0x3F3)
876
#define SPR_440_DBDR   (0x3F3)
877
#define SPR_40x_IAC1   (0x3F4)
878
#define SPR_DABR       (0x3F5)
879
#define DABR_MASK (~(target_ulong)0x7)
880
#define SPR_40x_IAC2   (0x3F5)
881
#define SPR_601_HID5   (0x3F5)
882
#define SPR_40x_DAC1   (0x3F6)
883
#define SPR_40x_DAC2   (0x3F7)
884
#define SPR_L2PM       (0x3F8)
885
#define SPR_750_HID2   (0x3F8)
886
#define SPR_L2CR       (0x3F9)
887
#define SPR_IABR2      (0x3FA)
888
#define SPR_40x_DCCR   (0x3FA)
889
#define SPR_ICTC       (0x3FB)
890
#define SPR_40x_ICCR   (0x3FB)
891
#define SPR_THRM1      (0x3FC)
892
#define SPR_403_PBL1   (0x3FC)
893
#define SPR_SP         (0x3FD)
894
#define SPR_THRM2      (0x3FD)
895
#define SPR_403_PBU1   (0x3FD)
896
#define SPR_LT         (0x3FE)
897
#define SPR_THRM3      (0x3FE)
898
#define SPR_FPECR      (0x3FE)
899
#define SPR_403_PBL2   (0x3FE)
900
#define SPR_PIR        (0x3FF)
901
#define SPR_403_PBU2   (0x3FF)
902
#define SPR_601_HID15  (0x3FF)
903

    
904
/* Memory access type :
905
 * may be needed for precise access rights control and precise exceptions.
906
 */
907
enum {
908
    /* 1 bit to define user level / supervisor access */
909
    ACCESS_USER  = 0x00,
910
    ACCESS_SUPER = 0x01,
911
    /* Type of instruction that generated the access */
912
    ACCESS_CODE  = 0x10, /* Code fetch access                */
913
    ACCESS_INT   = 0x20, /* Integer load/store access        */
914
    ACCESS_FLOAT = 0x30, /* floating point load/store access */
915
    ACCESS_RES   = 0x40, /* load/store with reservation      */
916
    ACCESS_EXT   = 0x50, /* external access                  */
917
    ACCESS_CACHE = 0x60, /* Cache manipulation               */
918
};
919

    
920
/*****************************************************************************/
921
/* Exceptions */
922
#define EXCP_NONE          -1
923
/* PowerPC hardware exceptions : exception vectors defined in PowerPC book 3 */
924
#define EXCP_RESET         0x0100 /* System reset                            */
925
#define EXCP_MACHINE_CHECK 0x0200 /* Machine check exception                 */
926
#define EXCP_DSI           0x0300 /* Data storage exception                  */
927
#define EXCP_DSEG          0x0380 /* Data segment exception                  */
928
#define EXCP_ISI           0x0400 /* Instruction storage exception           */
929
#define EXCP_ISEG          0x0480 /* Instruction segment exception           */
930
#define EXCP_EXTERNAL      0x0500 /* External interruption                   */
931
#define EXCP_ALIGN         0x0600 /* Alignment exception                     */
932
#define EXCP_PROGRAM       0x0700 /* Program exception                       */
933
#define EXCP_NO_FP         0x0800 /* Floating point unavailable exception    */
934
#define EXCP_DECR          0x0900 /* Decrementer exception                   */
935
#define EXCP_HDECR         0x0980 /* Hypervisor decrementer exception        */
936
#define EXCP_SYSCALL       0x0C00 /* System call                             */
937
#define EXCP_TRACE         0x0D00 /* Trace exception                         */
938
#define EXCP_PERF          0x0F00 /* Performance monitor exception           */
939
/* Exceptions defined in PowerPC 32 bits programming environment manual      */
940
#define EXCP_FP_ASSIST     0x0E00 /* Floating-point assist                   */
941
/* Implementation specific exceptions                                        */
942
/* 40x exceptions                                                            */
943
#define EXCP_40x_PIT       0x1000 /* Programmable interval timer interrupt   */
944
#define EXCP_40x_FIT       0x1010 /* Fixed interval timer interrupt          */
945
#define EXCP_40x_WATCHDOG  0x1020 /* Watchdog timer exception                */
946
#define EXCP_40x_DTLBMISS  0x1100 /* Data TLB miss exception                 */
947
#define EXCP_40x_ITLBMISS  0x1200 /* Instruction TLB miss exception          */
948
#define EXCP_40x_DEBUG     0x2000 /* Debug exception                         */
949
/* 405 specific exceptions                                                   */
950
#define EXCP_405_APU       0x0F20 /* APU unavailable exception               */
951
/* TLB assist exceptions (602/603)                                           */
952
#define EXCP_I_TLBMISS     0x1000 /* Instruction TLB miss                    */
953
#define EXCP_DL_TLBMISS    0x1100 /* Data load TLB miss                      */
954
#define EXCP_DS_TLBMISS    0x1200 /* Data store TLB miss                     */
955
/* Breakpoint exceptions (602/603/604/620/740/745/750/755...)                */
956
#define EXCP_IABR          0x1300 /* Instruction address breakpoint          */
957
#define EXCP_SMI           0x1400 /* System management interrupt             */
958
/* Altivec related exceptions                                                */
959
#define EXCP_VPU           0x0F20 /* VPU unavailable exception               */
960
/* 601 specific exceptions                                                   */
961
#define EXCP_601_IO        0x0600 /* IO error exception                      */
962
#define EXCP_601_RUNM      0x2000 /* Run mode exception                      */
963
/* 602 specific exceptions                                                   */
964
#define EXCP_602_WATCHDOG  0x1500 /* Watchdog exception                      */
965
#define EXCP_602_EMUL      0x1600 /* Emulation trap exception                */
966
/* G2 specific exceptions                                                    */
967
#define EXCP_G2_CRIT       0x0A00 /* Critical interrupt                      */
968
/* MPC740/745/750 & IBM 750 specific exceptions                              */
969
#define EXCP_THRM          0x1700 /* Thermal management interrupt            */
970
/* 74xx specific exceptions                                                  */
971
#define EXCP_74xx_VPUA     0x1600 /* VPU assist exception                    */
972
/* 970FX specific exceptions                                                 */
973
#define EXCP_970_SOFTP     0x1500 /* Soft patch exception                    */
974
#define EXCP_970_MAINT     0x1600 /* Maintenance exception                   */
975
#define EXCP_970_THRM      0x1800 /* Thermal exception                       */
976
#define EXCP_970_VPUA      0x1700 /* VPU assist exception                    */
977
/* End of exception vectors area                                             */
978
#define EXCP_PPC_MAX       0x4000
979
/* Qemu exceptions: special cases we want to stop translation                */
980
#define EXCP_MTMSR         0x11000 /* mtmsr instruction:                     */
981
                                /* may change privilege level       */
982
#define EXCP_BRANCH        0x11001 /* branch instruction                     */
983
#define EXCP_SYSCALL_USER  0x12000 /* System call in user mode only          */
984
#define EXCP_INTERRUPT_CRITICAL 0x13000 /* critical IRQ                      */
985

    
986
/* Error codes */
987
enum {
988
    /* Exception subtypes for EXCP_ALIGN                            */
989
    EXCP_ALIGN_FP      = 0x01,  /* FP alignment exception           */
990
    EXCP_ALIGN_LST     = 0x02,  /* Unaligned mult/extern load/store */
991
    EXCP_ALIGN_LE      = 0x03,  /* Multiple little-endian access    */
992
    EXCP_ALIGN_PROT    = 0x04,  /* Access cross protection boundary */
993
    EXCP_ALIGN_BAT     = 0x05,  /* Access cross a BAT/seg boundary  */
994
    EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access           */
995
    /* Exception subtypes for EXCP_PROGRAM                          */
996
    /* FP exceptions */
997
    EXCP_FP            = 0x10,
998
    EXCP_FP_OX         = 0x01,  /* FP overflow                      */
999
    EXCP_FP_UX         = 0x02,  /* FP underflow                     */
1000
    EXCP_FP_ZX         = 0x03,  /* FP divide by zero                */
1001
    EXCP_FP_XX         = 0x04,  /* FP inexact                       */
1002
    EXCP_FP_VXNAN      = 0x05,  /* FP invalid SNaN op               */
1003
    EXCP_FP_VXISI      = 0x06,  /* FP invalid infinite substraction */
1004
    EXCP_FP_VXIDI      = 0x07,  /* FP invalid infinite divide       */
1005
    EXCP_FP_VXZDZ      = 0x08,  /* FP invalid zero divide           */
1006
    EXCP_FP_VXIMZ      = 0x09,  /* FP invalid infinite * zero       */
1007
    EXCP_FP_VXVC       = 0x0A,  /* FP invalid compare               */
1008
    EXCP_FP_VXSOFT     = 0x0B,  /* FP invalid operation             */
1009
    EXCP_FP_VXSQRT     = 0x0C,  /* FP invalid square root           */
1010
    EXCP_FP_VXCVI      = 0x0D,  /* FP invalid integer conversion    */
1011
    /* Invalid instruction */
1012
    EXCP_INVAL         = 0x20,
1013
    EXCP_INVAL_INVAL   = 0x01,  /* Invalid instruction              */
1014
    EXCP_INVAL_LSWX    = 0x02,  /* Invalid lswx instruction         */
1015
    EXCP_INVAL_SPR     = 0x03,  /* Invalid SPR access               */
1016
    EXCP_INVAL_FP      = 0x04,  /* Unimplemented mandatory fp instr */
1017
    /* Privileged instruction */
1018
    EXCP_PRIV          = 0x30,
1019
    EXCP_PRIV_OPC      = 0x01,
1020
    EXCP_PRIV_REG      = 0x02,
1021
    /* Trap */
1022
    EXCP_TRAP          = 0x40,
1023
};
1024

    
1025
/*****************************************************************************/
1026

    
1027
#endif /* !defined (__CPU_PPC_H__) */