Revision 90e189ec hw/ppc405_uc.c
b/hw/ppc405_uc.c | ||
---|---|---|
267 | 267 |
uint32_t ret; |
268 | 268 |
|
269 | 269 |
#ifdef DEBUG_OPBA |
270 |
printf("%s: addr " PADDRX "\n", __func__, addr);
|
|
270 |
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
|
|
271 | 271 |
#endif |
272 | 272 |
opba = opaque; |
273 | 273 |
switch (addr) { |
... | ... | |
291 | 291 |
ppc4xx_opba_t *opba; |
292 | 292 |
|
293 | 293 |
#ifdef DEBUG_OPBA |
294 |
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
|
294 |
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
|
295 |
value); |
|
295 | 296 |
#endif |
296 | 297 |
opba = opaque; |
297 | 298 |
switch (addr) { |
... | ... | |
311 | 312 |
uint32_t ret; |
312 | 313 |
|
313 | 314 |
#ifdef DEBUG_OPBA |
314 |
printf("%s: addr " PADDRX "\n", __func__, addr);
|
|
315 |
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
|
|
315 | 316 |
#endif |
316 | 317 |
ret = opba_readb(opaque, addr) << 8; |
317 | 318 |
ret |= opba_readb(opaque, addr + 1); |
... | ... | |
323 | 324 |
target_phys_addr_t addr, uint32_t value) |
324 | 325 |
{ |
325 | 326 |
#ifdef DEBUG_OPBA |
326 |
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
|
327 |
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
|
328 |
value); |
|
327 | 329 |
#endif |
328 | 330 |
opba_writeb(opaque, addr, value >> 8); |
329 | 331 |
opba_writeb(opaque, addr + 1, value); |
... | ... | |
334 | 336 |
uint32_t ret; |
335 | 337 |
|
336 | 338 |
#ifdef DEBUG_OPBA |
337 |
printf("%s: addr " PADDRX "\n", __func__, addr);
|
|
339 |
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
|
|
338 | 340 |
#endif |
339 | 341 |
ret = opba_readb(opaque, addr) << 24; |
340 | 342 |
ret |= opba_readb(opaque, addr + 1) << 16; |
... | ... | |
346 | 348 |
target_phys_addr_t addr, uint32_t value) |
347 | 349 |
{ |
348 | 350 |
#ifdef DEBUG_OPBA |
349 |
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
|
351 |
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
|
352 |
value); |
|
350 | 353 |
#endif |
351 | 354 |
opba_writeb(opaque, addr, value >> 24); |
352 | 355 |
opba_writeb(opaque, addr + 1, value >> 16); |
... | ... | |
380 | 383 |
|
381 | 384 |
opba = qemu_mallocz(sizeof(ppc4xx_opba_t)); |
382 | 385 |
#ifdef DEBUG_OPBA |
383 |
printf("%s: offset " PADDRX "\n", __func__, base);
|
|
386 |
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
|
|
384 | 387 |
#endif |
385 | 388 |
io = cpu_register_io_memory(opba_read, opba_write, opba); |
386 | 389 |
cpu_register_physical_memory(base, 0x002, io); |
... | ... | |
744 | 747 |
|
745 | 748 |
gpio = opaque; |
746 | 749 |
#ifdef DEBUG_GPIO |
747 |
printf("%s: addr " PADDRX "\n", __func__, addr);
|
|
750 |
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
|
|
748 | 751 |
#endif |
749 | 752 |
|
750 | 753 |
return 0; |
... | ... | |
757 | 760 |
|
758 | 761 |
gpio = opaque; |
759 | 762 |
#ifdef DEBUG_GPIO |
760 |
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
|
763 |
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
|
764 |
value); |
|
761 | 765 |
#endif |
762 | 766 |
} |
763 | 767 |
|
... | ... | |
767 | 771 |
|
768 | 772 |
gpio = opaque; |
769 | 773 |
#ifdef DEBUG_GPIO |
770 |
printf("%s: addr " PADDRX "\n", __func__, addr);
|
|
774 |
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
|
|
771 | 775 |
#endif |
772 | 776 |
|
773 | 777 |
return 0; |
... | ... | |
780 | 784 |
|
781 | 785 |
gpio = opaque; |
782 | 786 |
#ifdef DEBUG_GPIO |
783 |
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
|
787 |
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
|
788 |
value); |
|
784 | 789 |
#endif |
785 | 790 |
} |
786 | 791 |
|
... | ... | |
790 | 795 |
|
791 | 796 |
gpio = opaque; |
792 | 797 |
#ifdef DEBUG_GPIO |
793 |
printf("%s: addr " PADDRX "\n", __func__, addr);
|
|
798 |
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
|
|
794 | 799 |
#endif |
795 | 800 |
|
796 | 801 |
return 0; |
... | ... | |
803 | 808 |
|
804 | 809 |
gpio = opaque; |
805 | 810 |
#ifdef DEBUG_GPIO |
806 |
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
|
811 |
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
|
812 |
value); |
|
807 | 813 |
#endif |
808 | 814 |
} |
809 | 815 |
|
... | ... | |
833 | 839 |
|
834 | 840 |
gpio = qemu_mallocz(sizeof(ppc405_gpio_t)); |
835 | 841 |
#ifdef DEBUG_GPIO |
836 |
printf("%s: offset " PADDRX "\n", __func__, base);
|
|
842 |
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
|
|
837 | 843 |
#endif |
838 | 844 |
io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio); |
839 | 845 |
cpu_register_physical_memory(base, 0x038, io); |
... | ... | |
1035 | 1041 |
uint32_t ret; |
1036 | 1042 |
|
1037 | 1043 |
#ifdef DEBUG_I2C |
1038 |
printf("%s: addr " PADDRX "\n", __func__, addr);
|
|
1044 |
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
|
|
1039 | 1045 |
#endif |
1040 | 1046 |
i2c = opaque; |
1041 | 1047 |
switch (addr) { |
... | ... | |
1090 | 1096 |
break; |
1091 | 1097 |
} |
1092 | 1098 |
#ifdef DEBUG_I2C |
1093 |
printf("%s: addr " PADDRX " %02" PRIx32 "\n", __func__, addr, ret);
|
|
1099 |
printf("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__, addr, ret);
|
|
1094 | 1100 |
#endif |
1095 | 1101 |
|
1096 | 1102 |
return ret; |
... | ... | |
1102 | 1108 |
ppc4xx_i2c_t *i2c; |
1103 | 1109 |
|
1104 | 1110 |
#ifdef DEBUG_I2C |
1105 |
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
|
1111 |
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
|
1112 |
value); |
|
1106 | 1113 |
#endif |
1107 | 1114 |
i2c = opaque; |
1108 | 1115 |
switch (addr) { |
... | ... | |
1160 | 1167 |
uint32_t ret; |
1161 | 1168 |
|
1162 | 1169 |
#ifdef DEBUG_I2C |
1163 |
printf("%s: addr " PADDRX "\n", __func__, addr);
|
|
1170 |
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
|
|
1164 | 1171 |
#endif |
1165 | 1172 |
ret = ppc4xx_i2c_readb(opaque, addr) << 8; |
1166 | 1173 |
ret |= ppc4xx_i2c_readb(opaque, addr + 1); |
... | ... | |
1172 | 1179 |
target_phys_addr_t addr, uint32_t value) |
1173 | 1180 |
{ |
1174 | 1181 |
#ifdef DEBUG_I2C |
1175 |
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
|
1182 |
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
|
1183 |
value); |
|
1176 | 1184 |
#endif |
1177 | 1185 |
ppc4xx_i2c_writeb(opaque, addr, value >> 8); |
1178 | 1186 |
ppc4xx_i2c_writeb(opaque, addr + 1, value); |
... | ... | |
1183 | 1191 |
uint32_t ret; |
1184 | 1192 |
|
1185 | 1193 |
#ifdef DEBUG_I2C |
1186 |
printf("%s: addr " PADDRX "\n", __func__, addr);
|
|
1194 |
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
|
|
1187 | 1195 |
#endif |
1188 | 1196 |
ret = ppc4xx_i2c_readb(opaque, addr) << 24; |
1189 | 1197 |
ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16; |
... | ... | |
1197 | 1205 |
target_phys_addr_t addr, uint32_t value) |
1198 | 1206 |
{ |
1199 | 1207 |
#ifdef DEBUG_I2C |
1200 |
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
|
1208 |
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
|
1209 |
value); |
|
1201 | 1210 |
#endif |
1202 | 1211 |
ppc4xx_i2c_writeb(opaque, addr, value >> 24); |
1203 | 1212 |
ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16); |
... | ... | |
1241 | 1250 |
i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t)); |
1242 | 1251 |
i2c->irq = irq; |
1243 | 1252 |
#ifdef DEBUG_I2C |
1244 |
printf("%s: offset " PADDRX "\n", __func__, base);
|
|
1253 |
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
|
|
1245 | 1254 |
#endif |
1246 | 1255 |
io = cpu_register_io_memory(i2c_read, i2c_write, i2c); |
1247 | 1256 |
cpu_register_physical_memory(base, 0x011, io); |
... | ... | |
1269 | 1278 |
static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr) |
1270 | 1279 |
{ |
1271 | 1280 |
#ifdef DEBUG_GPT |
1272 |
printf("%s: addr " PADDRX "\n", __func__, addr);
|
|
1281 |
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
|
|
1273 | 1282 |
#endif |
1274 | 1283 |
/* XXX: generate a bus fault */ |
1275 | 1284 |
return -1; |
... | ... | |
1279 | 1288 |
target_phys_addr_t addr, uint32_t value) |
1280 | 1289 |
{ |
1281 | 1290 |
#ifdef DEBUG_I2C |
1282 |
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
|
1291 |
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
|
1292 |
value); |
|
1283 | 1293 |
#endif |
1284 | 1294 |
/* XXX: generate a bus fault */ |
1285 | 1295 |
} |
... | ... | |
1287 | 1297 |
static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr) |
1288 | 1298 |
{ |
1289 | 1299 |
#ifdef DEBUG_GPT |
1290 |
printf("%s: addr " PADDRX "\n", __func__, addr);
|
|
1300 |
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
|
|
1291 | 1301 |
#endif |
1292 | 1302 |
/* XXX: generate a bus fault */ |
1293 | 1303 |
return -1; |
... | ... | |
1297 | 1307 |
target_phys_addr_t addr, uint32_t value) |
1298 | 1308 |
{ |
1299 | 1309 |
#ifdef DEBUG_I2C |
1300 |
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
|
1310 |
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
|
1311 |
value); |
|
1301 | 1312 |
#endif |
1302 | 1313 |
/* XXX: generate a bus fault */ |
1303 | 1314 |
} |
... | ... | |
1361 | 1372 |
int idx; |
1362 | 1373 |
|
1363 | 1374 |
#ifdef DEBUG_GPT |
1364 |
printf("%s: addr " PADDRX "\n", __func__, addr);
|
|
1375 |
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
|
|
1365 | 1376 |
#endif |
1366 | 1377 |
gpt = opaque; |
1367 | 1378 |
switch (addr) { |
... | ... | |
1416 | 1427 |
int idx; |
1417 | 1428 |
|
1418 | 1429 |
#ifdef DEBUG_I2C |
1419 |
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
|
1430 |
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
|
1431 |
value); |
|
1420 | 1432 |
#endif |
1421 | 1433 |
gpt = opaque; |
1422 | 1434 |
switch (addr) { |
... | ... | |
1522 | 1534 |
} |
1523 | 1535 |
gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt); |
1524 | 1536 |
#ifdef DEBUG_GPT |
1525 |
printf("%s: offset " PADDRX "\n", __func__, base);
|
|
1537 |
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
|
|
1526 | 1538 |
#endif |
1527 | 1539 |
io = cpu_register_io_memory(gpt_read, gpt_write, gpt); |
1528 | 1540 |
cpu_register_physical_memory(base, 0x0d4, io); |
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