Revision 90e189ec hw/ppc4xx_devs.c
| b/hw/ppc4xx_devs.c | ||
|---|---|---|
| 235 | 235 |
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| 236 | 236 |
uic = opaque; |
| 237 | 237 |
dcrn -= uic->dcr_base; |
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LOG_UIC("%s: dcr %d val " ADDRX "\n", __func__, dcrn, val);
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|
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LOG_UIC("%s: dcr %d val " TARGET_FMT_lx "\n", __func__, dcrn, val);
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|
| 239 | 239 |
switch (dcrn) {
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| 240 | 240 |
case DCR_UICSR: |
| 241 | 241 |
uic->uicsr &= ~val; |
| ... | ... | |
| 368 | 368 |
bcr = 0x000C0000; |
| 369 | 369 |
break; |
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default: |
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printf("%s: invalid RAM size " PADDRX "\n", __func__, ram_size);
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printf("%s: invalid RAM size " TARGET_FMT_plx "\n", __func__,
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ram_size); |
|
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return 0x00000000; |
| 373 | 374 |
} |
| 374 | 375 |
bcr |= ram_base & 0xFF800000; |
| ... | ... | |
| 401 | 402 |
if (*bcrp & 0x00000001) {
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| 402 | 403 |
/* Unmap RAM */ |
| 403 | 404 |
#ifdef DEBUG_SDRAM |
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printf("%s: unmap RAM area " PADDRX " " ADDRX "\n",
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printf("%s: unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
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__func__, sdram_base(*bcrp), sdram_size(*bcrp)); |
| 406 | 407 |
#endif |
| 407 | 408 |
cpu_register_physical_memory(sdram_base(*bcrp), sdram_size(*bcrp), |
| ... | ... | |
| 410 | 411 |
*bcrp = bcr & 0xFFDEE001; |
| 411 | 412 |
if (enabled && (bcr & 0x00000001)) {
|
| 412 | 413 |
#ifdef DEBUG_SDRAM |
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printf("%s: Map RAM area " PADDRX " " ADDRX "\n",
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printf("%s: Map RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
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__func__, sdram_base(bcr), sdram_size(bcr)); |
| 415 | 416 |
#endif |
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cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr), |
| ... | ... | |
| 439 | 440 |
|
| 440 | 441 |
for (i = 0; i < sdram->nbanks; i++) {
|
| 441 | 442 |
#ifdef DEBUG_SDRAM |
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printf("%s: Unmap RAM area " PADDRX " " ADDRX "\n",
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printf("%s: Unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
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__func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i])); |
| 444 | 445 |
#endif |
| 445 | 446 |
cpu_register_physical_memory(sdram_base(sdram->bcr[i]), |
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