Revision 90e189ec target-ppc/helper.c
b/target-ppc/helper.c | ||
---|---|---|
345 | 345 |
nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code); |
346 | 346 |
tlb = &env->tlb[nr].tlb6; |
347 | 347 |
if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) { |
348 |
LOG_SWTLB("TLB invalidate %d/%d " ADDRX "\n",
|
|
349 |
nr, env->nb_tlb, eaddr);
|
|
348 |
LOG_SWTLB("TLB invalidate %d/%d " TARGET_FMT_lx "\n", nr,
|
|
349 |
env->nb_tlb, eaddr); |
|
350 | 350 |
pte_invalidate(&tlb->pte0); |
351 | 351 |
tlb_flush_page(env, tlb->EPN); |
352 | 352 |
} |
... | ... | |
371 | 371 |
|
372 | 372 |
nr = ppc6xx_tlb_getnum(env, EPN, way, is_code); |
373 | 373 |
tlb = &env->tlb[nr].tlb6; |
374 |
LOG_SWTLB("Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX
|
|
375 |
" PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1);
|
|
374 |
LOG_SWTLB("Set TLB %d/%d EPN " TARGET_FMT_lx " PTE0 " TARGET_FMT_lx
|
|
375 |
" PTE1 " TARGET_FMT_lx "\n", nr, env->nb_tlb, EPN, pte0, pte1);
|
|
376 | 376 |
/* Invalidate any pending reference in Qemu for this virtual address */ |
377 | 377 |
__ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1); |
378 | 378 |
tlb->pte0 = pte0; |
... | ... | |
397 | 397 |
tlb = &env->tlb[nr].tlb6; |
398 | 398 |
/* This test "emulates" the PTE index match for hardware TLBs */ |
399 | 399 |
if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) { |
400 |
LOG_SWTLB("TLB %d/%d %s [" ADDRX " " ADDRX |
|
401 |
"] <> " ADDRX "\n", |
|
402 |
nr, env->nb_tlb, |
|
403 |
pte_is_valid(tlb->pte0) ? "valid" : "inval", |
|
404 |
tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr); |
|
400 |
LOG_SWTLB("TLB %d/%d %s [" TARGET_FMT_lx " " TARGET_FMT_lx |
|
401 |
"] <> " TARGET_FMT_lx "\n", nr, env->nb_tlb, |
|
402 |
pte_is_valid(tlb->pte0) ? "valid" : "inval", |
|
403 |
tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr); |
|
405 | 404 |
continue; |
406 | 405 |
} |
407 |
LOG_SWTLB("TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX |
|
408 |
" %c %c\n", |
|
409 |
nr, env->nb_tlb, |
|
410 |
pte_is_valid(tlb->pte0) ? "valid" : "inval", |
|
411 |
tlb->EPN, eaddr, tlb->pte1, |
|
412 |
rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D'); |
|
406 |
LOG_SWTLB("TLB %d/%d %s " TARGET_FMT_lx " <> " TARGET_FMT_lx " " |
|
407 |
TARGET_FMT_lx " %c %c\n", nr, env->nb_tlb, |
|
408 |
pte_is_valid(tlb->pte0) ? "valid" : "inval", |
|
409 |
tlb->EPN, eaddr, tlb->pte1, |
|
410 |
rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D'); |
|
413 | 411 |
switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw, access_type)) { |
414 | 412 |
case -3: |
415 | 413 |
/* TLB inconsistency */ |
... | ... | |
436 | 434 |
} |
437 | 435 |
if (best != -1) { |
438 | 436 |
done: |
439 |
LOG_SWTLB("found TLB at addr " PADDRX " prot=%01x ret=%d\n",
|
|
440 |
ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
|
|
437 |
LOG_SWTLB("found TLB at addr " TARGET_FMT_plx " prot=%01x ret=%d\n",
|
|
438 |
ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret); |
|
441 | 439 |
/* Update page flags */ |
442 | 440 |
pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw); |
443 | 441 |
} |
... | ... | |
479 | 477 |
int key, pp, valid, prot; |
480 | 478 |
|
481 | 479 |
bl = (*BATl & 0x0000003F) << 17; |
482 |
LOG_BATS("b %02x ==> bl " ADDRX " msk " ADDRX "\n",
|
|
483 |
(uint8_t)(*BATl & 0x0000003F), bl, ~bl);
|
|
480 |
LOG_BATS("b %02x ==> bl " TARGET_FMT_lx " msk " TARGET_FMT_lx "\n",
|
|
481 |
(uint8_t)(*BATl & 0x0000003F), bl, ~bl); |
|
484 | 482 |
prot = 0; |
485 | 483 |
valid = (*BATl >> 6) & 1; |
486 | 484 |
if (valid) { |
... | ... | |
504 | 502 |
int i, valid, prot; |
505 | 503 |
int ret = -1; |
506 | 504 |
|
507 |
LOG_BATS("%s: %cBAT v " ADDRX "\n", __func__,
|
|
508 |
type == ACCESS_CODE ? 'I' : 'D', virtual);
|
|
505 |
LOG_BATS("%s: %cBAT v " TARGET_FMT_lx "\n", __func__,
|
|
506 |
type == ACCESS_CODE ? 'I' : 'D', virtual); |
|
509 | 507 |
switch (type) { |
510 | 508 |
case ACCESS_CODE: |
511 | 509 |
BATlt = env->IBAT[1]; |
... | ... | |
527 | 525 |
} else { |
528 | 526 |
bat_size_prot(env, &bl, &valid, &prot, BATu, BATl); |
529 | 527 |
} |
530 |
LOG_BATS("%s: %cBAT%d v " ADDRX " BATu " ADDRX
|
|
531 |
" BATl " ADDRX "\n", __func__,
|
|
532 |
type == ACCESS_CODE ? 'I' : 'D', i, virtual, *BATu, *BATl);
|
|
528 |
LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
|
|
529 |
" BATl " TARGET_FMT_lx "\n", __func__,
|
|
530 |
type == ACCESS_CODE ? 'I' : 'D', i, virtual, *BATu, *BATl); |
|
533 | 531 |
if ((virtual & 0xF0000000) == BEPIu && |
534 | 532 |
((virtual & 0x0FFE0000) & ~bl) == BEPIl) { |
535 | 533 |
/* BAT matches */ |
... | ... | |
542 | 540 |
ctx->prot = prot; |
543 | 541 |
ret = check_prot(ctx->prot, rw, type); |
544 | 542 |
if (ret == 0) |
545 |
LOG_BATS("BAT %d match: r " PADDRX " prot=%c%c\n",
|
|
543 |
LOG_BATS("BAT %d match: r " TARGET_FMT_plx " prot=%c%c\n",
|
|
546 | 544 |
i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-', |
547 | 545 |
ctx->prot & PAGE_WRITE ? 'W' : '-'); |
548 | 546 |
break; |
... | ... | |
552 | 550 |
if (ret < 0) { |
553 | 551 |
#if defined(DEBUG_BATS) |
554 | 552 |
if (qemu_log_enabled()) { |
555 |
LOG_BATS("no BAT match for " ADDRX ":\n", virtual);
|
|
553 |
LOG_BATS("no BAT match for " TARGET_FMT_lx ":\n", virtual);
|
|
556 | 554 |
for (i = 0; i < 4; i++) { |
557 | 555 |
BATu = &BATut[i]; |
558 | 556 |
BATl = &BATlt[i]; |
559 | 557 |
BEPIu = *BATu & 0xF0000000; |
560 | 558 |
BEPIl = *BATu & 0x0FFE0000; |
561 | 559 |
bl = (*BATu & 0x00001FFC) << 15; |
562 |
LOG_BATS("%s: %cBAT%d v " ADDRX " BATu " ADDRX |
|
563 |
" BATl " ADDRX " \n\t" ADDRX " " ADDRX " " ADDRX "\n", |
|
560 |
LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx |
|
561 |
" BATl " TARGET_FMT_lx " \n\t" TARGET_FMT_lx " " |
|
562 |
TARGET_FMT_lx " " TARGET_FMT_lx "\n", |
|
564 | 563 |
__func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, |
565 | 564 |
*BATu, *BATl, BEPIu, BEPIl, bl); |
566 | 565 |
} |
... | ... | |
594 | 593 |
& TARGET_PAGE_MASK; |
595 | 594 |
|
596 | 595 |
r = pte64_check(ctx, pte0, pte1, h, rw, type); |
597 |
LOG_MMU("Load pte from " ADDRX " => " ADDRX " " ADDRX |
|
598 |
" %d %d %d " ADDRX "\n", |
|
599 |
base + (i * 16), pte0, pte1, |
|
600 |
(int)(pte0 & 1), h, (int)((pte0 >> 1) & 1), |
|
601 |
ctx->ptem); |
|
596 |
LOG_MMU("Load pte from " TARGET_FMT_lx " => " TARGET_FMT_lx " " |
|
597 |
TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n", |
|
598 |
base + (i * 16), pte0, pte1, (int)(pte0 & 1), h, |
|
599 |
(int)((pte0 >> 1) & 1), ctx->ptem); |
|
602 | 600 |
} else |
603 | 601 |
#endif |
604 | 602 |
{ |
605 | 603 |
pte0 = ldl_phys(base + (i * 8)); |
606 | 604 |
pte1 = ldl_phys(base + (i * 8) + 4); |
607 | 605 |
r = pte32_check(ctx, pte0, pte1, h, rw, type); |
608 |
LOG_MMU("Load pte from " ADDRX " => " ADDRX " " ADDRX |
|
609 |
" %d %d %d " ADDRX "\n", |
|
610 |
base + (i * 8), pte0, pte1, |
|
611 |
(int)(pte0 >> 31), h, (int)((pte0 >> 6) & 1), |
|
612 |
ctx->ptem); |
|
606 |
LOG_MMU("Load pte from " TARGET_FMT_lx " => " TARGET_FMT_lx " " |
|
607 |
TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n", |
|
608 |
base + (i * 8), pte0, pte1, (int)(pte0 >> 31), h, |
|
609 |
(int)((pte0 >> 6) & 1), ctx->ptem); |
|
613 | 610 |
} |
614 | 611 |
switch (r) { |
615 | 612 |
case -3: |
... | ... | |
637 | 634 |
} |
638 | 635 |
if (good != -1) { |
639 | 636 |
done: |
640 |
LOG_MMU("found PTE at addr " PADDRX " prot=%01x ret=%d\n",
|
|
641 |
ctx->raddr, ctx->prot, ret);
|
|
637 |
LOG_MMU("found PTE at addr " TARGET_FMT_lx " prot=%01x ret=%d\n",
|
|
638 |
ctx->raddr, ctx->prot, ret); |
|
642 | 639 |
/* Update page flags */ |
643 | 640 |
pte1 = ctx->raddr; |
644 | 641 |
if (pte_update_flags(ctx, &pte1, ret, rw) == 1) { |
... | ... | |
730 | 727 |
int n, ret; |
731 | 728 |
|
732 | 729 |
ret = -5; |
733 |
LOG_SLB("%s: eaddr " ADDRX "\n", __func__, eaddr);
|
|
730 |
LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr);
|
|
734 | 731 |
mask = 0x0000000000000000ULL; /* Avoid gcc warning */ |
735 | 732 |
for (n = 0; n < env->slb_nr; n++) { |
736 | 733 |
ppc_slb_t *slb = slb_get_entry(env, n); |
... | ... | |
825 | 822 |
rt = 0; |
826 | 823 |
} |
827 | 824 |
LOG_SLB("%s: %016" PRIx64 " %08" PRIx32 " => %d " |
828 |
ADDRX "\n", __func__, slb->tmp64, slb->tmp, slb_nr, rt);
|
|
825 |
TARGET_FMT_lx "\n", __func__, slb->tmp64, slb->tmp, slb_nr, rt);
|
|
829 | 826 |
|
830 | 827 |
return rt; |
831 | 828 |
} |
... | ... | |
849 | 846 |
slb->tmp64 = (esid << 28) | valid | (vsid >> 24); |
850 | 847 |
slb->tmp = (vsid << 8) | (flags << 3); |
851 | 848 |
|
852 |
LOG_SLB("%s: %d " ADDRX " - " ADDRX " => %016" PRIx64
|
|
853 |
" %08" PRIx32 "\n", __func__, |
|
854 |
slb_nr, rb, rs, slb->tmp64, slb->tmp);
|
|
849 |
LOG_SLB("%s: %d " TARGET_FMT_lx " - " TARGET_FMT_lx " => %016" PRIx64
|
|
850 |
" %08" PRIx32 "\n", __func__, slb_nr, rb, rs, slb->tmp64,
|
|
851 |
slb->tmp); |
|
855 | 852 |
|
856 | 853 |
slb_set_entry(env, slb_nr, slb); |
857 | 854 |
} |
... | ... | |
909 | 906 |
sdr_sh = 16; |
910 | 907 |
sdr_mask = 0xFFC0; |
911 | 908 |
target_page_bits = TARGET_PAGE_BITS; |
912 |
LOG_MMU("Check segment v=" ADDRX " %d " ADDRX
|
|
913 |
" nip=" ADDRX " lr=" ADDRX " ir=%d dr=%d pr=%d %d t=%d\n",
|
|
914 |
eaddr, (int)(eaddr >> 28), sr, env->nip,
|
|
915 |
env->lr, (int)msr_ir, (int)msr_dr, pr != 0 ? 1 : 0,
|
|
916 |
rw, type);
|
|
909 |
LOG_MMU("Check segment v=" TARGET_FMT_lx " %d " TARGET_FMT_lx " nip="
|
|
910 |
TARGET_FMT_lx " lr=" TARGET_FMT_lx
|
|
911 |
" ir=%d dr=%d pr=%d %d t=%d\n",
|
|
912 |
eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir,
|
|
913 |
(int)msr_dr, pr != 0 ? 1 : 0, rw, type);
|
|
917 | 914 |
} |
918 |
LOG_MMU("pte segment: key=%d ds %d nx %d vsid " ADDRX "\n",
|
|
919 |
ctx->key, ds, ctx->nx, vsid);
|
|
915 |
LOG_MMU("pte segment: key=%d ds %d nx %d vsid " TARGET_FMT_lx "\n",
|
|
916 |
ctx->key, ds, ctx->nx, vsid); |
|
920 | 917 |
ret = -1; |
921 | 918 |
if (!ds) { |
922 | 919 |
/* Check if instruction fetch is allowed, if needed */ |
... | ... | |
937 | 934 |
hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask; |
938 | 935 |
} |
939 | 936 |
mask = (htab_mask << sdr_sh) | sdr_mask; |
940 |
LOG_MMU("sdr " PADDRX " sh %d hash " PADDRX
|
|
941 |
" mask " PADDRX " " ADDRX "\n",
|
|
942 |
sdr, sdr_sh, hash, mask, page_mask);
|
|
937 |
LOG_MMU("sdr " TARGET_FMT_plx " sh %d hash " TARGET_FMT_plx
|
|
938 |
" mask " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
|
|
939 |
sdr, sdr_sh, hash, mask, page_mask); |
|
943 | 940 |
ctx->pg_addr[0] = get_pgaddr(sdr, sdr_sh, hash, mask); |
944 | 941 |
/* Secondary table address */ |
945 | 942 |
hash = (~hash) & vsid_mask; |
946 |
LOG_MMU("sdr " PADDRX " sh %d hash " PADDRX |
|
947 |
" mask " PADDRX "\n", |
|
948 |
sdr, sdr_sh, hash, mask); |
|
943 |
LOG_MMU("sdr " TARGET_FMT_plx " sh %d hash " TARGET_FMT_plx |
|
944 |
" mask " TARGET_FMT_plx "\n", sdr, sdr_sh, hash, mask); |
|
949 | 945 |
ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask); |
950 | 946 |
#if defined(TARGET_PPC64) |
951 | 947 |
if (env->mmu_model & POWERPC_MMU_64) { |
... | ... | |
968 | 964 |
/* Software TLB search */ |
969 | 965 |
ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type); |
970 | 966 |
} else { |
971 |
LOG_MMU("0 sdr1=" PADDRX " vsid=" ADDRX " "
|
|
972 |
"api=" ADDRX " hash=" PADDRX
|
|
973 |
" pg_addr=" PADDRX "\n",
|
|
974 |
sdr, vsid, pgidx, hash, ctx->pg_addr[0]);
|
|
967 |
LOG_MMU("0 sdr1=" TARGET_FMT_plx " vsid=" TARGET_FMT_lx " "
|
|
968 |
"api=" TARGET_FMT_lx " hash=" TARGET_FMT_plx
|
|
969 |
" pg_addr=" TARGET_FMT_plx "\n",
|
|
970 |
sdr, vsid, pgidx, hash, ctx->pg_addr[0]); |
|
975 | 971 |
/* Primary table lookup */ |
976 | 972 |
ret = find_pte(env, ctx, 0, rw, type, target_page_bits); |
977 | 973 |
if (ret < 0) { |
978 | 974 |
/* Secondary table lookup */ |
979 | 975 |
if (eaddr != 0xEFFFFFFF) |
980 |
LOG_MMU("1 sdr1=" PADDRX " vsid=" ADDRX " "
|
|
981 |
"api=" ADDRX " hash=" PADDRX
|
|
982 |
" pg_addr=" PADDRX "\n",
|
|
983 |
sdr, vsid, pgidx, hash, ctx->pg_addr[1]);
|
|
976 |
LOG_MMU("1 sdr1=" TARGET_FMT_plx " vsid=" TARGET_FMT_lx " "
|
|
977 |
"api=" TARGET_FMT_lx " hash=" TARGET_FMT_plx
|
|
978 |
" pg_addr=" TARGET_FMT_plx "\n", sdr, vsid,
|
|
979 |
pgidx, hash, ctx->pg_addr[1]); |
|
984 | 980 |
ret2 = find_pte(env, ctx, 1, rw, type, |
985 | 981 |
target_page_bits); |
986 | 982 |
if (ret2 != -1) |
... | ... | |
991 | 987 |
if (qemu_log_enabled()) { |
992 | 988 |
target_phys_addr_t curaddr; |
993 | 989 |
uint32_t a0, a1, a2, a3; |
994 |
qemu_log("Page table: " PADDRX " len " PADDRX "\n",
|
|
995 |
sdr, mask + 0x80); |
|
990 |
qemu_log("Page table: " TARGET_FMT_plx " len " TARGET_FMT_plx
|
|
991 |
"\n", sdr, mask + 0x80);
|
|
996 | 992 |
for (curaddr = sdr; curaddr < (sdr + mask + 0x80); |
997 | 993 |
curaddr += 16) { |
998 | 994 |
a0 = ldl_phys(curaddr); |
... | ... | |
1000 | 996 |
a2 = ldl_phys(curaddr + 8); |
1001 | 997 |
a3 = ldl_phys(curaddr + 12); |
1002 | 998 |
if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) { |
1003 |
qemu_log(PADDRX ": %08x %08x %08x %08x\n",
|
|
1004 |
curaddr, a0, a1, a2, a3);
|
|
999 |
qemu_log(TARGET_FMT_plx ": %08x %08x %08x %08x\n",
|
|
1000 |
curaddr, a0, a1, a2, a3); |
|
1005 | 1001 |
} |
1006 | 1002 |
} |
1007 | 1003 |
} |
... | ... | |
1066 | 1062 |
return -1; |
1067 | 1063 |
} |
1068 | 1064 |
mask = ~(tlb->size - 1); |
1069 |
LOG_SWTLB("%s: TLB %d address " ADDRX " PID %u <=> " ADDRX
|
|
1070 |
" " ADDRX " %u\n",
|
|
1071 |
__func__, i, address, pid, tlb->EPN, mask, (uint32_t)tlb->PID);
|
|
1065 |
LOG_SWTLB("%s: TLB %d address " TARGET_FMT_lx " PID %u <=> " TARGET_FMT_lx
|
|
1066 |
" " TARGET_FMT_lx " %u\n", __func__, i, address, pid, tlb->EPN,
|
|
1067 |
mask, (uint32_t)tlb->PID); |
|
1072 | 1068 |
/* Check PID */ |
1073 | 1069 |
if (tlb->PID != 0 && tlb->PID != pid) |
1074 | 1070 |
return -1; |
... | ... | |
1191 | 1187 |
} |
1192 | 1188 |
if (ret >= 0) { |
1193 | 1189 |
ctx->raddr = raddr; |
1194 |
LOG_SWTLB("%s: access granted " ADDRX " => " PADDRX
|
|
1195 |
" %d %d\n", __func__, address, ctx->raddr, ctx->prot,
|
|
1196 |
ret);
|
|
1190 |
LOG_SWTLB("%s: access granted " TARGET_FMT_lx " => " TARGET_FMT_plx
|
|
1191 |
" %d %d\n", __func__, address, ctx->raddr, ctx->prot, |
|
1192 |
ret); |
|
1197 | 1193 |
return 0; |
1198 | 1194 |
} |
1199 | 1195 |
} |
1200 |
LOG_SWTLB("%s: access refused " ADDRX " => " PADDRX |
|
1201 |
" %d %d\n", __func__, address, raddr, ctx->prot, |
|
1202 |
ret); |
|
1196 |
LOG_SWTLB("%s: access refused " TARGET_FMT_lx " => " TARGET_FMT_plx |
|
1197 |
" %d %d\n", __func__, address, raddr, ctx->prot, ret); |
|
1203 | 1198 |
|
1204 | 1199 |
return ret; |
1205 | 1200 |
} |
... | ... | |
1382 | 1377 |
} |
1383 | 1378 |
} |
1384 | 1379 |
#if 0 |
1385 |
qemu_log("%s address " ADDRX " => %d " PADDRX "\n",
|
|
1386 |
__func__, eaddr, ret, ctx->raddr);
|
|
1380 |
qemu_log("%s address " TARGET_FMT_lx " => %d " TARGET_FMT_plx "\n",
|
|
1381 |
__func__, eaddr, ret, ctx->raddr); |
|
1387 | 1382 |
#endif |
1388 | 1383 |
|
1389 | 1384 |
return ret; |
... | ... | |
1670 | 1665 |
|
1671 | 1666 |
base = BATu & ~0x0001FFFF; |
1672 | 1667 |
end = base + mask + 0x00020000; |
1673 |
LOG_BATS("Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n",
|
|
1674 |
base, end, mask);
|
|
1668 |
LOG_BATS("Flush BAT from " TARGET_FMT_lx " to " TARGET_FMT_lx " ("
|
|
1669 |
TARGET_FMT_lx ")\n", base, end, mask);
|
|
1675 | 1670 |
for (page = base; page != end; page += TARGET_PAGE_SIZE) |
1676 | 1671 |
tlb_flush_page(env, page); |
1677 | 1672 |
LOG_BATS("Flush done\n"); |
... | ... | |
1681 | 1676 |
static inline void dump_store_bat(CPUPPCState *env, char ID, int ul, int nr, |
1682 | 1677 |
target_ulong value) |
1683 | 1678 |
{ |
1684 |
LOG_BATS("Set %cBAT%d%c to " ADDRX " (" ADDRX ")\n",
|
|
1685 |
ID, nr, ul == 0 ? 'u' : 'l', value, env->nip);
|
|
1679 |
LOG_BATS("Set %cBAT%d%c to " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", ID,
|
|
1680 |
nr, ul == 0 ? 'u' : 'l', value, env->nip); |
|
1686 | 1681 |
} |
1687 | 1682 |
|
1688 | 1683 |
void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value) |
... | ... | |
1952 | 1947 |
|
1953 | 1948 |
void ppc_store_sdr1 (CPUPPCState *env, target_ulong value) |
1954 | 1949 |
{ |
1955 |
LOG_MMU("%s: " ADDRX "\n", __func__, value);
|
|
1950 |
LOG_MMU("%s: " TARGET_FMT_lx "\n", __func__, value);
|
|
1956 | 1951 |
if (env->sdr1 != value) { |
1957 | 1952 |
/* XXX: for PowerPC 64, should check that the HTABSIZE value |
1958 | 1953 |
* is <= 28 |
... | ... | |
1972 | 1967 |
|
1973 | 1968 |
void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value) |
1974 | 1969 |
{ |
1975 |
LOG_MMU("%s: reg=%d " ADDRX " " ADDRX "\n",
|
|
1976 |
__func__, srnum, value, env->sr[srnum]);
|
|
1970 |
LOG_MMU("%s: reg=%d " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__,
|
|
1971 |
srnum, value, env->sr[srnum]); |
|
1977 | 1972 |
#if defined(TARGET_PPC64) |
1978 | 1973 |
if (env->mmu_model & POWERPC_MMU_64) { |
1979 | 1974 |
uint64_t rb = 0, rs = 0; |
... | ... | |
2037 | 2032 |
static inline void dump_syscall(CPUState *env) |
2038 | 2033 |
{ |
2039 | 2034 |
qemu_log_mask(CPU_LOG_INT, "syscall r0=" REGX " r3=" REGX " r4=" REGX |
2040 |
" r5=" REGX " r6=" REGX " nip=" ADDRX "\n", |
|
2041 |
ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3), ppc_dump_gpr(env, 4), |
|
2042 |
ppc_dump_gpr(env, 5), ppc_dump_gpr(env, 6), env->nip); |
|
2035 |
" r5=" REGX " r6=" REGX " nip=" TARGET_FMT_lx "\n", |
|
2036 |
ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3), |
|
2037 |
ppc_dump_gpr(env, 4), ppc_dump_gpr(env, 5), |
|
2038 |
ppc_dump_gpr(env, 6), env->nip); |
|
2043 | 2039 |
} |
2044 | 2040 |
|
2045 | 2041 |
/* Note that this function should be greatly optimized |
... | ... | |
2061 | 2057 |
lpes1 = 1; |
2062 | 2058 |
} |
2063 | 2059 |
|
2064 |
qemu_log_mask(CPU_LOG_INT, "Raise exception at " ADDRX " => %08x (%02x)\n",
|
|
2065 |
env->nip, excp, env->error_code); |
|
2060 |
qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
|
|
2061 |
" => %08x (%02x)\n", env->nip, excp, env->error_code);
|
|
2066 | 2062 |
msr = env->msr; |
2067 | 2063 |
new_msr = msr; |
2068 | 2064 |
srr0 = SPR_SRR0; |
... | ... | |
2129 | 2125 |
} |
2130 | 2126 |
goto store_next; |
2131 | 2127 |
case POWERPC_EXCP_DSI: /* Data storage exception */ |
2132 |
LOG_EXCP("DSI exception: DSISR=" ADDRX" DAR=" ADDRX "\n",
|
|
2133 |
env->spr[SPR_DSISR], env->spr[SPR_DAR]);
|
|
2128 |
LOG_EXCP("DSI exception: DSISR=" TARGET_FMT_lx" DAR=" TARGET_FMT_lx
|
|
2129 |
"\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
|
|
2134 | 2130 |
new_msr &= ~((target_ulong)1 << MSR_RI); |
2135 | 2131 |
if (lpes1 == 0) |
2136 | 2132 |
new_msr |= (target_ulong)MSR_HVB; |
2137 | 2133 |
goto store_next; |
2138 | 2134 |
case POWERPC_EXCP_ISI: /* Instruction storage exception */ |
2139 |
LOG_EXCP("ISI exception: msr=" ADDRX ", nip=" ADDRX "\n",
|
|
2140 |
msr, env->nip);
|
|
2135 |
LOG_EXCP("ISI exception: msr=" TARGET_FMT_lx ", nip=" TARGET_FMT_lx
|
|
2136 |
"\n", msr, env->nip);
|
|
2141 | 2137 |
new_msr &= ~((target_ulong)1 << MSR_RI); |
2142 | 2138 |
if (lpes1 == 0) |
2143 | 2139 |
new_msr |= (target_ulong)MSR_HVB; |
... | ... | |
2174 | 2170 |
msr |= 0x00010000; |
2175 | 2171 |
break; |
2176 | 2172 |
case POWERPC_EXCP_INVAL: |
2177 |
LOG_EXCP("Invalid instruction at " ADDRX "\n", |
|
2178 |
env->nip); |
|
2173 |
LOG_EXCP("Invalid instruction at " TARGET_FMT_lx "\n", env->nip); |
|
2179 | 2174 |
new_msr &= ~((target_ulong)1 << MSR_RI); |
2180 | 2175 |
if (lpes1 == 0) |
2181 | 2176 |
new_msr |= (target_ulong)MSR_HVB; |
... | ... | |
2449 | 2444 |
miss = &env->spr[SPR_DMISS]; |
2450 | 2445 |
cmp = &env->spr[SPR_DCMP]; |
2451 | 2446 |
} |
2452 |
qemu_log("6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
|
|
2453 |
" H1 " ADDRX " H2 " ADDRX " %08x\n",
|
|
2454 |
es, en, *miss, en, *cmp, |
|
2455 |
env->spr[SPR_HASH1], env->spr[SPR_HASH2], |
|
2456 |
env->error_code); |
|
2447 |
qemu_log("6xx %sTLB miss: %cM " TARGET_FMT_lx " %cC "
|
|
2448 |
TARGET_FMT_lx " H1 " TARGET_FMT_lx " H2 "
|
|
2449 |
TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp,
|
|
2450 |
env->spr[SPR_HASH1], env->spr[SPR_HASH2],
|
|
2451 |
env->error_code);
|
|
2457 | 2452 |
} |
2458 | 2453 |
#endif |
2459 | 2454 |
msr |= env->crf[0] << 28; |
... | ... | |
2482 | 2477 |
miss = &env->spr[SPR_TLBMISS]; |
2483 | 2478 |
cmp = &env->spr[SPR_PTEHI]; |
2484 | 2479 |
} |
2485 |
qemu_log("74xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
|
|
2486 |
" %08x\n",
|
|
2487 |
es, en, *miss, en, *cmp, env->error_code);
|
|
2480 |
qemu_log("74xx %sTLB miss: %cM " TARGET_FMT_lx " %cC "
|
|
2481 |
TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp,
|
|
2482 |
env->error_code); |
|
2488 | 2483 |
} |
2489 | 2484 |
#endif |
2490 | 2485 |
msr |= env->error_code; /* key bit */ |
... | ... | |
2748 | 2743 |
|
2749 | 2744 |
void cpu_dump_rfi (target_ulong RA, target_ulong msr) |
2750 | 2745 |
{ |
2751 |
qemu_log("Return from exception at " ADDRX " with flags " ADDRX "\n",
|
|
2752 |
RA, msr); |
|
2746 |
qemu_log("Return from exception at " TARGET_FMT_lx " with flags "
|
|
2747 |
TARGET_FMT_lx "\n", RA, msr);
|
|
2753 | 2748 |
} |
2754 | 2749 |
|
2755 | 2750 |
void cpu_ppc_reset (void *opaque) |
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