Revision 9143e598
| b/target-sparc/cpu.h | ||
|---|---|---|
| 127 | 127 |
#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0) |
| 128 | 128 |
#define FSR_FTT_IEEE_EXCP (1 << 14) |
| 129 | 129 |
#define FSR_FTT_UNIMPFPOP (3 << 14) |
| 130 |
#define FSR_FTT_SEQ_ERROR (4 << 14) |
|
| 130 | 131 |
#define FSR_FTT_INVAL_FPR (6 << 14) |
| 131 | 132 |
|
| 132 | 133 |
#define FSR_FCC1 (1<<11) |
| ... | ... | |
| 239 | 240 |
#else |
| 240 | 241 |
#define GET_FSR32(env) (env->fsr) |
| 241 | 242 |
#define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
|
| 242 |
env->fsr = (_tmp & 0xcfc1ffff) | (env->fsr & 0x000e0000); \
|
|
| 243 |
env->fsr = (_tmp & 0xcfc1dfff) | (env->fsr & 0x000e0000); \
|
|
| 243 | 244 |
} while (0) |
| 244 | 245 |
#endif |
| 245 | 246 |
|
| b/target-sparc/translate.c | ||
|---|---|---|
| 2602 | 2602 |
gen_op_stfsr(); |
| 2603 | 2603 |
gen_op_ldst(stf); |
| 2604 | 2604 |
break; |
| 2605 |
#if !defined(CONFIG_USER_ONLY) |
|
| 2605 | 2606 |
case 0x26: /* stdfq */ |
| 2606 |
goto nfpu_insn; |
|
| 2607 |
if (!supervisor(dc)) |
|
| 2608 |
goto priv_insn; |
|
| 2609 |
if (gen_trap_ifnofpu(dc)) |
|
| 2610 |
goto jmp_insn; |
|
| 2611 |
goto nfq_insn; |
|
| 2612 |
#endif |
|
| 2607 | 2613 |
case 0x27: |
| 2608 | 2614 |
gen_op_load_fpr_DT0(DFPREG(rd)); |
| 2609 | 2615 |
gen_op_ldst(stdf); |
| ... | ... | |
| 2675 | 2681 |
gen_op_fpexception_im(FSR_FTT_UNIMPFPOP); |
| 2676 | 2682 |
dc->is_br = 1; |
| 2677 | 2683 |
return; |
| 2684 |
#if !defined(CONFIG_USER_ONLY) |
|
| 2685 |
nfq_insn: |
|
| 2686 |
save_state(dc); |
|
| 2687 |
gen_op_fpexception_im(FSR_FTT_SEQ_ERROR); |
|
| 2688 |
dc->is_br = 1; |
|
| 2689 |
return; |
|
| 2690 |
#endif |
|
| 2678 | 2691 |
#ifndef TARGET_SPARC64 |
| 2679 | 2692 |
ncp_insn: |
| 2680 | 2693 |
save_state(dc); |
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