Revision 91736d37 target-sparc/helper.c
| b/target-sparc/helper.c | ||
|---|---|---|
| 28 | 28 |
#include "cpu.h" |
| 29 | 29 |
#include "exec-all.h" |
| 30 | 30 |
#include "qemu-common.h" |
| 31 |
#include "helper.h" |
|
| 32 | 31 |
|
| 33 | 32 |
//#define DEBUG_MMU |
| 34 | 33 |
//#define DEBUG_FEATURES |
| ... | ... | |
| 639 | 638 |
} |
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#endif |
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| 642 |
#ifdef TARGET_SPARC64 |
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| 643 |
#ifdef DEBUG_PCALL |
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static const char * const excp_names[0x80] = {
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| 645 |
[TT_TFAULT] = "Instruction Access Fault", |
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[TT_TMISS] = "Instruction Access MMU Miss", |
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[TT_CODE_ACCESS] = "Instruction Access Error", |
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[TT_ILL_INSN] = "Illegal Instruction", |
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[TT_PRIV_INSN] = "Privileged Instruction", |
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[TT_NFPU_INSN] = "FPU Disabled", |
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[TT_FP_EXCP] = "FPU Exception", |
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[TT_TOVF] = "Tag Overflow", |
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[TT_CLRWIN] = "Clean Windows", |
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[TT_DIV_ZERO] = "Division By Zero", |
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[TT_DFAULT] = "Data Access Fault", |
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[TT_DMISS] = "Data Access MMU Miss", |
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[TT_DATA_ACCESS] = "Data Access Error", |
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[TT_DPROT] = "Data Protection Error", |
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[TT_UNALIGNED] = "Unaligned Memory Access", |
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[TT_PRIV_ACT] = "Privileged Action", |
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[TT_EXTINT | 0x1] = "External Interrupt 1", |
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[TT_EXTINT | 0x2] = "External Interrupt 2", |
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[TT_EXTINT | 0x3] = "External Interrupt 3", |
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[TT_EXTINT | 0x4] = "External Interrupt 4", |
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[TT_EXTINT | 0x5] = "External Interrupt 5", |
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[TT_EXTINT | 0x6] = "External Interrupt 6", |
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[TT_EXTINT | 0x7] = "External Interrupt 7", |
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[TT_EXTINT | 0x8] = "External Interrupt 8", |
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[TT_EXTINT | 0x9] = "External Interrupt 9", |
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[TT_EXTINT | 0xa] = "External Interrupt 10", |
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[TT_EXTINT | 0xb] = "External Interrupt 11", |
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[TT_EXTINT | 0xc] = "External Interrupt 12", |
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[TT_EXTINT | 0xd] = "External Interrupt 13", |
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[TT_EXTINT | 0xe] = "External Interrupt 14", |
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[TT_EXTINT | 0xf] = "External Interrupt 15", |
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}; |
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#endif |
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|
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void do_interrupt(CPUState *env) |
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{
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int intno = env->exception_index; |
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|
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#ifdef DEBUG_PCALL |
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if (loglevel & CPU_LOG_INT) {
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static int count; |
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const char *name; |
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|
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if (intno < 0 || intno >= 0x180) |
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name = "Unknown"; |
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else if (intno >= 0x100) |
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name = "Trap Instruction"; |
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else if (intno >= 0xc0) |
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name = "Window Fill"; |
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else if (intno >= 0x80) |
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name = "Window Spill"; |
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else {
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name = excp_names[intno]; |
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if (!name) |
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name = "Unknown"; |
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} |
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|
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fprintf(logfile, "%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64 |
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" SP=%016" PRIx64 "\n", |
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count, name, intno, |
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env->pc, |
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env->npc, env->regwptr[6]); |
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cpu_dump_state(env, logfile, fprintf, 0); |
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#if 0 |
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{
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int i; |
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uint8_t *ptr; |
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|
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fprintf(logfile, " code="); |
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ptr = (uint8_t *)env->pc; |
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for(i = 0; i < 16; i++) {
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fprintf(logfile, " %02x", ldub(ptr + i)); |
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} |
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fprintf(logfile, "\n"); |
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} |
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#endif |
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count++; |
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} |
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#endif |
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#if !defined(CONFIG_USER_ONLY) |
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if (env->tl >= env->maxtl) {
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cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d)," |
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" Error state", env->exception_index, env->tl, env->maxtl); |
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return; |
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} |
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#endif |
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if (env->tl < env->maxtl - 1) {
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env->tl++; |
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} else {
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env->pstate |= PS_RED; |
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if (env->tl < env->maxtl) |
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env->tl++; |
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} |
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env->tsptr = &env->ts[env->tl & MAXTL_MASK]; |
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env->tsptr->tstate = ((uint64_t)GET_CCR(env) << 32) | |
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((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) | |
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GET_CWP64(env); |
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env->tsptr->tpc = env->pc; |
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env->tsptr->tnpc = env->npc; |
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env->tsptr->tt = intno; |
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if (!(env->def->features & CPU_FEATURE_GL)) {
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switch (intno) {
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case TT_IVEC: |
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change_pstate(PS_PEF | PS_PRIV | PS_IG); |
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break; |
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case TT_TFAULT: |
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case TT_TMISS: |
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case TT_DFAULT: |
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case TT_DMISS: |
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case TT_DPROT: |
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change_pstate(PS_PEF | PS_PRIV | PS_MG); |
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break; |
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default: |
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change_pstate(PS_PEF | PS_PRIV | PS_AG); |
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break; |
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} |
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} |
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if (intno == TT_CLRWIN) |
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cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1)); |
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else if ((intno & 0x1c0) == TT_SPILL) |
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cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2)); |
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else if ((intno & 0x1c0) == TT_FILL) |
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cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1)); |
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env->tbr &= ~0x7fffULL; |
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env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5); |
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env->pc = env->tbr; |
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env->npc = env->pc + 4; |
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env->exception_index = 0; |
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} |
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#else |
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#ifdef DEBUG_PCALL |
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static const char * const excp_names[0x80] = {
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[TT_TFAULT] = "Instruction Access Fault", |
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[TT_ILL_INSN] = "Illegal Instruction", |
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[TT_PRIV_INSN] = "Privileged Instruction", |
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[TT_NFPU_INSN] = "FPU Disabled", |
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[TT_WIN_OVF] = "Window Overflow", |
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[TT_WIN_UNF] = "Window Underflow", |
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[TT_UNALIGNED] = "Unaligned Memory Access", |
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[TT_FP_EXCP] = "FPU Exception", |
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[TT_DFAULT] = "Data Access Fault", |
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[TT_TOVF] = "Tag Overflow", |
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[TT_EXTINT | 0x1] = "External Interrupt 1", |
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[TT_EXTINT | 0x2] = "External Interrupt 2", |
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[TT_EXTINT | 0x3] = "External Interrupt 3", |
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[TT_EXTINT | 0x4] = "External Interrupt 4", |
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[TT_EXTINT | 0x5] = "External Interrupt 5", |
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[TT_EXTINT | 0x6] = "External Interrupt 6", |
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[TT_EXTINT | 0x7] = "External Interrupt 7", |
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[TT_EXTINT | 0x8] = "External Interrupt 8", |
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[TT_EXTINT | 0x9] = "External Interrupt 9", |
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[TT_EXTINT | 0xa] = "External Interrupt 10", |
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[TT_EXTINT | 0xb] = "External Interrupt 11", |
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[TT_EXTINT | 0xc] = "External Interrupt 12", |
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[TT_EXTINT | 0xd] = "External Interrupt 13", |
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[TT_EXTINT | 0xe] = "External Interrupt 14", |
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[TT_EXTINT | 0xf] = "External Interrupt 15", |
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[TT_TOVF] = "Tag Overflow", |
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[TT_CODE_ACCESS] = "Instruction Access Error", |
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[TT_DATA_ACCESS] = "Data Access Error", |
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[TT_DIV_ZERO] = "Division By Zero", |
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[TT_NCP_INSN] = "Coprocessor Disabled", |
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}; |
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#endif |
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|
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void do_interrupt(CPUState *env) |
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{
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int cwp, intno = env->exception_index; |
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|
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#ifdef DEBUG_PCALL |
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if (loglevel & CPU_LOG_INT) {
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static int count; |
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const char *name; |
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| 818 |
|
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if (intno < 0 || intno >= 0x100) |
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name = "Unknown"; |
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else if (intno >= 0x80) |
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name = "Trap Instruction"; |
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else {
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name = excp_names[intno]; |
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if (!name) |
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name = "Unknown"; |
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} |
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| 828 |
|
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fprintf(logfile, "%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n", |
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count, name, intno, |
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env->pc, |
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env->npc, env->regwptr[6]); |
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| 833 |
cpu_dump_state(env, logfile, fprintf, 0); |
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#if 0 |
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{
|
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| 836 |
int i; |
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uint8_t *ptr; |
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| 838 |
|
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fprintf(logfile, " code="); |
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ptr = (uint8_t *)env->pc; |
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| 841 |
for(i = 0; i < 16; i++) {
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fprintf(logfile, " %02x", ldub(ptr + i)); |
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} |
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fprintf(logfile, "\n"); |
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| 845 |
} |
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| 846 |
#endif |
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| 847 |
count++; |
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} |
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| 849 |
#endif |
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| 850 |
#if !defined(CONFIG_USER_ONLY) |
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| 851 |
if (env->psret == 0) {
|
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| 852 |
cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", |
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| 853 |
env->exception_index); |
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| 854 |
return; |
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| 855 |
} |
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| 856 |
#endif |
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| 857 |
env->psret = 0; |
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| 858 |
cwp = cpu_cwp_dec(env, env->cwp - 1); |
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| 859 |
cpu_set_cwp(env, cwp); |
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| 860 |
env->regwptr[9] = env->pc; |
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| 861 |
env->regwptr[10] = env->npc; |
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| 862 |
env->psrps = env->psrs; |
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| 863 |
env->psrs = 1; |
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| 864 |
env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4); |
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| 865 |
env->pc = env->tbr; |
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| 866 |
env->npc = env->pc + 4; |
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| 867 |
env->exception_index = 0; |
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| 868 |
} |
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| 869 |
#endif |
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| 870 |
|
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| 871 |
void memcpy32(target_ulong *dst, const target_ulong *src) |
|
| 872 |
{
|
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| 873 |
dst[0] = src[0]; |
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| 874 |
dst[1] = src[1]; |
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| 875 |
dst[2] = src[2]; |
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| 876 |
dst[3] = src[3]; |
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| 877 |
dst[4] = src[4]; |
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| 878 |
dst[5] = src[5]; |
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| 879 |
dst[6] = src[6]; |
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| 880 |
dst[7] = src[7]; |
|
| 881 |
} |
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| 882 |
|
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| 883 | 641 |
void cpu_reset(CPUSPARCState *env) |
| 884 | 642 |
{
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tlb_flush(env, 1); |
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