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1 | 6af0bf9c | bellard | /*
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2 | 6af0bf9c | bellard | * MIPS emulation helpers for qemu.
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3 | 6af0bf9c | bellard | *
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4 | 6af0bf9c | bellard | * Copyright (c) 2004-2005 Jocelyn Mayer
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5 | 6af0bf9c | bellard | *
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6 | 6af0bf9c | bellard | * This library is free software; you can redistribute it and/or
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7 | 6af0bf9c | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 6af0bf9c | bellard | * License as published by the Free Software Foundation; either
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9 | 6af0bf9c | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 6af0bf9c | bellard | *
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11 | 6af0bf9c | bellard | * This library is distributed in the hope that it will be useful,
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12 | 6af0bf9c | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 6af0bf9c | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 6af0bf9c | bellard | * Lesser General Public License for more details.
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15 | 6af0bf9c | bellard | *
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16 | 6af0bf9c | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 6af0bf9c | bellard | * License along with this library; if not, write to the Free Software
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18 | 6af0bf9c | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 6af0bf9c | bellard | */
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20 | 6af0bf9c | bellard | #include "exec.h" |
21 | 6af0bf9c | bellard | |
22 | 6af0bf9c | bellard | #define MIPS_DEBUG_DISAS
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23 | 6af0bf9c | bellard | |
24 | 4ad40f36 | bellard | #define GETPC() (__builtin_return_address(0)) |
25 | 4ad40f36 | bellard | |
26 | 6af0bf9c | bellard | /*****************************************************************************/
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27 | 6af0bf9c | bellard | /* Exceptions processing helpers */
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28 | 6af0bf9c | bellard | void cpu_loop_exit(void) |
29 | 6af0bf9c | bellard | { |
30 | 6af0bf9c | bellard | longjmp(env->jmp_env, 1);
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31 | 6af0bf9c | bellard | } |
32 | 6af0bf9c | bellard | |
33 | 6af0bf9c | bellard | void do_raise_exception_err (uint32_t exception, int error_code) |
34 | 6af0bf9c | bellard | { |
35 | 6af0bf9c | bellard | #if 1 |
36 | 6af0bf9c | bellard | if (logfile && exception < 0x100) |
37 | 6af0bf9c | bellard | fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
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38 | 6af0bf9c | bellard | #endif
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39 | 6af0bf9c | bellard | env->exception_index = exception; |
40 | 6af0bf9c | bellard | env->error_code = error_code; |
41 | 6af0bf9c | bellard | T0 = 0;
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42 | 6af0bf9c | bellard | cpu_loop_exit(); |
43 | 6af0bf9c | bellard | } |
44 | 6af0bf9c | bellard | |
45 | 6af0bf9c | bellard | void do_raise_exception (uint32_t exception)
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46 | 6af0bf9c | bellard | { |
47 | 6af0bf9c | bellard | do_raise_exception_err(exception, 0);
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48 | 6af0bf9c | bellard | } |
49 | 6af0bf9c | bellard | |
50 | 4ad40f36 | bellard | void do_restore_state (void *pc_ptr) |
51 | 4ad40f36 | bellard | { |
52 | 4ad40f36 | bellard | TranslationBlock *tb; |
53 | 4ad40f36 | bellard | unsigned long pc = (unsigned long) pc_ptr; |
54 | 4ad40f36 | bellard | |
55 | 4ad40f36 | bellard | tb = tb_find_pc (pc); |
56 | 4ad40f36 | bellard | cpu_restore_state (tb, env, pc, NULL);
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57 | 4ad40f36 | bellard | } |
58 | 4ad40f36 | bellard | |
59 | 4ad40f36 | bellard | void do_raise_exception_direct (uint32_t exception)
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60 | 4ad40f36 | bellard | { |
61 | 4ad40f36 | bellard | do_restore_state (GETPC ()); |
62 | 4ad40f36 | bellard | do_raise_exception_err (exception, 0);
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63 | 4ad40f36 | bellard | } |
64 | 4ad40f36 | bellard | |
65 | 6af0bf9c | bellard | #define MEMSUFFIX _raw
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66 | 6af0bf9c | bellard | #include "op_helper_mem.c" |
67 | 6af0bf9c | bellard | #undef MEMSUFFIX
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68 | 6af0bf9c | bellard | #if !defined(CONFIG_USER_ONLY)
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69 | 6af0bf9c | bellard | #define MEMSUFFIX _user
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70 | 6af0bf9c | bellard | #include "op_helper_mem.c" |
71 | 6af0bf9c | bellard | #undef MEMSUFFIX
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72 | 6af0bf9c | bellard | #define MEMSUFFIX _kernel
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73 | 6af0bf9c | bellard | #include "op_helper_mem.c" |
74 | 6af0bf9c | bellard | #undef MEMSUFFIX
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75 | 6af0bf9c | bellard | #endif
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76 | 6af0bf9c | bellard | |
77 | c570fd16 | ths | #ifdef MIPS_HAS_MIPS64
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78 | c570fd16 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
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79 | c570fd16 | ths | /* Those might call libgcc functions. */
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80 | c570fd16 | ths | void do_dsll (void) |
81 | c570fd16 | ths | { |
82 | c570fd16 | ths | T0 = T0 << T1; |
83 | c570fd16 | ths | } |
84 | c570fd16 | ths | |
85 | c570fd16 | ths | void do_dsll32 (void) |
86 | c570fd16 | ths | { |
87 | c570fd16 | ths | T0 = T0 << (T1 + 32);
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88 | c570fd16 | ths | } |
89 | c570fd16 | ths | |
90 | c570fd16 | ths | void do_dsra (void) |
91 | c570fd16 | ths | { |
92 | c570fd16 | ths | T0 = (int64_t)T0 >> T1; |
93 | c570fd16 | ths | } |
94 | c570fd16 | ths | |
95 | c570fd16 | ths | void do_dsra32 (void) |
96 | c570fd16 | ths | { |
97 | c570fd16 | ths | T0 = (int64_t)T0 >> (T1 + 32);
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98 | c570fd16 | ths | } |
99 | c570fd16 | ths | |
100 | c570fd16 | ths | void do_dsrl (void) |
101 | c570fd16 | ths | { |
102 | c570fd16 | ths | T0 = T0 >> T1; |
103 | c570fd16 | ths | } |
104 | c570fd16 | ths | |
105 | c570fd16 | ths | void do_dsrl32 (void) |
106 | c570fd16 | ths | { |
107 | c570fd16 | ths | T0 = T0 >> (T1 + 32);
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108 | c570fd16 | ths | } |
109 | c570fd16 | ths | |
110 | c570fd16 | ths | void do_drotr (void) |
111 | c570fd16 | ths | { |
112 | c570fd16 | ths | target_ulong tmp; |
113 | c570fd16 | ths | |
114 | c570fd16 | ths | if (T1) {
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115 | c570fd16 | ths | tmp = T0 << (0x40 - T1);
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116 | c570fd16 | ths | T0 = (T0 >> T1) | tmp; |
117 | c570fd16 | ths | } else
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118 | c570fd16 | ths | T0 = T1; |
119 | c570fd16 | ths | } |
120 | c570fd16 | ths | |
121 | c570fd16 | ths | void do_drotr32 (void) |
122 | c570fd16 | ths | { |
123 | c570fd16 | ths | target_ulong tmp; |
124 | c570fd16 | ths | |
125 | c570fd16 | ths | if (T1) {
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126 | c570fd16 | ths | tmp = T0 << (0x40 - (32 + T1)); |
127 | c570fd16 | ths | T0 = (T0 >> (32 + T1)) | tmp;
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128 | c570fd16 | ths | } else
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129 | c570fd16 | ths | T0 = T1; |
130 | c570fd16 | ths | } |
131 | c570fd16 | ths | |
132 | c570fd16 | ths | void do_dsllv (void) |
133 | c570fd16 | ths | { |
134 | c570fd16 | ths | T0 = T1 << (T0 & 0x3F);
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135 | c570fd16 | ths | } |
136 | c570fd16 | ths | |
137 | c570fd16 | ths | void do_dsrav (void) |
138 | c570fd16 | ths | { |
139 | c570fd16 | ths | T0 = (int64_t)T1 >> (T0 & 0x3F);
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140 | c570fd16 | ths | } |
141 | c570fd16 | ths | |
142 | c570fd16 | ths | void do_dsrlv (void) |
143 | c570fd16 | ths | { |
144 | c570fd16 | ths | T0 = T1 >> (T0 & 0x3F);
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145 | c570fd16 | ths | } |
146 | c570fd16 | ths | |
147 | c570fd16 | ths | void do_drotrv (void) |
148 | c570fd16 | ths | { |
149 | c570fd16 | ths | target_ulong tmp; |
150 | c570fd16 | ths | |
151 | c570fd16 | ths | T0 &= 0x3F;
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152 | c570fd16 | ths | if (T0) {
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153 | c570fd16 | ths | tmp = T1 << (0x40 - T0);
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154 | c570fd16 | ths | T0 = (T1 >> T0) | tmp; |
155 | c570fd16 | ths | } else
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156 | c570fd16 | ths | T0 = T1; |
157 | c570fd16 | ths | } |
158 | c570fd16 | ths | #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
159 | c570fd16 | ths | #endif /* MIPS_HAS_MIPS64 */ |
160 | c570fd16 | ths | |
161 | 6af0bf9c | bellard | /* 64 bits arithmetic for 32 bits hosts */
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162 | c570fd16 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
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163 | 6af0bf9c | bellard | static inline uint64_t get_HILO (void) |
164 | 6af0bf9c | bellard | { |
165 | 7495fd0f | ths | return (env->HI << 32) | (uint32_t)env->LO; |
166 | 6af0bf9c | bellard | } |
167 | 6af0bf9c | bellard | |
168 | 6af0bf9c | bellard | static inline void set_HILO (uint64_t HILO) |
169 | 6af0bf9c | bellard | { |
170 | 7495fd0f | ths | env->LO = (int32_t)HILO; |
171 | 5dc4b744 | ths | env->HI = (int32_t)(HILO >> 32);
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172 | 6af0bf9c | bellard | } |
173 | 6af0bf9c | bellard | |
174 | 6af0bf9c | bellard | void do_mult (void) |
175 | 6af0bf9c | bellard | { |
176 | 4ad40f36 | bellard | set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
177 | 6af0bf9c | bellard | } |
178 | 6af0bf9c | bellard | |
179 | 6af0bf9c | bellard | void do_multu (void) |
180 | 6af0bf9c | bellard | { |
181 | c570fd16 | ths | set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
182 | 6af0bf9c | bellard | } |
183 | 6af0bf9c | bellard | |
184 | 6af0bf9c | bellard | void do_madd (void) |
185 | 6af0bf9c | bellard | { |
186 | 6af0bf9c | bellard | int64_t tmp; |
187 | 6af0bf9c | bellard | |
188 | 4ad40f36 | bellard | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
189 | 6af0bf9c | bellard | set_HILO((int64_t)get_HILO() + tmp); |
190 | 6af0bf9c | bellard | } |
191 | 6af0bf9c | bellard | |
192 | 6af0bf9c | bellard | void do_maddu (void) |
193 | 6af0bf9c | bellard | { |
194 | 6af0bf9c | bellard | uint64_t tmp; |
195 | 6af0bf9c | bellard | |
196 | c570fd16 | ths | tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
197 | 6af0bf9c | bellard | set_HILO(get_HILO() + tmp); |
198 | 6af0bf9c | bellard | } |
199 | 6af0bf9c | bellard | |
200 | 6af0bf9c | bellard | void do_msub (void) |
201 | 6af0bf9c | bellard | { |
202 | 6af0bf9c | bellard | int64_t tmp; |
203 | 6af0bf9c | bellard | |
204 | 4ad40f36 | bellard | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
205 | 6af0bf9c | bellard | set_HILO((int64_t)get_HILO() - tmp); |
206 | 6af0bf9c | bellard | } |
207 | 6af0bf9c | bellard | |
208 | 6af0bf9c | bellard | void do_msubu (void) |
209 | 6af0bf9c | bellard | { |
210 | 6af0bf9c | bellard | uint64_t tmp; |
211 | 6af0bf9c | bellard | |
212 | c570fd16 | ths | tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
213 | 6af0bf9c | bellard | set_HILO(get_HILO() - tmp); |
214 | 6af0bf9c | bellard | } |
215 | 6af0bf9c | bellard | #endif
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216 | 6af0bf9c | bellard | |
217 | c570fd16 | ths | #ifdef MIPS_HAS_MIPS64
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218 | c570fd16 | ths | void do_dmult (void) |
219 | c570fd16 | ths | { |
220 | c570fd16 | ths | /* XXX */
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221 | c570fd16 | ths | set_HILO((int64_t)T0 * (int64_t)T1); |
222 | c570fd16 | ths | } |
223 | c570fd16 | ths | |
224 | c570fd16 | ths | void do_dmultu (void) |
225 | c570fd16 | ths | { |
226 | c570fd16 | ths | /* XXX */
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227 | c570fd16 | ths | set_HILO((uint64_t)T0 * (uint64_t)T1); |
228 | c570fd16 | ths | } |
229 | c570fd16 | ths | |
230 | c570fd16 | ths | void do_ddiv (void) |
231 | c570fd16 | ths | { |
232 | c570fd16 | ths | if (T1 != 0) { |
233 | c570fd16 | ths | env->LO = (int64_t)T0 / (int64_t)T1; |
234 | c570fd16 | ths | env->HI = (int64_t)T0 % (int64_t)T1; |
235 | c570fd16 | ths | } |
236 | c570fd16 | ths | } |
237 | c570fd16 | ths | |
238 | c570fd16 | ths | void do_ddivu (void) |
239 | c570fd16 | ths | { |
240 | c570fd16 | ths | if (T1 != 0) { |
241 | c570fd16 | ths | env->LO = T0 / T1; |
242 | c570fd16 | ths | env->HI = T0 % T1; |
243 | c570fd16 | ths | } |
244 | c570fd16 | ths | } |
245 | c570fd16 | ths | #endif
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246 | c570fd16 | ths | |
247 | 048f6b4d | bellard | #if defined(CONFIG_USER_ONLY)
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248 | 873eb012 | ths | void do_mfc0_random (void) |
249 | 048f6b4d | bellard | { |
250 | 873eb012 | ths | cpu_abort(env, "mfc0 random\n");
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251 | 048f6b4d | bellard | } |
252 | 873eb012 | ths | |
253 | 873eb012 | ths | void do_mfc0_count (void) |
254 | 873eb012 | ths | { |
255 | 873eb012 | ths | cpu_abort(env, "mfc0 count\n");
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256 | 873eb012 | ths | } |
257 | 873eb012 | ths | |
258 | 8c0fdd85 | ths | void cpu_mips_store_count(CPUState *env, uint32_t value)
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259 | 048f6b4d | bellard | { |
260 | 8c0fdd85 | ths | cpu_abort(env, "mtc0 count\n");
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261 | 8c0fdd85 | ths | } |
262 | 8c0fdd85 | ths | |
263 | 8c0fdd85 | ths | void cpu_mips_store_compare(CPUState *env, uint32_t value)
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264 | 8c0fdd85 | ths | { |
265 | 8c0fdd85 | ths | cpu_abort(env, "mtc0 compare\n");
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266 | 8c0fdd85 | ths | } |
267 | 8c0fdd85 | ths | |
268 | 4de9b249 | ths | void cpu_mips_update_irq(CPUState *env)
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269 | 4de9b249 | ths | { |
270 | 4de9b249 | ths | cpu_abort(env, "mtc0 status / mtc0 cause\n");
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271 | 4de9b249 | ths | } |
272 | 4de9b249 | ths | |
273 | 8c0fdd85 | ths | void do_mtc0_status_debug(uint32_t old, uint32_t val)
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274 | 8c0fdd85 | ths | { |
275 | 7a387fff | ths | cpu_abort(env, "mtc0 status debug\n");
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276 | 8c0fdd85 | ths | } |
277 | 8c0fdd85 | ths | |
278 | 7a387fff | ths | void do_mtc0_status_irqraise_debug (void) |
279 | 8c0fdd85 | ths | { |
280 | 7a387fff | ths | cpu_abort(env, "mtc0 status irqraise debug\n");
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281 | 048f6b4d | bellard | } |
282 | 048f6b4d | bellard | |
283 | 048f6b4d | bellard | void do_tlbwi (void) |
284 | 048f6b4d | bellard | { |
285 | 048f6b4d | bellard | cpu_abort(env, "tlbwi\n");
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286 | 048f6b4d | bellard | } |
287 | 048f6b4d | bellard | |
288 | 048f6b4d | bellard | void do_tlbwr (void) |
289 | 048f6b4d | bellard | { |
290 | 048f6b4d | bellard | cpu_abort(env, "tlbwr\n");
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291 | 048f6b4d | bellard | } |
292 | 048f6b4d | bellard | |
293 | 048f6b4d | bellard | void do_tlbp (void) |
294 | 048f6b4d | bellard | { |
295 | 048f6b4d | bellard | cpu_abort(env, "tlbp\n");
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296 | 048f6b4d | bellard | } |
297 | 048f6b4d | bellard | |
298 | 048f6b4d | bellard | void do_tlbr (void) |
299 | 048f6b4d | bellard | { |
300 | 048f6b4d | bellard | cpu_abort(env, "tlbr\n");
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301 | 048f6b4d | bellard | } |
302 | 873eb012 | ths | |
303 | 8c0fdd85 | ths | void cpu_mips_tlb_flush (CPUState *env, int flush_global) |
304 | 8c0fdd85 | ths | { |
305 | 8c0fdd85 | ths | cpu_abort(env, "mips_tlb_flush\n");
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306 | 8c0fdd85 | ths | } |
307 | 8c0fdd85 | ths | |
308 | 048f6b4d | bellard | #else
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309 | 048f6b4d | bellard | |
310 | 6af0bf9c | bellard | /* CP0 helpers */
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311 | 873eb012 | ths | void do_mfc0_random (void) |
312 | 6af0bf9c | bellard | { |
313 | 5dc4b744 | ths | T0 = (int32_t)cpu_mips_get_random(env); |
314 | 873eb012 | ths | } |
315 | 6af0bf9c | bellard | |
316 | 873eb012 | ths | void do_mfc0_count (void) |
317 | 873eb012 | ths | { |
318 | 5dc4b744 | ths | T0 = (int32_t)cpu_mips_get_count(env); |
319 | 6af0bf9c | bellard | } |
320 | 6af0bf9c | bellard | |
321 | 8c0fdd85 | ths | void do_mtc0_status_debug(uint32_t old, uint32_t val)
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322 | 6af0bf9c | bellard | { |
323 | 8c0fdd85 | ths | const uint32_t mask = 0x0000FF00; |
324 | 8c0fdd85 | ths | fprintf(logfile, "Status %08x => %08x Cause %08x (%08x %08x %08x)\n",
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325 | 8c0fdd85 | ths | old, val, env->CP0_Cause, old & mask, val & mask, |
326 | 8c0fdd85 | ths | env->CP0_Cause & mask); |
327 | 8c0fdd85 | ths | } |
328 | 8c0fdd85 | ths | |
329 | 8c0fdd85 | ths | void do_mtc0_status_irqraise_debug(void) |
330 | 8c0fdd85 | ths | { |
331 | 8c0fdd85 | ths | fprintf(logfile, "Raise pending IRQs\n");
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332 | 6af0bf9c | bellard | } |
333 | 6af0bf9c | bellard | |
334 | 6ea83fed | bellard | #ifdef MIPS_USES_FPU
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335 | 6ea83fed | bellard | #include "softfloat.h" |
336 | 6ea83fed | bellard | |
337 | 6ea83fed | bellard | void fpu_handle_exception(void) |
338 | 6ea83fed | bellard | { |
339 | 6ea83fed | bellard | #ifdef CONFIG_SOFTFLOAT
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340 | 6ea83fed | bellard | int flags = get_float_exception_flags(&env->fp_status);
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341 | 6ea83fed | bellard | unsigned int cpuflags = 0, enable, cause = 0; |
342 | 6ea83fed | bellard | |
343 | 6ea83fed | bellard | enable = GET_FP_ENABLE(env->fcr31); |
344 | 6ea83fed | bellard | |
345 | 6ea83fed | bellard | /* determine current flags */
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346 | 6ea83fed | bellard | if (flags & float_flag_invalid) {
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347 | 6ea83fed | bellard | cpuflags |= FP_INVALID; |
348 | 6ea83fed | bellard | cause |= FP_INVALID & enable; |
349 | 6ea83fed | bellard | } |
350 | 6ea83fed | bellard | if (flags & float_flag_divbyzero) {
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351 | 6ea83fed | bellard | cpuflags |= FP_DIV0; |
352 | 6ea83fed | bellard | cause |= FP_DIV0 & enable; |
353 | 6ea83fed | bellard | } |
354 | 6ea83fed | bellard | if (flags & float_flag_overflow) {
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355 | 6ea83fed | bellard | cpuflags |= FP_OVERFLOW; |
356 | 6ea83fed | bellard | cause |= FP_OVERFLOW & enable; |
357 | 6ea83fed | bellard | } |
358 | 6ea83fed | bellard | if (flags & float_flag_underflow) {
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359 | 6ea83fed | bellard | cpuflags |= FP_UNDERFLOW; |
360 | 6ea83fed | bellard | cause |= FP_UNDERFLOW & enable; |
361 | 6ea83fed | bellard | } |
362 | 6ea83fed | bellard | if (flags & float_flag_inexact) {
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363 | 6ea83fed | bellard | cpuflags |= FP_INEXACT; |
364 | 6ea83fed | bellard | cause |= FP_INEXACT & enable; |
365 | 6ea83fed | bellard | } |
366 | 6ea83fed | bellard | SET_FP_FLAGS(env->fcr31, cpuflags); |
367 | 6ea83fed | bellard | SET_FP_CAUSE(env->fcr31, cause); |
368 | 6ea83fed | bellard | #else
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369 | 6ea83fed | bellard | SET_FP_FLAGS(env->fcr31, 0);
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370 | 6ea83fed | bellard | SET_FP_CAUSE(env->fcr31, 0);
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371 | 6ea83fed | bellard | #endif
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372 | 6ea83fed | bellard | } |
373 | 6ea83fed | bellard | #endif /* MIPS_USES_FPU */ |
374 | 6ea83fed | bellard | |
375 | 6af0bf9c | bellard | /* TLB management */
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376 | 6af0bf9c | bellard | #if defined(MIPS_USES_R4K_TLB)
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377 | 814b9a47 | ths | void cpu_mips_tlb_flush (CPUState *env, int flush_global) |
378 | 814b9a47 | ths | { |
379 | 814b9a47 | ths | /* Flush qemu's TLB and discard all shadowed entries. */
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380 | 814b9a47 | ths | tlb_flush (env, flush_global); |
381 | 814b9a47 | ths | env->tlb_in_use = MIPS_TLB_NB; |
382 | 814b9a47 | ths | } |
383 | 814b9a47 | ths | |
384 | 814b9a47 | ths | static void mips_tlb_flush_extra (CPUState *env, int first) |
385 | 814b9a47 | ths | { |
386 | 814b9a47 | ths | /* Discard entries from env->tlb[first] onwards. */
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387 | 814b9a47 | ths | while (env->tlb_in_use > first) {
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388 | 2ee4aed8 | bellard | invalidate_tlb(env, --env->tlb_in_use, 0);
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389 | 814b9a47 | ths | } |
390 | 814b9a47 | ths | } |
391 | 814b9a47 | ths | |
392 | 98c1b82b | pbrook | static void fill_tlb (int idx) |
393 | 6af0bf9c | bellard | { |
394 | 6af0bf9c | bellard | tlb_t *tlb; |
395 | 6af0bf9c | bellard | |
396 | 6af0bf9c | bellard | /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
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397 | 6af0bf9c | bellard | tlb = &env->tlb[idx]; |
398 | 925fd0f2 | ths | tlb->VPN = env->CP0_EntryHi & ~(target_ulong)0x1FFF;
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399 | 98c1b82b | pbrook | tlb->ASID = env->CP0_EntryHi & 0xFF;
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400 | 3b1c8be4 | ths | tlb->PageMask = env->CP0_PageMask; |
401 | 6af0bf9c | bellard | tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
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402 | 98c1b82b | pbrook | tlb->V0 = (env->CP0_EntryLo0 & 2) != 0; |
403 | 98c1b82b | pbrook | tlb->D0 = (env->CP0_EntryLo0 & 4) != 0; |
404 | 98c1b82b | pbrook | tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7; |
405 | 6af0bf9c | bellard | tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12; |
406 | 98c1b82b | pbrook | tlb->V1 = (env->CP0_EntryLo1 & 2) != 0; |
407 | 98c1b82b | pbrook | tlb->D1 = (env->CP0_EntryLo1 & 4) != 0; |
408 | 98c1b82b | pbrook | tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7; |
409 | 6af0bf9c | bellard | tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12; |
410 | 6af0bf9c | bellard | } |
411 | 6af0bf9c | bellard | |
412 | 6af0bf9c | bellard | void do_tlbwi (void) |
413 | 6af0bf9c | bellard | { |
414 | 814b9a47 | ths | /* Discard cached TLB entries. We could avoid doing this if the
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415 | 814b9a47 | ths | tlbwi is just upgrading access permissions on the current entry;
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416 | 814b9a47 | ths | that might be a further win. */
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417 | 814b9a47 | ths | mips_tlb_flush_extra (env, MIPS_TLB_NB); |
418 | 814b9a47 | ths | |
419 | 9c2149c8 | ths | /* Wildly undefined effects for CP0_Index containing a too high value and
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420 | 7a962d30 | bellard | MIPS_TLB_NB not being a power of two. But so does real silicon. */
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421 | 9c2149c8 | ths | invalidate_tlb(env, env->CP0_Index & (MIPS_TLB_NB - 1), 0); |
422 | 9c2149c8 | ths | fill_tlb(env->CP0_Index & (MIPS_TLB_NB - 1));
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423 | 6af0bf9c | bellard | } |
424 | 6af0bf9c | bellard | |
425 | 6af0bf9c | bellard | void do_tlbwr (void) |
426 | 6af0bf9c | bellard | { |
427 | 6af0bf9c | bellard | int r = cpu_mips_get_random(env);
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428 | 6af0bf9c | bellard | |
429 | 2ee4aed8 | bellard | invalidate_tlb(env, r, 1);
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430 | 98c1b82b | pbrook | fill_tlb(r); |
431 | 6af0bf9c | bellard | } |
432 | 6af0bf9c | bellard | |
433 | 6af0bf9c | bellard | void do_tlbp (void) |
434 | 6af0bf9c | bellard | { |
435 | 6af0bf9c | bellard | tlb_t *tlb; |
436 | 6af0bf9c | bellard | target_ulong tag; |
437 | 6af0bf9c | bellard | uint8_t ASID; |
438 | 6af0bf9c | bellard | int i;
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439 | 6af0bf9c | bellard | |
440 | 5dc4b744 | ths | tag = env->CP0_EntryHi & (int32_t)0xFFFFE000;
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441 | 3d9fb9fe | bellard | ASID = env->CP0_EntryHi & 0xFF;
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442 | 3d9fb9fe | bellard | for (i = 0; i < MIPS_TLB_NB; i++) { |
443 | 6af0bf9c | bellard | tlb = &env->tlb[i]; |
444 | 6af0bf9c | bellard | /* Check ASID, virtual page number & size */
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445 | 6af0bf9c | bellard | if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) { |
446 | 6af0bf9c | bellard | /* TLB match */
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447 | 9c2149c8 | ths | env->CP0_Index = i; |
448 | 6af0bf9c | bellard | break;
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449 | 6af0bf9c | bellard | } |
450 | 6af0bf9c | bellard | } |
451 | 7a962d30 | bellard | if (i == MIPS_TLB_NB) {
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452 | 814b9a47 | ths | /* No match. Discard any shadow entries, if any of them match. */
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453 | 814b9a47 | ths | for (i = MIPS_TLB_NB; i < env->tlb_in_use; i++) {
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454 | 814b9a47 | ths | tlb = &env->tlb[i]; |
455 | 814b9a47 | ths | |
456 | 814b9a47 | ths | /* Check ASID, virtual page number & size */
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457 | 814b9a47 | ths | if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) { |
458 | 814b9a47 | ths | mips_tlb_flush_extra (env, i); |
459 | 814b9a47 | ths | break;
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460 | 814b9a47 | ths | } |
461 | 814b9a47 | ths | } |
462 | 814b9a47 | ths | |
463 | 9c2149c8 | ths | env->CP0_Index |= 0x80000000;
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464 | 6af0bf9c | bellard | } |
465 | 6af0bf9c | bellard | } |
466 | 6af0bf9c | bellard | |
467 | 6af0bf9c | bellard | void do_tlbr (void) |
468 | 6af0bf9c | bellard | { |
469 | 6af0bf9c | bellard | tlb_t *tlb; |
470 | 09c56b84 | pbrook | uint8_t ASID; |
471 | 6af0bf9c | bellard | |
472 | 09c56b84 | pbrook | ASID = env->CP0_EntryHi & 0xFF;
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473 | 9c2149c8 | ths | tlb = &env->tlb[env->CP0_Index & (MIPS_TLB_NB - 1)];
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474 | 4ad40f36 | bellard | |
475 | 4ad40f36 | bellard | /* If this will change the current ASID, flush qemu's TLB. */
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476 | 814b9a47 | ths | if (ASID != tlb->ASID)
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477 | 814b9a47 | ths | cpu_mips_tlb_flush (env, 1);
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478 | 814b9a47 | ths | |
479 | 814b9a47 | ths | mips_tlb_flush_extra(env, MIPS_TLB_NB); |
480 | 4ad40f36 | bellard | |
481 | 6af0bf9c | bellard | env->CP0_EntryHi = tlb->VPN | tlb->ASID; |
482 | 3b1c8be4 | ths | env->CP0_PageMask = tlb->PageMask; |
483 | 7495fd0f | ths | env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) | |
484 | 7495fd0f | ths | (tlb->C0 << 3) | (tlb->PFN[0] >> 6); |
485 | 7495fd0f | ths | env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) | |
486 | 7495fd0f | ths | (tlb->C1 << 3) | (tlb->PFN[1] >> 6); |
487 | 6af0bf9c | bellard | } |
488 | 6af0bf9c | bellard | #endif
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489 | 6af0bf9c | bellard | |
490 | 048f6b4d | bellard | #endif /* !CONFIG_USER_ONLY */ |
491 | 048f6b4d | bellard | |
492 | c570fd16 | ths | void dump_ldst (const unsigned char *func) |
493 | 6af0bf9c | bellard | { |
494 | 6af0bf9c | bellard | if (loglevel)
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495 | c570fd16 | ths | fprintf(logfile, "%s => " TLSZ " " TLSZ "\n", __func__, T0, T1); |
496 | 6af0bf9c | bellard | } |
497 | 6af0bf9c | bellard | |
498 | 6af0bf9c | bellard | void dump_sc (void) |
499 | 6af0bf9c | bellard | { |
500 | 6af0bf9c | bellard | if (loglevel) {
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501 | c570fd16 | ths | fprintf(logfile, "%s " TLSZ " at " TLSZ " (" TLSZ ")\n", __func__, |
502 | 6af0bf9c | bellard | T1, T0, env->CP0_LLAddr); |
503 | 6af0bf9c | bellard | } |
504 | 6af0bf9c | bellard | } |
505 | 6af0bf9c | bellard | |
506 | 6af0bf9c | bellard | void debug_eret (void) |
507 | 6af0bf9c | bellard | { |
508 | 6af0bf9c | bellard | if (loglevel) {
|
509 | c570fd16 | ths | fprintf(logfile, "ERET: pc " TLSZ " EPC " TLSZ " ErrorEPC " TLSZ " (%d)\n", |
510 | 6af0bf9c | bellard | env->PC, env->CP0_EPC, env->CP0_ErrorEPC, |
511 | 6af0bf9c | bellard | env->hflags & MIPS_HFLAG_ERL ? 1 : 0); |
512 | 6af0bf9c | bellard | } |
513 | 6af0bf9c | bellard | } |
514 | 6af0bf9c | bellard | |
515 | 6af0bf9c | bellard | void do_pmon (int function) |
516 | 6af0bf9c | bellard | { |
517 | 6af0bf9c | bellard | function /= 2;
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518 | 6af0bf9c | bellard | switch (function) {
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519 | 6af0bf9c | bellard | case 2: /* TODO: char inbyte(int waitflag); */ |
520 | 6af0bf9c | bellard | if (env->gpr[4] == 0) |
521 | 6af0bf9c | bellard | env->gpr[2] = -1; |
522 | 6af0bf9c | bellard | /* Fall through */
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523 | 6af0bf9c | bellard | case 11: /* TODO: char inbyte (void); */ |
524 | 6af0bf9c | bellard | env->gpr[2] = -1; |
525 | 6af0bf9c | bellard | break;
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526 | 6af0bf9c | bellard | case 3: |
527 | 6af0bf9c | bellard | case 12: |
528 | c570fd16 | ths | printf("%c", (char)(env->gpr[4] & 0xFF)); |
529 | 6af0bf9c | bellard | break;
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530 | 6af0bf9c | bellard | case 17: |
531 | 6af0bf9c | bellard | break;
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532 | 6af0bf9c | bellard | case 158: |
533 | 6af0bf9c | bellard | { |
534 | c570fd16 | ths | unsigned char *fmt = (void *)(unsigned long)env->gpr[4]; |
535 | 6af0bf9c | bellard | printf("%s", fmt);
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536 | 6af0bf9c | bellard | } |
537 | 6af0bf9c | bellard | break;
|
538 | 6af0bf9c | bellard | } |
539 | 6af0bf9c | bellard | } |
540 | e37e863f | bellard | |
541 | e37e863f | bellard | #if !defined(CONFIG_USER_ONLY)
|
542 | e37e863f | bellard | |
543 | 4ad40f36 | bellard | static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr); |
544 | 4ad40f36 | bellard | |
545 | e37e863f | bellard | #define MMUSUFFIX _mmu
|
546 | 4ad40f36 | bellard | #define ALIGNED_ONLY
|
547 | e37e863f | bellard | |
548 | e37e863f | bellard | #define SHIFT 0 |
549 | e37e863f | bellard | #include "softmmu_template.h" |
550 | e37e863f | bellard | |
551 | e37e863f | bellard | #define SHIFT 1 |
552 | e37e863f | bellard | #include "softmmu_template.h" |
553 | e37e863f | bellard | |
554 | e37e863f | bellard | #define SHIFT 2 |
555 | e37e863f | bellard | #include "softmmu_template.h" |
556 | e37e863f | bellard | |
557 | e37e863f | bellard | #define SHIFT 3 |
558 | e37e863f | bellard | #include "softmmu_template.h" |
559 | e37e863f | bellard | |
560 | 4ad40f36 | bellard | static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr) |
561 | 4ad40f36 | bellard | { |
562 | 4ad40f36 | bellard | env->CP0_BadVAddr = addr; |
563 | 4ad40f36 | bellard | do_restore_state (retaddr); |
564 | 4ad40f36 | bellard | do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
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565 | 4ad40f36 | bellard | } |
566 | 4ad40f36 | bellard | |
567 | e37e863f | bellard | void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr) |
568 | e37e863f | bellard | { |
569 | e37e863f | bellard | TranslationBlock *tb; |
570 | e37e863f | bellard | CPUState *saved_env; |
571 | e37e863f | bellard | unsigned long pc; |
572 | e37e863f | bellard | int ret;
|
573 | e37e863f | bellard | |
574 | e37e863f | bellard | /* XXX: hack to restore env in all cases, even if not called from
|
575 | e37e863f | bellard | generated code */
|
576 | e37e863f | bellard | saved_env = env; |
577 | e37e863f | bellard | env = cpu_single_env; |
578 | e37e863f | bellard | ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1);
|
579 | e37e863f | bellard | if (ret) {
|
580 | e37e863f | bellard | if (retaddr) {
|
581 | e37e863f | bellard | /* now we have a real cpu fault */
|
582 | e37e863f | bellard | pc = (unsigned long)retaddr; |
583 | e37e863f | bellard | tb = tb_find_pc(pc); |
584 | e37e863f | bellard | if (tb) {
|
585 | e37e863f | bellard | /* the PC is inside the translated code. It means that we have
|
586 | e37e863f | bellard | a virtual CPU fault */
|
587 | e37e863f | bellard | cpu_restore_state(tb, env, pc, NULL);
|
588 | e37e863f | bellard | } |
589 | e37e863f | bellard | } |
590 | e37e863f | bellard | do_raise_exception_err(env->exception_index, env->error_code); |
591 | e37e863f | bellard | } |
592 | e37e863f | bellard | env = saved_env; |
593 | e37e863f | bellard | } |
594 | e37e863f | bellard | |
595 | e37e863f | bellard | #endif |