Revision 925fd0f2 target-mips/op.c

b/target-mips/op.c
1340 1340 

  		





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    /* 1k pages not implemented */


  		





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    /* Ignore MIPS64 TLB for now */


  		





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    val = (int32_t)T0 & 0xFFFFE0FF;


  		





  
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    val = (target_ulong)(int32_t)T0 & ~(target_ulong)0x1F00;


  		





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    old = env->CP0_EntryHi;


  		





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    env->CP0_EntryHi = val;


  		





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    /* If the ASID changes, flush qemu's TLB.  */


  		












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