root / target-mips / helper.c @ 925fd0f2
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/*
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* MIPS emulation helpers for qemu.
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*
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* Copyright (c) 2004-2005 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <stdarg.h> |
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#include <stdlib.h> |
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#include <stdio.h> |
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#include <string.h> |
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#include <inttypes.h> |
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#include <signal.h> |
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#include <assert.h> |
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#include "cpu.h" |
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#include "exec-all.h" |
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enum {
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TLBRET_DIRTY = -4,
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TLBRET_INVALID = -3,
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TLBRET_NOMATCH = -2,
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TLBRET_BADADDR = -1,
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TLBRET_MATCH = 0
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}; |
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/* MIPS32 4K MMU emulation */
|
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#ifdef MIPS_USES_R4K_TLB
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static int map_address (CPUState *env, target_ulong *physical, int *prot, |
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target_ulong address, int rw, int access_type) |
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{
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uint8_t ASID = env->CP0_EntryHi & 0xFF;
|
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int i;
|
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|
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for (i = 0; i < env->tlb_in_use; i++) { |
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tlb_t *tlb = &env->tlb[i]; |
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/* 1k pages are not supported. */
|
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target_ulong mask = tlb->PageMask | 0x1FFF;
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target_ulong tag = address & ~mask; |
| 52 |
int n;
|
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|
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/* Check ASID, virtual page number & size */
|
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if ((tlb->G == 1 || tlb->ASID == ASID) && |
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tlb->VPN == tag) {
|
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/* TLB match */
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n = !!(address & mask & ~(mask >> 1));
|
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/* Check access rights */
|
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if (!(n ? tlb->V1 : tlb->V0))
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return TLBRET_INVALID;
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if (rw == 0 || (n ? tlb->D1 : tlb->D0)) { |
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*physical = tlb->PFN[n] | (address & (mask >> 1));
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*prot = PAGE_READ; |
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if (n ? tlb->D1 : tlb->D0)
|
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*prot |= PAGE_WRITE; |
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return TLBRET_MATCH;
|
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} |
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return TLBRET_DIRTY;
|
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} |
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} |
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return TLBRET_NOMATCH;
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} |
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#endif
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|
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static int get_physical_address (CPUState *env, target_ulong *physical, |
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int *prot, target_ulong address,
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int rw, int access_type) |
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{
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/* User mode can only access useg */
|
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int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
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int ret = TLBRET_MATCH;
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|
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#if 0
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if (logfile) {
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fprintf(logfile, "user mode %d h %08x\n",
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user_mode, env->hflags);
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}
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#endif
|
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if (user_mode && address > 0x7FFFFFFFUL) |
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return TLBRET_BADADDR;
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if (address < (int32_t)0x80000000UL) { |
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if (!(env->hflags & MIPS_HFLAG_ERL)) {
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#ifdef MIPS_USES_R4K_TLB
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ret = map_address(env, physical, prot, address, rw, access_type); |
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#else
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*physical = address + 0x40000000UL;
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*prot = PAGE_READ | PAGE_WRITE; |
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#endif
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} else {
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*physical = address; |
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*prot = PAGE_READ | PAGE_WRITE; |
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} |
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} else if (address < (int32_t)0xA0000000UL) { |
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/* kseg0 */
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/* XXX: check supervisor mode */
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*physical = address - (int32_t)0x80000000UL;
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*prot = PAGE_READ | PAGE_WRITE; |
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} else if (address < (int32_t)0xC0000000UL) { |
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/* kseg1 */
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/* XXX: check supervisor mode */
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*physical = address - (int32_t)0xA0000000UL;
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*prot = PAGE_READ | PAGE_WRITE; |
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} else if (address < (int32_t)0xE0000000UL) { |
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/* kseg2 */
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#ifdef MIPS_USES_R4K_TLB
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ret = map_address(env, physical, prot, address, rw, access_type); |
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#else
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*physical = address; |
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*prot = PAGE_READ | PAGE_WRITE; |
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#endif
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} else {
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/* kseg3 */
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/* XXX: check supervisor mode */
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/* XXX: debug segment is not emulated */
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#ifdef MIPS_USES_R4K_TLB
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ret = map_address(env, physical, prot, address, rw, access_type); |
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#else
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*physical = address; |
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*prot = PAGE_READ | PAGE_WRITE; |
| 131 |
#endif
|
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} |
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#if 0
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if (logfile) {
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fprintf(logfile, TLSZ " %d %d => " TLSZ " %d (%d)\n",
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address, rw, access_type, *physical, *prot, ret);
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}
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#endif
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return ret;
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} |
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|
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#if defined(CONFIG_USER_ONLY)
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target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
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{
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return addr;
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} |
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#else
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target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
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{
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target_ulong phys_addr; |
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int prot;
|
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|
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if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0) |
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return -1; |
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return phys_addr;
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} |
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|
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void cpu_mips_init_mmu (CPUState *env)
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{
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} |
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#endif /* !defined(CONFIG_USER_ONLY) */ |
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|
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int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
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int is_user, int is_softmmu) |
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{
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target_ulong physical; |
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int prot;
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int exception = 0, error_code = 0; |
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int access_type;
|
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int ret = 0; |
| 172 |
|
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if (logfile) {
|
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#if 0
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cpu_dump_state(env, logfile, fprintf, 0);
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#endif
|
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fprintf(logfile, "%s pc " TLSZ " ad " TLSZ " rw %d is_user %d smmu %d\n", |
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__func__, env->PC, address, rw, is_user, is_softmmu); |
| 179 |
} |
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|
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rw &= 1;
|
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|
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/* data access */
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/* XXX: put correct access by using cpu_restore_state()
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correctly */
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access_type = ACCESS_INT; |
| 187 |
if (env->user_mode_only) {
|
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/* user mode only emulation */
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ret = TLBRET_NOMATCH; |
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goto do_fault;
|
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} |
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ret = get_physical_address(env, &physical, &prot, |
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address, rw, access_type); |
| 194 |
if (logfile) {
|
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fprintf(logfile, "%s address=" TLSZ " ret %d physical " TLSZ " prot %d\n", |
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__func__, address, ret, physical, prot); |
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} |
| 198 |
if (ret == TLBRET_MATCH) {
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ret = tlb_set_page(env, address & TARGET_PAGE_MASK, |
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physical & TARGET_PAGE_MASK, prot, |
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is_user, is_softmmu); |
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} else if (ret < 0) { |
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do_fault:
|
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switch (ret) {
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default:
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case TLBRET_BADADDR:
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/* Reference to kernel address from user mode or supervisor mode */
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/* Reference to supervisor address from user mode */
|
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if (rw)
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exception = EXCP_AdES; |
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else
|
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exception = EXCP_AdEL; |
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break;
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case TLBRET_NOMATCH:
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/* No TLB match for a mapped address */
|
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if (rw)
|
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exception = EXCP_TLBS; |
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else
|
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exception = EXCP_TLBL; |
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error_code = 1;
|
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break;
|
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case TLBRET_INVALID:
|
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/* TLB match with no valid bit */
|
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if (rw)
|
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exception = EXCP_TLBS; |
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else
|
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exception = EXCP_TLBL; |
| 228 |
break;
|
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case TLBRET_DIRTY:
|
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/* TLB match but 'D' bit is cleared */
|
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exception = EXCP_LTLBL; |
| 232 |
break;
|
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|
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} |
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/* Raise exception */
|
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env->CP0_BadVAddr = address; |
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env->CP0_Context = (env->CP0_Context & 0xff800000) |
|
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((address >> 9) & 0x007ffff0); |
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env->CP0_EntryHi = |
| 240 |
(env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1)); |
| 241 |
env->exception_index = exception; |
| 242 |
env->error_code = error_code; |
| 243 |
ret = 1;
|
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} |
| 245 |
|
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return ret;
|
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} |
| 248 |
|
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#if defined(CONFIG_USER_ONLY)
|
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void do_interrupt (CPUState *env)
|
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{
|
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env->exception_index = EXCP_NONE; |
| 253 |
} |
| 254 |
#else
|
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void do_interrupt (CPUState *env)
|
| 256 |
{
|
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target_ulong offset; |
| 258 |
int cause = -1; |
| 259 |
|
| 260 |
if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
|
| 261 |
fprintf(logfile, "%s enter: PC " TLSZ " EPC " TLSZ " cause %d excp %d\n", |
| 262 |
__func__, env->PC, env->CP0_EPC, cause, env->exception_index); |
| 263 |
} |
| 264 |
if (env->exception_index == EXCP_EXT_INTERRUPT &&
|
| 265 |
(env->hflags & MIPS_HFLAG_DM)) |
| 266 |
env->exception_index = EXCP_DINT; |
| 267 |
offset = 0x180;
|
| 268 |
switch (env->exception_index) {
|
| 269 |
case EXCP_DSS:
|
| 270 |
env->CP0_Debug |= 1 << CP0DB_DSS;
|
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/* Debug single step cannot be raised inside a delay slot and
|
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* resume will always occur on the next instruction
|
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* (but we assume the pc has always been updated during
|
| 274 |
* code translation).
|
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*/
|
| 276 |
env->CP0_DEPC = env->PC; |
| 277 |
goto enter_debug_mode;
|
| 278 |
case EXCP_DINT:
|
| 279 |
env->CP0_Debug |= 1 << CP0DB_DINT;
|
| 280 |
goto set_DEPC;
|
| 281 |
case EXCP_DIB:
|
| 282 |
env->CP0_Debug |= 1 << CP0DB_DIB;
|
| 283 |
goto set_DEPC;
|
| 284 |
case EXCP_DBp:
|
| 285 |
env->CP0_Debug |= 1 << CP0DB_DBp;
|
| 286 |
goto set_DEPC;
|
| 287 |
case EXCP_DDBS:
|
| 288 |
env->CP0_Debug |= 1 << CP0DB_DDBS;
|
| 289 |
goto set_DEPC;
|
| 290 |
case EXCP_DDBL:
|
| 291 |
env->CP0_Debug |= 1 << CP0DB_DDBL;
|
| 292 |
goto set_DEPC;
|
| 293 |
set_DEPC:
|
| 294 |
if (env->hflags & MIPS_HFLAG_BMASK) {
|
| 295 |
/* If the exception was raised from a delay slot,
|
| 296 |
come back to the jump. */
|
| 297 |
env->CP0_DEPC = env->PC - 4;
|
| 298 |
env->hflags &= ~MIPS_HFLAG_BMASK; |
| 299 |
} else {
|
| 300 |
env->CP0_DEPC = env->PC; |
| 301 |
} |
| 302 |
enter_debug_mode:
|
| 303 |
env->hflags |= MIPS_HFLAG_DM; |
| 304 |
/* EJTAG probe trap enable is not implemented... */
|
| 305 |
env->PC = (int32_t)0xBFC00480;
|
| 306 |
break;
|
| 307 |
case EXCP_RESET:
|
| 308 |
cpu_reset(env); |
| 309 |
break;
|
| 310 |
case EXCP_SRESET:
|
| 311 |
env->CP0_Status = (1 << CP0St_SR);
|
| 312 |
env->CP0_WatchLo = 0;
|
| 313 |
goto set_error_EPC;
|
| 314 |
case EXCP_NMI:
|
| 315 |
env->CP0_Status = (1 << CP0St_NMI);
|
| 316 |
set_error_EPC:
|
| 317 |
if (env->hflags & MIPS_HFLAG_BMASK) {
|
| 318 |
/* If the exception was raised from a delay slot,
|
| 319 |
come back to the jump. */
|
| 320 |
env->CP0_ErrorEPC = env->PC - 4;
|
| 321 |
env->hflags &= ~MIPS_HFLAG_BMASK; |
| 322 |
} else {
|
| 323 |
env->CP0_ErrorEPC = env->PC; |
| 324 |
} |
| 325 |
env->hflags |= MIPS_HFLAG_ERL; |
| 326 |
env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV); |
| 327 |
env->PC = (int32_t)0xBFC00000;
|
| 328 |
break;
|
| 329 |
case EXCP_MCHECK:
|
| 330 |
cause = 24;
|
| 331 |
goto set_EPC;
|
| 332 |
case EXCP_EXT_INTERRUPT:
|
| 333 |
cause = 0;
|
| 334 |
if (env->CP0_Cause & (1 << CP0Ca_IV)) |
| 335 |
offset = 0x200;
|
| 336 |
goto set_EPC;
|
| 337 |
case EXCP_DWATCH:
|
| 338 |
cause = 23;
|
| 339 |
/* XXX: TODO: manage defered watch exceptions */
|
| 340 |
goto set_EPC;
|
| 341 |
case EXCP_AdEL:
|
| 342 |
case EXCP_AdES:
|
| 343 |
cause = 4;
|
| 344 |
goto set_EPC;
|
| 345 |
case EXCP_TLBL:
|
| 346 |
cause = 2;
|
| 347 |
if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL)) |
| 348 |
offset = 0x000;
|
| 349 |
goto set_EPC;
|
| 350 |
case EXCP_IBE:
|
| 351 |
cause = 6;
|
| 352 |
goto set_EPC;
|
| 353 |
case EXCP_DBE:
|
| 354 |
cause = 7;
|
| 355 |
goto set_EPC;
|
| 356 |
case EXCP_SYSCALL:
|
| 357 |
cause = 8;
|
| 358 |
goto set_EPC;
|
| 359 |
case EXCP_BREAK:
|
| 360 |
cause = 9;
|
| 361 |
goto set_EPC;
|
| 362 |
case EXCP_RI:
|
| 363 |
cause = 10;
|
| 364 |
goto set_EPC;
|
| 365 |
case EXCP_CpU:
|
| 366 |
cause = 11;
|
| 367 |
env->CP0_Cause = (env->CP0_Cause & ~0x03000000) | (env->error_code << 28); |
| 368 |
goto set_EPC;
|
| 369 |
case EXCP_OVERFLOW:
|
| 370 |
cause = 12;
|
| 371 |
goto set_EPC;
|
| 372 |
case EXCP_TRAP:
|
| 373 |
cause = 13;
|
| 374 |
goto set_EPC;
|
| 375 |
case EXCP_LTLBL:
|
| 376 |
cause = 1;
|
| 377 |
goto set_EPC;
|
| 378 |
case EXCP_TLBS:
|
| 379 |
cause = 3;
|
| 380 |
if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL)) |
| 381 |
offset = 0x000;
|
| 382 |
goto set_EPC;
|
| 383 |
set_EPC:
|
| 384 |
if (env->hflags & MIPS_HFLAG_BMASK) {
|
| 385 |
/* If the exception was raised from a delay slot,
|
| 386 |
come back to the jump. */
|
| 387 |
env->CP0_EPC = env->PC - 4;
|
| 388 |
env->CP0_Cause |= 0x80000000;
|
| 389 |
env->hflags &= ~MIPS_HFLAG_BMASK; |
| 390 |
} else {
|
| 391 |
env->CP0_EPC = env->PC; |
| 392 |
env->CP0_Cause &= ~0x80000000;
|
| 393 |
} |
| 394 |
if (env->CP0_Status & (1 << CP0St_BEV)) { |
| 395 |
env->PC = (int32_t)0xBFC00200;
|
| 396 |
} else {
|
| 397 |
env->PC = (int32_t)0x80000000;
|
| 398 |
} |
| 399 |
env->hflags |= MIPS_HFLAG_EXL; |
| 400 |
env->CP0_Status |= (1 << CP0St_EXL);
|
| 401 |
env->PC += offset; |
| 402 |
env->CP0_Cause = (env->CP0_Cause & ~0x7C) | (cause << 2); |
| 403 |
break;
|
| 404 |
default:
|
| 405 |
if (logfile) {
|
| 406 |
fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
|
| 407 |
env->exception_index); |
| 408 |
} |
| 409 |
printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
|
| 410 |
exit(1);
|
| 411 |
} |
| 412 |
if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
|
| 413 |
fprintf(logfile, "%s: PC " TLSZ " EPC " TLSZ " cause %d excp %d\n" |
| 414 |
" S %08x C %08x A " TLSZ " D " TLSZ "\n", |
| 415 |
__func__, env->PC, env->CP0_EPC, cause, env->exception_index, |
| 416 |
env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr, |
| 417 |
env->CP0_DEPC); |
| 418 |
} |
| 419 |
env->exception_index = EXCP_NONE; |
| 420 |
} |
| 421 |
#endif /* !defined(CONFIG_USER_ONLY) */ |
| 422 |
|
| 423 |
void invalidate_tlb (CPUState *env, int idx, int use_extra) |
| 424 |
{
|
| 425 |
tlb_t *tlb; |
| 426 |
target_ulong addr; |
| 427 |
target_ulong end; |
| 428 |
uint8_t ASID = env->CP0_EntryHi & 0xFF;
|
| 429 |
target_ulong mask; |
| 430 |
|
| 431 |
tlb = &env->tlb[idx]; |
| 432 |
/* The qemu TLB is flushed then the ASID changes, so no need to
|
| 433 |
flush these entries again. */
|
| 434 |
if (tlb->G == 0 && tlb->ASID != ASID) { |
| 435 |
return;
|
| 436 |
} |
| 437 |
|
| 438 |
if (use_extra && env->tlb_in_use < MIPS_TLB_MAX) {
|
| 439 |
/* For tlbwr, we can shadow the discarded entry into
|
| 440 |
a new (fake) TLB entry, as long as the guest can not
|
| 441 |
tell that it's there. */
|
| 442 |
env->tlb[env->tlb_in_use] = *tlb; |
| 443 |
env->tlb_in_use++; |
| 444 |
return;
|
| 445 |
} |
| 446 |
|
| 447 |
/* 1k pages are not supported. */
|
| 448 |
mask = tlb->PageMask | 0x1FFF;
|
| 449 |
if (tlb->V0) {
|
| 450 |
addr = tlb->VPN; |
| 451 |
end = addr | (mask >> 1);
|
| 452 |
while (addr < end) {
|
| 453 |
tlb_flush_page (env, addr); |
| 454 |
addr += TARGET_PAGE_SIZE; |
| 455 |
} |
| 456 |
} |
| 457 |
if (tlb->V1) {
|
| 458 |
addr = tlb->VPN | ((mask >> 1) + 1); |
| 459 |
addr = tlb->VPN + TARGET_PAGE_SIZE; |
| 460 |
end = addr | mask; |
| 461 |
while (addr < end) {
|
| 462 |
tlb_flush_page (env, addr); |
| 463 |
addr += TARGET_PAGE_SIZE; |
| 464 |
} |
| 465 |
} |
| 466 |
} |