Revision 92af06d2 target-mips/op.c
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#include "op_mem.c" |
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#undef MEMSUFFIX |
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#endif |
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/* 64 bits arithmetic */ |
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#if TARGET_LONG_BITS > HOST_LONG_BITS |
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void op_madd (void) |
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{ |
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CALL_FROM_TB0(do_madd); |
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FORCE_RET(); |
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} |
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void op_maddu (void) |
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{ |
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CALL_FROM_TB0(do_maddu); |
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FORCE_RET(); |
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} |
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void op_msub (void) |
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{ |
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CALL_FROM_TB0(do_msub); |
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FORCE_RET(); |
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} |
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void op_msubu (void) |
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{ |
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CALL_FROM_TB0(do_msubu); |
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FORCE_RET(); |
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} |
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/* Multiplication variants of the vr54xx. */ |
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void op_muls (void) |
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{ |
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CALL_FROM_TB0(do_muls); |
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FORCE_RET(); |
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} |
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void op_mulsu (void) |
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{ |
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CALL_FROM_TB0(do_mulsu); |
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FORCE_RET(); |
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} |
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void op_macc (void) |
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{ |
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CALL_FROM_TB0(do_macc); |
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FORCE_RET(); |
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} |
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void op_macchi (void) |
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{ |
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CALL_FROM_TB0(do_macchi); |
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FORCE_RET(); |
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} |
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void op_maccu (void) |
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{ |
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CALL_FROM_TB0(do_maccu); |
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FORCE_RET(); |
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} |
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void op_macchiu (void) |
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{ |
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CALL_FROM_TB0(do_macchiu); |
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FORCE_RET(); |
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} |
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void op_msac (void) |
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{ |
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CALL_FROM_TB0(do_msac); |
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FORCE_RET(); |
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} |
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void op_msachi (void) |
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{ |
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CALL_FROM_TB0(do_msachi); |
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FORCE_RET(); |
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} |
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void op_msacu (void) |
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{ |
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CALL_FROM_TB0(do_msacu); |
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FORCE_RET(); |
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} |
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void op_msachiu (void) |
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{ |
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CALL_FROM_TB0(do_msachiu); |
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FORCE_RET(); |
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} |
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void op_mulhi (void) |
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{ |
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CALL_FROM_TB0(do_mulhi); |
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FORCE_RET(); |
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} |
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void op_mulhiu (void) |
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{ |
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CALL_FROM_TB0(do_mulhiu); |
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FORCE_RET(); |
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} |
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void op_mulshi (void) |
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{ |
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CALL_FROM_TB0(do_mulshi); |
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FORCE_RET(); |
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} |
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void op_mulshiu (void) |
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{ |
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CALL_FROM_TB0(do_mulshiu); |
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FORCE_RET(); |
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} |
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#else /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
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static always_inline uint64_t get_HILO (void) |
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{ |
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return ((uint64_t)env->HI[env->current_tc][0] << 32) | |
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((uint64_t)(uint32_t)env->LO[env->current_tc][0]); |
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} |
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static always_inline void set_HILO (uint64_t HILO) |
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{ |
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env->LO[env->current_tc][0] = (int32_t)(HILO & 0xFFFFFFFF); |
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env->HI[env->current_tc][0] = (int32_t)(HILO >> 32); |
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} |
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static always_inline void set_HIT0_LO (uint64_t HILO) |
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{ |
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env->LO[env->current_tc][0] = (int32_t)(HILO & 0xFFFFFFFF); |
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T0 = env->HI[env->current_tc][0] = (int32_t)(HILO >> 32); |
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} |
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static always_inline void set_HI_LOT0 (uint64_t HILO) |
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{ |
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T0 = env->LO[env->current_tc][0] = (int32_t)(HILO & 0xFFFFFFFF); |
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env->HI[env->current_tc][0] = (int32_t)(HILO >> 32); |
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} |
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/* Multiplication variants of the vr54xx. */ |
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void op_muls (void) |
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{ |
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set_HI_LOT0(0 - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); |
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FORCE_RET(); |
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} |
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void op_mulsu (void) |
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{ |
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set_HI_LOT0(0 - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); |
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FORCE_RET(); |
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} |
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void op_macc (void) |
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{ |
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set_HI_LOT0(get_HILO() + ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); |
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FORCE_RET(); |
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} |
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void op_macchi (void) |
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{ |
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set_HIT0_LO(get_HILO() + ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); |
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FORCE_RET(); |
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} |
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void op_maccu (void) |
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{ |
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set_HI_LOT0(get_HILO() + ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); |
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FORCE_RET(); |
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} |
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void op_macchiu (void) |
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{ |
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set_HIT0_LO(get_HILO() + ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); |
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FORCE_RET(); |
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} |
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void op_msac (void) |
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{ |
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set_HI_LOT0(get_HILO() - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); |
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FORCE_RET(); |
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} |
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void op_msachi (void) |
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{ |
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set_HIT0_LO(get_HILO() - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); |
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FORCE_RET(); |
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} |
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void op_msacu (void) |
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{ |
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set_HI_LOT0(get_HILO() - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); |
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FORCE_RET(); |
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} |
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void op_msachiu (void) |
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{ |
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set_HIT0_LO(get_HILO() - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); |
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FORCE_RET(); |
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} |
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void op_mulhi (void) |
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{ |
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set_HIT0_LO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
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FORCE_RET(); |
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} |
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void op_mulhiu (void) |
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{ |
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set_HIT0_LO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
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FORCE_RET(); |
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} |
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void op_mulshi (void) |
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{ |
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set_HIT0_LO(0 - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); |
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FORCE_RET(); |
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} |
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void op_mulshiu (void) |
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{ |
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set_HIT0_LO(0 - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); |
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FORCE_RET(); |
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} |
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#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
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